tegra186-cpufreq.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
  4. */
  5. #include <linux/cpufreq.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <soc/tegra/bpmp.h>
  11. #include <soc/tegra/bpmp-abi.h>
  12. #define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4)
  13. #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
  14. #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
  15. #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
  16. struct tegra186_cpufreq_cluster_info {
  17. unsigned long offset;
  18. int cpus[4];
  19. unsigned int bpmp_cluster_id;
  20. };
  21. #define NO_CPU -1
  22. static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
  23. /* Denver cluster */
  24. {
  25. .offset = SZ_64K * 7,
  26. .cpus = { 1, 2, NO_CPU, NO_CPU },
  27. .bpmp_cluster_id = 0,
  28. },
  29. /* A57 cluster */
  30. {
  31. .offset = SZ_64K * 6,
  32. .cpus = { 0, 3, 4, 5 },
  33. .bpmp_cluster_id = 1,
  34. },
  35. };
  36. struct tegra186_cpufreq_cluster {
  37. const struct tegra186_cpufreq_cluster_info *info;
  38. struct cpufreq_frequency_table *table;
  39. u32 ref_clk_khz;
  40. u32 div;
  41. };
  42. struct tegra186_cpufreq_data {
  43. void __iomem *regs;
  44. size_t num_clusters;
  45. struct tegra186_cpufreq_cluster *clusters;
  46. };
  47. static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
  48. {
  49. struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
  50. unsigned int i;
  51. for (i = 0; i < data->num_clusters; i++) {
  52. struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
  53. const struct tegra186_cpufreq_cluster_info *info =
  54. cluster->info;
  55. int core;
  56. for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
  57. if (info->cpus[core] == policy->cpu)
  58. break;
  59. }
  60. if (core == ARRAY_SIZE(info->cpus))
  61. continue;
  62. policy->driver_data =
  63. data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
  64. policy->freq_table = cluster->table;
  65. break;
  66. }
  67. policy->cpuinfo.transition_latency = 300 * 1000;
  68. return 0;
  69. }
  70. static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
  71. unsigned int index)
  72. {
  73. struct cpufreq_frequency_table *tbl = policy->freq_table + index;
  74. void __iomem *edvd_reg = policy->driver_data;
  75. u32 edvd_val = tbl->driver_data;
  76. writel(edvd_val, edvd_reg);
  77. return 0;
  78. }
  79. static unsigned int tegra186_cpufreq_get(unsigned int cpu)
  80. {
  81. struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
  82. struct cpufreq_policy *policy;
  83. void __iomem *edvd_reg;
  84. unsigned int i, freq = 0;
  85. u32 ndiv;
  86. policy = cpufreq_cpu_get(cpu);
  87. if (!policy)
  88. return 0;
  89. edvd_reg = policy->driver_data;
  90. ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
  91. for (i = 0; i < data->num_clusters; i++) {
  92. struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
  93. int core;
  94. for (core = 0; core < ARRAY_SIZE(cluster->info->cpus); core++) {
  95. if (cluster->info->cpus[core] != policy->cpu)
  96. continue;
  97. freq = (cluster->ref_clk_khz * ndiv) / cluster->div;
  98. goto out;
  99. }
  100. }
  101. out:
  102. cpufreq_cpu_put(policy);
  103. return freq;
  104. }
  105. static struct cpufreq_driver tegra186_cpufreq_driver = {
  106. .name = "tegra186",
  107. .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
  108. CPUFREQ_NEED_INITIAL_FREQ_CHECK,
  109. .get = tegra186_cpufreq_get,
  110. .verify = cpufreq_generic_frequency_table_verify,
  111. .target_index = tegra186_cpufreq_set_target,
  112. .init = tegra186_cpufreq_init,
  113. .attr = cpufreq_generic_attr,
  114. };
  115. static struct cpufreq_frequency_table *init_vhint_table(
  116. struct platform_device *pdev, struct tegra_bpmp *bpmp,
  117. struct tegra186_cpufreq_cluster *cluster)
  118. {
  119. struct cpufreq_frequency_table *table;
  120. struct mrq_cpu_vhint_request req;
  121. struct tegra_bpmp_message msg;
  122. struct cpu_vhint_data *data;
  123. int err, i, j, num_rates = 0;
  124. dma_addr_t phys;
  125. void *virt;
  126. virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
  127. GFP_KERNEL);
  128. if (!virt)
  129. return ERR_PTR(-ENOMEM);
  130. data = (struct cpu_vhint_data *)virt;
  131. memset(&req, 0, sizeof(req));
  132. req.addr = phys;
  133. req.cluster_id = cluster->info->bpmp_cluster_id;
  134. memset(&msg, 0, sizeof(msg));
  135. msg.mrq = MRQ_CPU_VHINT;
  136. msg.tx.data = &req;
  137. msg.tx.size = sizeof(req);
  138. err = tegra_bpmp_transfer(bpmp, &msg);
  139. if (err) {
  140. table = ERR_PTR(err);
  141. goto free;
  142. }
  143. for (i = data->vfloor; i <= data->vceil; i++) {
  144. u16 ndiv = data->ndiv[i];
  145. if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
  146. continue;
  147. /* Only store lowest voltage index for each rate */
  148. if (i > 0 && ndiv == data->ndiv[i - 1])
  149. continue;
  150. num_rates++;
  151. }
  152. table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
  153. GFP_KERNEL);
  154. if (!table) {
  155. table = ERR_PTR(-ENOMEM);
  156. goto free;
  157. }
  158. cluster->ref_clk_khz = data->ref_clk_hz / 1000;
  159. cluster->div = data->pdiv * data->mdiv;
  160. for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
  161. struct cpufreq_frequency_table *point;
  162. u16 ndiv = data->ndiv[i];
  163. u32 edvd_val = 0;
  164. if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
  165. continue;
  166. /* Only store lowest voltage index for each rate */
  167. if (i > 0 && ndiv == data->ndiv[i - 1])
  168. continue;
  169. edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
  170. edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
  171. point = &table[j++];
  172. point->driver_data = edvd_val;
  173. point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
  174. }
  175. table[j].frequency = CPUFREQ_TABLE_END;
  176. free:
  177. dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
  178. return table;
  179. }
  180. static int tegra186_cpufreq_probe(struct platform_device *pdev)
  181. {
  182. struct tegra186_cpufreq_data *data;
  183. struct tegra_bpmp *bpmp;
  184. unsigned int i = 0, err;
  185. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  186. if (!data)
  187. return -ENOMEM;
  188. data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
  189. sizeof(*data->clusters), GFP_KERNEL);
  190. if (!data->clusters)
  191. return -ENOMEM;
  192. data->num_clusters = ARRAY_SIZE(tegra186_clusters);
  193. bpmp = tegra_bpmp_get(&pdev->dev);
  194. if (IS_ERR(bpmp))
  195. return PTR_ERR(bpmp);
  196. data->regs = devm_platform_ioremap_resource(pdev, 0);
  197. if (IS_ERR(data->regs)) {
  198. err = PTR_ERR(data->regs);
  199. goto put_bpmp;
  200. }
  201. for (i = 0; i < data->num_clusters; i++) {
  202. struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
  203. cluster->info = &tegra186_clusters[i];
  204. cluster->table = init_vhint_table(pdev, bpmp, cluster);
  205. if (IS_ERR(cluster->table)) {
  206. err = PTR_ERR(cluster->table);
  207. goto put_bpmp;
  208. }
  209. }
  210. tegra186_cpufreq_driver.driver_data = data;
  211. err = cpufreq_register_driver(&tegra186_cpufreq_driver);
  212. put_bpmp:
  213. tegra_bpmp_put(bpmp);
  214. return err;
  215. }
  216. static int tegra186_cpufreq_remove(struct platform_device *pdev)
  217. {
  218. cpufreq_unregister_driver(&tegra186_cpufreq_driver);
  219. return 0;
  220. }
  221. static const struct of_device_id tegra186_cpufreq_of_match[] = {
  222. { .compatible = "nvidia,tegra186-ccplex-cluster", },
  223. { }
  224. };
  225. MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
  226. static struct platform_driver tegra186_cpufreq_platform_driver = {
  227. .driver = {
  228. .name = "tegra186-cpufreq",
  229. .of_match_table = tegra186_cpufreq_of_match,
  230. },
  231. .probe = tegra186_cpufreq_probe,
  232. .remove = tegra186_cpufreq_remove,
  233. };
  234. module_platform_driver(tegra186_cpufreq_platform_driver);
  235. MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
  236. MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
  237. MODULE_LICENSE("GPL v2");