sc520_freq.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sc520_freq.c: cpufreq driver for the AMD Elan sc520
  4. *
  5. * Copyright (C) 2005 Sean Young <sean@mess.org>
  6. *
  7. * Based on elanfreq.c
  8. *
  9. * 2005-03-30: - initial revision
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/cpufreq.h>
  17. #include <linux/timex.h>
  18. #include <linux/io.h>
  19. #include <asm/cpu_device_id.h>
  20. #include <asm/msr.h>
  21. #define MMCR_BASE 0xfffef000 /* The default base address */
  22. #define OFFS_CPUCTL 0x2 /* CPU Control Register */
  23. static __u8 __iomem *cpuctl;
  24. static struct cpufreq_frequency_table sc520_freq_table[] = {
  25. {0, 0x01, 100000},
  26. {0, 0x02, 133000},
  27. {0, 0, CPUFREQ_TABLE_END},
  28. };
  29. static unsigned int sc520_freq_get_cpu_frequency(unsigned int cpu)
  30. {
  31. u8 clockspeed_reg = *cpuctl;
  32. switch (clockspeed_reg & 0x03) {
  33. default:
  34. pr_err("error: cpuctl register has unexpected value %02x\n",
  35. clockspeed_reg);
  36. case 0x01:
  37. return 100000;
  38. case 0x02:
  39. return 133000;
  40. }
  41. }
  42. static int sc520_freq_target(struct cpufreq_policy *policy, unsigned int state)
  43. {
  44. u8 clockspeed_reg;
  45. local_irq_disable();
  46. clockspeed_reg = *cpuctl & ~0x03;
  47. *cpuctl = clockspeed_reg | sc520_freq_table[state].driver_data;
  48. local_irq_enable();
  49. return 0;
  50. }
  51. /*
  52. * Module init and exit code
  53. */
  54. static int sc520_freq_cpu_init(struct cpufreq_policy *policy)
  55. {
  56. struct cpuinfo_x86 *c = &cpu_data(0);
  57. /* capability check */
  58. if (c->x86_vendor != X86_VENDOR_AMD ||
  59. c->x86 != 4 || c->x86_model != 9)
  60. return -ENODEV;
  61. /* cpuinfo and default policy values */
  62. policy->cpuinfo.transition_latency = 1000000; /* 1ms */
  63. policy->freq_table = sc520_freq_table;
  64. return 0;
  65. }
  66. static struct cpufreq_driver sc520_freq_driver = {
  67. .get = sc520_freq_get_cpu_frequency,
  68. .verify = cpufreq_generic_frequency_table_verify,
  69. .target_index = sc520_freq_target,
  70. .init = sc520_freq_cpu_init,
  71. .name = "sc520_freq",
  72. .attr = cpufreq_generic_attr,
  73. };
  74. static const struct x86_cpu_id sc520_ids[] = {
  75. X86_MATCH_VENDOR_FAM_MODEL(AMD, 4, 9, NULL),
  76. {}
  77. };
  78. MODULE_DEVICE_TABLE(x86cpu, sc520_ids);
  79. static int __init sc520_freq_init(void)
  80. {
  81. int err;
  82. if (!x86_match_cpu(sc520_ids))
  83. return -ENODEV;
  84. cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1);
  85. if (!cpuctl) {
  86. pr_err("sc520_freq: error: failed to remap memory\n");
  87. return -ENOMEM;
  88. }
  89. err = cpufreq_register_driver(&sc520_freq_driver);
  90. if (err)
  91. iounmap(cpuctl);
  92. return err;
  93. }
  94. static void __exit sc520_freq_exit(void)
  95. {
  96. cpufreq_unregister_driver(&sc520_freq_driver);
  97. iounmap(cpuctl);
  98. }
  99. MODULE_LICENSE("GPL");
  100. MODULE_AUTHOR("Sean Young <sean@mess.org>");
  101. MODULE_DESCRIPTION("cpufreq driver for AMD's Elan sc520 CPU");
  102. module_init(sc520_freq_init);
  103. module_exit(sc520_freq_exit);