sa1110-cpufreq.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-sa1100/cpu-sa1110.c
  4. *
  5. * Copyright (C) 2001 Russell King
  6. *
  7. * Note: there are two erratas that apply to the SA1110 here:
  8. * 7 - SDRAM auto-power-up failure (rev A0)
  9. * 13 - Corruption of internal register reads/writes following
  10. * SDRAM reads (rev A0, B0, B1)
  11. *
  12. * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
  13. *
  14. * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
  15. */
  16. #include <linux/cpufreq.h>
  17. #include <linux/delay.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/kernel.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/types.h>
  23. #include <asm/cputype.h>
  24. #include <asm/mach-types.h>
  25. #include <mach/generic.h>
  26. #include <mach/hardware.h>
  27. #undef DEBUG
  28. struct sdram_params {
  29. const char name[20];
  30. u_char rows; /* bits */
  31. u_char cas_latency; /* cycles */
  32. u_char tck; /* clock cycle time (ns) */
  33. u_char trcd; /* activate to r/w (ns) */
  34. u_char trp; /* precharge to activate (ns) */
  35. u_char twr; /* write recovery time (ns) */
  36. u_short refresh; /* refresh time for array (us) */
  37. };
  38. struct sdram_info {
  39. u_int mdcnfg;
  40. u_int mdrefr;
  41. u_int mdcas[3];
  42. };
  43. static struct sdram_params sdram_tbl[] __initdata = {
  44. { /* Toshiba TC59SM716 CL2 */
  45. .name = "TC59SM716-CL2",
  46. .rows = 12,
  47. .tck = 10,
  48. .trcd = 20,
  49. .trp = 20,
  50. .twr = 10,
  51. .refresh = 64000,
  52. .cas_latency = 2,
  53. }, { /* Toshiba TC59SM716 CL3 */
  54. .name = "TC59SM716-CL3",
  55. .rows = 12,
  56. .tck = 8,
  57. .trcd = 20,
  58. .trp = 20,
  59. .twr = 8,
  60. .refresh = 64000,
  61. .cas_latency = 3,
  62. }, { /* Samsung K4S641632D TC75 */
  63. .name = "K4S641632D",
  64. .rows = 14,
  65. .tck = 9,
  66. .trcd = 27,
  67. .trp = 20,
  68. .twr = 9,
  69. .refresh = 64000,
  70. .cas_latency = 3,
  71. }, { /* Samsung K4S281632B-1H */
  72. .name = "K4S281632B-1H",
  73. .rows = 12,
  74. .tck = 10,
  75. .trp = 20,
  76. .twr = 10,
  77. .refresh = 64000,
  78. .cas_latency = 3,
  79. }, { /* Samsung KM416S4030CT */
  80. .name = "KM416S4030CT",
  81. .rows = 13,
  82. .tck = 8,
  83. .trcd = 24, /* 3 CLKs */
  84. .trp = 24, /* 3 CLKs */
  85. .twr = 16, /* Trdl: 2 CLKs */
  86. .refresh = 64000,
  87. .cas_latency = 3,
  88. }, { /* Winbond W982516AH75L CL3 */
  89. .name = "W982516AH75L",
  90. .rows = 16,
  91. .tck = 8,
  92. .trcd = 20,
  93. .trp = 20,
  94. .twr = 8,
  95. .refresh = 64000,
  96. .cas_latency = 3,
  97. }, { /* Micron MT48LC8M16A2TG-75 */
  98. .name = "MT48LC8M16A2TG-75",
  99. .rows = 12,
  100. .tck = 8,
  101. .trcd = 20,
  102. .trp = 20,
  103. .twr = 8,
  104. .refresh = 64000,
  105. .cas_latency = 3,
  106. },
  107. };
  108. static struct sdram_params sdram_params;
  109. /*
  110. * Given a period in ns and frequency in khz, calculate the number of
  111. * cycles of frequency in period. Note that we round up to the next
  112. * cycle, even if we are only slightly over.
  113. */
  114. static inline u_int ns_to_cycles(u_int ns, u_int khz)
  115. {
  116. return (ns * khz + 999999) / 1000000;
  117. }
  118. /*
  119. * Create the MDCAS register bit pattern.
  120. */
  121. static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
  122. {
  123. u_int shift;
  124. rcd = 2 * rcd - 1;
  125. shift = delayed + 1 + rcd;
  126. mdcas[0] = (1 << rcd) - 1;
  127. mdcas[0] |= 0x55555555 << shift;
  128. mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
  129. }
  130. static void
  131. sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
  132. struct sdram_params *sdram)
  133. {
  134. u_int mem_khz, sd_khz, trp, twr;
  135. mem_khz = cpu_khz / 2;
  136. sd_khz = mem_khz;
  137. /*
  138. * If SDCLK would invalidate the SDRAM timings,
  139. * run SDCLK at half speed.
  140. *
  141. * CPU steppings prior to B2 must either run the memory at
  142. * half speed or use delayed read latching (errata 13).
  143. */
  144. if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
  145. (read_cpuid_revision() < ARM_CPU_REV_SA1110_B2 && sd_khz < 62000))
  146. sd_khz /= 2;
  147. sd->mdcnfg = MDCNFG & 0x007f007f;
  148. twr = ns_to_cycles(sdram->twr, mem_khz);
  149. /* trp should always be >1 */
  150. trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
  151. if (trp < 1)
  152. trp = 1;
  153. sd->mdcnfg |= trp << 8;
  154. sd->mdcnfg |= trp << 24;
  155. sd->mdcnfg |= sdram->cas_latency << 12;
  156. sd->mdcnfg |= sdram->cas_latency << 28;
  157. sd->mdcnfg |= twr << 14;
  158. sd->mdcnfg |= twr << 30;
  159. sd->mdrefr = MDREFR & 0xffbffff0;
  160. sd->mdrefr |= 7;
  161. if (sd_khz != mem_khz)
  162. sd->mdrefr |= MDREFR_K1DB2;
  163. /* initial number of '1's in MDCAS + 1 */
  164. set_mdcas(sd->mdcas, sd_khz >= 62000,
  165. ns_to_cycles(sdram->trcd, mem_khz));
  166. #ifdef DEBUG
  167. printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
  168. sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
  169. sd->mdcas[2]);
  170. #endif
  171. }
  172. /*
  173. * Set the SDRAM refresh rate.
  174. */
  175. static inline void sdram_set_refresh(u_int dri)
  176. {
  177. MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
  178. (void) MDREFR;
  179. }
  180. /*
  181. * Update the refresh period. We do this such that we always refresh
  182. * the SDRAMs within their permissible period. The refresh period is
  183. * always a multiple of the memory clock (fixed at cpu_clock / 2).
  184. *
  185. * FIXME: we don't currently take account of burst accesses here,
  186. * but neither do Intels DM nor Angel.
  187. */
  188. static void
  189. sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
  190. {
  191. u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
  192. u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
  193. #ifdef DEBUG
  194. mdelay(250);
  195. printk(KERN_DEBUG "new dri value = %d\n", dri);
  196. #endif
  197. sdram_set_refresh(dri);
  198. }
  199. /*
  200. * Ok, set the CPU frequency.
  201. */
  202. static int sa1110_target(struct cpufreq_policy *policy, unsigned int ppcr)
  203. {
  204. struct sdram_params *sdram = &sdram_params;
  205. struct sdram_info sd;
  206. unsigned long flags;
  207. unsigned int unused;
  208. sdram_calculate_timing(&sd, sa11x0_freq_table[ppcr].frequency, sdram);
  209. #if 0
  210. /*
  211. * These values are wrong according to the SA1110 documentation
  212. * and errata, but they seem to work. Need to get a storage
  213. * scope on to the SDRAM signals to work out why.
  214. */
  215. if (policy->max < 147500) {
  216. sd.mdrefr |= MDREFR_K1DB2;
  217. sd.mdcas[0] = 0xaaaaaa7f;
  218. } else {
  219. sd.mdrefr &= ~MDREFR_K1DB2;
  220. sd.mdcas[0] = 0xaaaaaa9f;
  221. }
  222. sd.mdcas[1] = 0xaaaaaaaa;
  223. sd.mdcas[2] = 0xaaaaaaaa;
  224. #endif
  225. /*
  226. * The clock could be going away for some time. Set the SDRAMs
  227. * to refresh rapidly (every 64 memory clock cycles). To get
  228. * through the whole array, we need to wait 262144 mclk cycles.
  229. * We wait 20ms to be safe.
  230. */
  231. sdram_set_refresh(2);
  232. if (!irqs_disabled())
  233. msleep(20);
  234. else
  235. mdelay(20);
  236. /*
  237. * Reprogram the DRAM timings with interrupts disabled, and
  238. * ensure that we are doing this within a complete cache line.
  239. * This means that we won't access SDRAM for the duration of
  240. * the programming.
  241. */
  242. local_irq_save(flags);
  243. asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  244. udelay(10);
  245. __asm__ __volatile__("\n\
  246. b 2f \n\
  247. .align 5 \n\
  248. 1: str %3, [%1, #0] @ MDCNFG \n\
  249. str %4, [%1, #28] @ MDREFR \n\
  250. str %5, [%1, #4] @ MDCAS0 \n\
  251. str %6, [%1, #8] @ MDCAS1 \n\
  252. str %7, [%1, #12] @ MDCAS2 \n\
  253. str %8, [%2, #0] @ PPCR \n\
  254. ldr %0, [%1, #0] \n\
  255. b 3f \n\
  256. 2: b 1b \n\
  257. 3: nop \n\
  258. nop"
  259. : "=&r" (unused)
  260. : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
  261. "r" (sd.mdrefr), "r" (sd.mdcas[0]),
  262. "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
  263. local_irq_restore(flags);
  264. /*
  265. * Now, return the SDRAM refresh back to normal.
  266. */
  267. sdram_update_refresh(sa11x0_freq_table[ppcr].frequency, sdram);
  268. return 0;
  269. }
  270. static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
  271. {
  272. cpufreq_generic_init(policy, sa11x0_freq_table, 0);
  273. return 0;
  274. }
  275. /* sa1110_driver needs __refdata because it must remain after init registers
  276. * it with cpufreq_register_driver() */
  277. static struct cpufreq_driver sa1110_driver __refdata = {
  278. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  279. CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
  280. .verify = cpufreq_generic_frequency_table_verify,
  281. .target_index = sa1110_target,
  282. .get = sa11x0_getspeed,
  283. .init = sa1110_cpu_init,
  284. .name = "sa1110",
  285. };
  286. static struct sdram_params *sa1110_find_sdram(const char *name)
  287. {
  288. struct sdram_params *sdram;
  289. for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
  290. sdram++)
  291. if (strcmp(name, sdram->name) == 0)
  292. return sdram;
  293. return NULL;
  294. }
  295. static char sdram_name[16];
  296. static int __init sa1110_clk_init(void)
  297. {
  298. struct sdram_params *sdram;
  299. const char *name = sdram_name;
  300. if (!cpu_is_sa1110())
  301. return -ENODEV;
  302. if (!name[0]) {
  303. if (machine_is_assabet())
  304. name = "TC59SM716-CL3";
  305. if (machine_is_pt_system3())
  306. name = "K4S641632D";
  307. if (machine_is_h3100())
  308. name = "KM416S4030CT";
  309. if (machine_is_jornada720() || machine_is_h3600())
  310. name = "K4S281632B-1H";
  311. if (machine_is_nanoengine())
  312. name = "MT48LC8M16A2TG-75";
  313. }
  314. sdram = sa1110_find_sdram(name);
  315. if (sdram) {
  316. printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
  317. " twr: %d refresh: %d cas_latency: %d\n",
  318. sdram->tck, sdram->trcd, sdram->trp,
  319. sdram->twr, sdram->refresh, sdram->cas_latency);
  320. memcpy(&sdram_params, sdram, sizeof(sdram_params));
  321. return cpufreq_register_driver(&sa1110_driver);
  322. }
  323. return 0;
  324. }
  325. module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
  326. arch_initcall(sa1110_clk_init);