sa1100-cpufreq.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * cpu-sa1100.c: clock scaling for the SA1100
  4. *
  5. * Copyright (C) 2000 2001, The Delft University of Technology
  6. *
  7. * Authors:
  8. * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
  9. * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
  10. * - major rewrite for linux-2.3.99
  11. * - rewritten for the more generic power management scheme in
  12. * linux-2.4.5-rmk1
  13. *
  14. * This software has been developed while working on the LART
  15. * computing board (http://www.lartmaker.nl/), which is
  16. * sponsored by the Mobile Multi-media Communications
  17. * (http://www.mobimedia.org/) and Ubiquitous Communications
  18. * (http://www.ubicom.tudelft.nl/) projects.
  19. *
  20. * The authors can be reached at:
  21. *
  22. * Erik Mouw
  23. * Information and Communication Theory Group
  24. * Faculty of Information Technology and Systems
  25. * Delft University of Technology
  26. * P.O. Box 5031
  27. * 2600 GA Delft
  28. * The Netherlands
  29. *
  30. * Theory of operations
  31. * ====================
  32. *
  33. * Clock scaling can be used to lower the power consumption of the CPU
  34. * core. This will give you a somewhat longer running time.
  35. *
  36. * The SA-1100 has a single register to change the core clock speed:
  37. *
  38. * PPCR 0x90020014 PLL config
  39. *
  40. * However, the DRAM timings are closely related to the core clock
  41. * speed, so we need to change these, too. The used registers are:
  42. *
  43. * MDCNFG 0xA0000000 DRAM config
  44. * MDCAS0 0xA0000004 Access waveform
  45. * MDCAS1 0xA0000008 Access waveform
  46. * MDCAS2 0xA000000C Access waveform
  47. *
  48. * Care must be taken to change the DRAM parameters the correct way,
  49. * because otherwise the DRAM becomes unusable and the kernel will
  50. * crash.
  51. *
  52. * The simple solution to avoid a kernel crash is to put the actual
  53. * clock change in ROM and jump to that code from the kernel. The main
  54. * disadvantage is that the ROM has to be modified, which is not
  55. * possible on all SA-1100 platforms. Another disadvantage is that
  56. * jumping to ROM makes clock switching unnecessary complicated.
  57. *
  58. * The idea behind this driver is that the memory configuration can be
  59. * changed while running from DRAM (even with interrupts turned on!)
  60. * as long as all re-configuration steps yield a valid DRAM
  61. * configuration. The advantages are clear: it will run on all SA-1100
  62. * platforms, and the code is very simple.
  63. *
  64. * If you really want to understand what is going on in
  65. * sa1100_update_dram_timings(), you'll have to read sections 8.2,
  66. * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
  67. * Developers Manual" (available for free from Intel).
  68. */
  69. #include <linux/kernel.h>
  70. #include <linux/types.h>
  71. #include <linux/init.h>
  72. #include <linux/cpufreq.h>
  73. #include <linux/io.h>
  74. #include <asm/cputype.h>
  75. #include <mach/generic.h>
  76. #include <mach/hardware.h>
  77. struct sa1100_dram_regs {
  78. int speed;
  79. u32 mdcnfg;
  80. u32 mdcas0;
  81. u32 mdcas1;
  82. u32 mdcas2;
  83. };
  84. static struct cpufreq_driver sa1100_driver;
  85. static struct sa1100_dram_regs sa1100_dram_settings[] = {
  86. /*speed, mdcnfg, mdcas0, mdcas1, mdcas2, clock freq */
  87. { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 59.0 MHz */
  88. { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 73.7 MHz */
  89. { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 88.5 MHz */
  90. {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
  91. {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
  92. {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
  93. {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
  94. {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
  95. {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
  96. {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
  97. {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
  98. {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
  99. {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
  100. {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
  101. {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
  102. {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
  103. { 0, 0, 0, 0, 0 } /* last entry */
  104. };
  105. static void sa1100_update_dram_timings(int current_speed, int new_speed)
  106. {
  107. struct sa1100_dram_regs *settings = sa1100_dram_settings;
  108. /* find speed */
  109. while (settings->speed != 0) {
  110. if (new_speed == settings->speed)
  111. break;
  112. settings++;
  113. }
  114. if (settings->speed == 0) {
  115. panic("%s: couldn't find dram setting for speed %d\n",
  116. __func__, new_speed);
  117. }
  118. /* No risk, no fun: run with interrupts on! */
  119. if (new_speed > current_speed) {
  120. /* We're going FASTER, so first relax the memory
  121. * timings before changing the core frequency
  122. */
  123. /* Half the memory access clock */
  124. MDCNFG |= MDCNFG_CDB2;
  125. /* The order of these statements IS important, keep 8
  126. * pulses!!
  127. */
  128. MDCAS2 = settings->mdcas2;
  129. MDCAS1 = settings->mdcas1;
  130. MDCAS0 = settings->mdcas0;
  131. MDCNFG = settings->mdcnfg;
  132. } else {
  133. /* We're going SLOWER: first decrease the core
  134. * frequency and then tighten the memory settings.
  135. */
  136. /* Half the memory access clock */
  137. MDCNFG |= MDCNFG_CDB2;
  138. /* The order of these statements IS important, keep 8
  139. * pulses!!
  140. */
  141. MDCAS0 = settings->mdcas0;
  142. MDCAS1 = settings->mdcas1;
  143. MDCAS2 = settings->mdcas2;
  144. MDCNFG = settings->mdcnfg;
  145. }
  146. }
  147. static int sa1100_target(struct cpufreq_policy *policy, unsigned int ppcr)
  148. {
  149. unsigned int cur = sa11x0_getspeed(0);
  150. unsigned int new_freq;
  151. new_freq = sa11x0_freq_table[ppcr].frequency;
  152. if (new_freq > cur)
  153. sa1100_update_dram_timings(cur, new_freq);
  154. PPCR = ppcr;
  155. if (new_freq < cur)
  156. sa1100_update_dram_timings(cur, new_freq);
  157. return 0;
  158. }
  159. static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
  160. {
  161. cpufreq_generic_init(policy, sa11x0_freq_table, 0);
  162. return 0;
  163. }
  164. static struct cpufreq_driver sa1100_driver __refdata = {
  165. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  166. CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
  167. .verify = cpufreq_generic_frequency_table_verify,
  168. .target_index = sa1100_target,
  169. .get = sa11x0_getspeed,
  170. .init = sa1100_cpu_init,
  171. .name = "sa1100",
  172. };
  173. static int __init sa1100_dram_init(void)
  174. {
  175. if (cpu_is_sa1100())
  176. return cpufreq_register_driver(&sa1100_driver);
  177. else
  178. return -ENODEV;
  179. }
  180. arch_initcall(sa1100_dram_init);