s5pv210-cpufreq.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * CPU frequency scaling for S5PC110/S5PV210
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/types.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/err.h>
  13. #include <linux/clk.h>
  14. #include <linux/io.h>
  15. #include <linux/cpufreq.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reboot.h>
  20. #include <linux/regulator/consumer.h>
  21. static void __iomem *clk_base;
  22. static void __iomem *dmc_base[2];
  23. #define S5P_CLKREG(x) (clk_base + (x))
  24. #define S5P_APLL_LOCK S5P_CLKREG(0x00)
  25. #define S5P_APLL_CON S5P_CLKREG(0x100)
  26. #define S5P_CLK_SRC0 S5P_CLKREG(0x200)
  27. #define S5P_CLK_SRC2 S5P_CLKREG(0x208)
  28. #define S5P_CLK_DIV0 S5P_CLKREG(0x300)
  29. #define S5P_CLK_DIV2 S5P_CLKREG(0x308)
  30. #define S5P_CLK_DIV6 S5P_CLKREG(0x318)
  31. #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
  32. #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
  33. #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
  34. #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
  35. #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
  36. /* CLKSRC0 */
  37. #define S5P_CLKSRC0_MUX200_SHIFT (16)
  38. #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
  39. #define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
  40. #define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
  41. /* CLKSRC2 */
  42. #define S5P_CLKSRC2_G3D_SHIFT (0)
  43. #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
  44. #define S5P_CLKSRC2_MFC_SHIFT (4)
  45. #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
  46. /* CLKDIV0 */
  47. #define S5P_CLKDIV0_APLL_SHIFT (0)
  48. #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
  49. #define S5P_CLKDIV0_A2M_SHIFT (4)
  50. #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
  51. #define S5P_CLKDIV0_HCLK200_SHIFT (8)
  52. #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
  53. #define S5P_CLKDIV0_PCLK100_SHIFT (12)
  54. #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
  55. #define S5P_CLKDIV0_HCLK166_SHIFT (16)
  56. #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
  57. #define S5P_CLKDIV0_PCLK83_SHIFT (20)
  58. #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
  59. #define S5P_CLKDIV0_HCLK133_SHIFT (24)
  60. #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
  61. #define S5P_CLKDIV0_PCLK66_SHIFT (28)
  62. #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
  63. /* CLKDIV2 */
  64. #define S5P_CLKDIV2_G3D_SHIFT (0)
  65. #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
  66. #define S5P_CLKDIV2_MFC_SHIFT (4)
  67. #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
  68. /* CLKDIV6 */
  69. #define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
  70. #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
  71. static struct clk *dmc0_clk;
  72. static struct clk *dmc1_clk;
  73. static DEFINE_MUTEX(set_freq_lock);
  74. /* APLL M,P,S values for 1G/800Mhz */
  75. #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  76. #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  77. /* Use 800MHz when entering sleep mode */
  78. #define SLEEP_FREQ (800 * 1000)
  79. /* Tracks if cpu freqency can be updated anymore */
  80. static bool no_cpufreq_access;
  81. /*
  82. * DRAM configurations to calculate refresh counter for changing
  83. * frequency of memory.
  84. */
  85. struct dram_conf {
  86. unsigned long freq; /* HZ */
  87. unsigned long refresh; /* DRAM refresh counter * 1000 */
  88. };
  89. /* DRAM configuration (DMC0 and DMC1) */
  90. static struct dram_conf s5pv210_dram_conf[2];
  91. enum perf_level {
  92. L0, L1, L2, L3, L4,
  93. };
  94. enum s5pv210_mem_type {
  95. LPDDR = 0x1,
  96. LPDDR2 = 0x2,
  97. DDR2 = 0x4,
  98. };
  99. enum s5pv210_dmc_port {
  100. DMC0 = 0,
  101. DMC1,
  102. };
  103. static struct cpufreq_frequency_table s5pv210_freq_table[] = {
  104. {0, L0, 1000*1000},
  105. {0, L1, 800*1000},
  106. {0, L2, 400*1000},
  107. {0, L3, 200*1000},
  108. {0, L4, 100*1000},
  109. {0, 0, CPUFREQ_TABLE_END},
  110. };
  111. static struct regulator *arm_regulator;
  112. static struct regulator *int_regulator;
  113. struct s5pv210_dvs_conf {
  114. int arm_volt; /* uV */
  115. int int_volt; /* uV */
  116. };
  117. static const int arm_volt_max = 1350000;
  118. static const int int_volt_max = 1250000;
  119. static struct s5pv210_dvs_conf dvs_conf[] = {
  120. [L0] = {
  121. .arm_volt = 1250000,
  122. .int_volt = 1100000,
  123. },
  124. [L1] = {
  125. .arm_volt = 1200000,
  126. .int_volt = 1100000,
  127. },
  128. [L2] = {
  129. .arm_volt = 1050000,
  130. .int_volt = 1100000,
  131. },
  132. [L3] = {
  133. .arm_volt = 950000,
  134. .int_volt = 1100000,
  135. },
  136. [L4] = {
  137. .arm_volt = 950000,
  138. .int_volt = 1000000,
  139. },
  140. };
  141. static u32 clkdiv_val[5][11] = {
  142. /*
  143. * Clock divider value for following
  144. * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
  145. * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
  146. * ONEDRAM, MFC, G3D }
  147. */
  148. /* L0 : [1000/200/100][166/83][133/66][200/200] */
  149. {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
  150. /* L1 : [800/200/100][166/83][133/66][200/200] */
  151. {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
  152. /* L2 : [400/200/100][166/83][133/66][200/200] */
  153. {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
  154. /* L3 : [200/200/100][166/83][133/66][200/200] */
  155. {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
  156. /* L4 : [100/100/100][83/83][66/66][100/100] */
  157. {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
  158. };
  159. /*
  160. * This function set DRAM refresh counter
  161. * accoriding to operating frequency of DRAM
  162. * ch: DMC port number 0 or 1
  163. * freq: Operating frequency of DRAM(KHz)
  164. */
  165. static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
  166. {
  167. unsigned long tmp, tmp1;
  168. void __iomem *reg = NULL;
  169. if (ch == DMC0) {
  170. reg = (dmc_base[0] + 0x30);
  171. } else if (ch == DMC1) {
  172. reg = (dmc_base[1] + 0x30);
  173. } else {
  174. pr_err("Cannot find DMC port\n");
  175. return;
  176. }
  177. /* Find current DRAM frequency */
  178. tmp = s5pv210_dram_conf[ch].freq;
  179. tmp /= freq;
  180. tmp1 = s5pv210_dram_conf[ch].refresh;
  181. tmp1 /= tmp;
  182. writel_relaxed(tmp1, reg);
  183. }
  184. static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
  185. {
  186. unsigned long reg;
  187. unsigned int priv_index;
  188. unsigned int pll_changing = 0;
  189. unsigned int bus_speed_changing = 0;
  190. unsigned int old_freq, new_freq;
  191. int arm_volt, int_volt;
  192. int ret = 0;
  193. mutex_lock(&set_freq_lock);
  194. if (no_cpufreq_access) {
  195. pr_err("Denied access to %s as it is disabled temporarily\n",
  196. __func__);
  197. ret = -EINVAL;
  198. goto exit;
  199. }
  200. old_freq = policy->cur;
  201. new_freq = s5pv210_freq_table[index].frequency;
  202. /* Finding current running level index */
  203. priv_index = cpufreq_table_find_index_h(policy, old_freq);
  204. arm_volt = dvs_conf[index].arm_volt;
  205. int_volt = dvs_conf[index].int_volt;
  206. if (new_freq > old_freq) {
  207. ret = regulator_set_voltage(arm_regulator,
  208. arm_volt, arm_volt_max);
  209. if (ret)
  210. goto exit;
  211. ret = regulator_set_voltage(int_regulator,
  212. int_volt, int_volt_max);
  213. if (ret)
  214. goto exit;
  215. }
  216. /* Check if there need to change PLL */
  217. if ((index == L0) || (priv_index == L0))
  218. pll_changing = 1;
  219. /* Check if there need to change System bus clock */
  220. if ((index == L4) || (priv_index == L4))
  221. bus_speed_changing = 1;
  222. if (bus_speed_changing) {
  223. /*
  224. * Reconfigure DRAM refresh counter value for minimum
  225. * temporary clock while changing divider.
  226. * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
  227. */
  228. if (pll_changing)
  229. s5pv210_set_refresh(DMC1, 83000);
  230. else
  231. s5pv210_set_refresh(DMC1, 100000);
  232. s5pv210_set_refresh(DMC0, 83000);
  233. }
  234. /*
  235. * APLL should be changed in this level
  236. * APLL -> MPLL(for stable transition) -> APLL
  237. * Some clock source's clock API are not prepared.
  238. * Do not use clock API in below code.
  239. */
  240. if (pll_changing) {
  241. /*
  242. * 1. Temporary Change divider for MFC and G3D
  243. * SCLKA2M(200/1=200)->(200/4=50)Mhz
  244. */
  245. reg = readl_relaxed(S5P_CLK_DIV2);
  246. reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
  247. reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
  248. (3 << S5P_CLKDIV2_MFC_SHIFT);
  249. writel_relaxed(reg, S5P_CLK_DIV2);
  250. /* For MFC, G3D dividing */
  251. do {
  252. reg = readl_relaxed(S5P_CLKDIV_STAT0);
  253. } while (reg & ((1 << 16) | (1 << 17)));
  254. /*
  255. * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
  256. * (200/4=50)->(667/4=166)Mhz
  257. */
  258. reg = readl_relaxed(S5P_CLK_SRC2);
  259. reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
  260. reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
  261. (1 << S5P_CLKSRC2_MFC_SHIFT);
  262. writel_relaxed(reg, S5P_CLK_SRC2);
  263. do {
  264. reg = readl_relaxed(S5P_CLKMUX_STAT1);
  265. } while (reg & ((1 << 7) | (1 << 3)));
  266. /*
  267. * 3. DMC1 refresh count for 133Mhz if (index == L4) is
  268. * true refresh counter is already programed in upper
  269. * code. 0x287@83Mhz
  270. */
  271. if (!bus_speed_changing)
  272. s5pv210_set_refresh(DMC1, 133000);
  273. /* 4. SCLKAPLL -> SCLKMPLL */
  274. reg = readl_relaxed(S5P_CLK_SRC0);
  275. reg &= ~(S5P_CLKSRC0_MUX200_MASK);
  276. reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
  277. writel_relaxed(reg, S5P_CLK_SRC0);
  278. do {
  279. reg = readl_relaxed(S5P_CLKMUX_STAT0);
  280. } while (reg & (0x1 << 18));
  281. }
  282. /* Change divider */
  283. reg = readl_relaxed(S5P_CLK_DIV0);
  284. reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
  285. S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
  286. S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
  287. S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
  288. reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
  289. (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
  290. (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
  291. (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
  292. (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
  293. (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
  294. (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
  295. (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
  296. writel_relaxed(reg, S5P_CLK_DIV0);
  297. do {
  298. reg = readl_relaxed(S5P_CLKDIV_STAT0);
  299. } while (reg & 0xff);
  300. /* ARM MCS value changed */
  301. reg = readl_relaxed(S5P_ARM_MCS_CON);
  302. reg &= ~0x3;
  303. if (index >= L3)
  304. reg |= 0x3;
  305. else
  306. reg |= 0x1;
  307. writel_relaxed(reg, S5P_ARM_MCS_CON);
  308. if (pll_changing) {
  309. /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
  310. writel_relaxed(0x2cf, S5P_APLL_LOCK);
  311. /*
  312. * 6. Turn on APLL
  313. * 6-1. Set PMS values
  314. * 6-2. Wait untile the PLL is locked
  315. */
  316. if (index == L0)
  317. writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
  318. else
  319. writel_relaxed(APLL_VAL_800, S5P_APLL_CON);
  320. do {
  321. reg = readl_relaxed(S5P_APLL_CON);
  322. } while (!(reg & (0x1 << 29)));
  323. /*
  324. * 7. Change souce clock from SCLKMPLL(667Mhz)
  325. * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
  326. * (667/4=166)->(200/4=50)Mhz
  327. */
  328. reg = readl_relaxed(S5P_CLK_SRC2);
  329. reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
  330. reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
  331. (0 << S5P_CLKSRC2_MFC_SHIFT);
  332. writel_relaxed(reg, S5P_CLK_SRC2);
  333. do {
  334. reg = readl_relaxed(S5P_CLKMUX_STAT1);
  335. } while (reg & ((1 << 7) | (1 << 3)));
  336. /*
  337. * 8. Change divider for MFC and G3D
  338. * (200/4=50)->(200/1=200)Mhz
  339. */
  340. reg = readl_relaxed(S5P_CLK_DIV2);
  341. reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
  342. reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
  343. (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
  344. writel_relaxed(reg, S5P_CLK_DIV2);
  345. /* For MFC, G3D dividing */
  346. do {
  347. reg = readl_relaxed(S5P_CLKDIV_STAT0);
  348. } while (reg & ((1 << 16) | (1 << 17)));
  349. /* 9. Change MPLL to APLL in MSYS_MUX */
  350. reg = readl_relaxed(S5P_CLK_SRC0);
  351. reg &= ~(S5P_CLKSRC0_MUX200_MASK);
  352. reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
  353. writel_relaxed(reg, S5P_CLK_SRC0);
  354. do {
  355. reg = readl_relaxed(S5P_CLKMUX_STAT0);
  356. } while (reg & (0x1 << 18));
  357. /*
  358. * 10. DMC1 refresh counter
  359. * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
  360. * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
  361. */
  362. if (!bus_speed_changing)
  363. s5pv210_set_refresh(DMC1, 200000);
  364. }
  365. /*
  366. * L4 level need to change memory bus speed, hence onedram clock divier
  367. * and memory refresh parameter should be changed
  368. */
  369. if (bus_speed_changing) {
  370. reg = readl_relaxed(S5P_CLK_DIV6);
  371. reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
  372. reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
  373. writel_relaxed(reg, S5P_CLK_DIV6);
  374. do {
  375. reg = readl_relaxed(S5P_CLKDIV_STAT1);
  376. } while (reg & (1 << 15));
  377. /* Reconfigure DRAM refresh counter value */
  378. if (index != L4) {
  379. /*
  380. * DMC0 : 166Mhz
  381. * DMC1 : 200Mhz
  382. */
  383. s5pv210_set_refresh(DMC0, 166000);
  384. s5pv210_set_refresh(DMC1, 200000);
  385. } else {
  386. /*
  387. * DMC0 : 83Mhz
  388. * DMC1 : 100Mhz
  389. */
  390. s5pv210_set_refresh(DMC0, 83000);
  391. s5pv210_set_refresh(DMC1, 100000);
  392. }
  393. }
  394. if (new_freq < old_freq) {
  395. regulator_set_voltage(int_regulator,
  396. int_volt, int_volt_max);
  397. regulator_set_voltage(arm_regulator,
  398. arm_volt, arm_volt_max);
  399. }
  400. pr_debug("Perf changed[L%d]\n", index);
  401. exit:
  402. mutex_unlock(&set_freq_lock);
  403. return ret;
  404. }
  405. static int check_mem_type(void __iomem *dmc_reg)
  406. {
  407. unsigned long val;
  408. val = readl_relaxed(dmc_reg + 0x4);
  409. val = (val & (0xf << 8));
  410. return val >> 8;
  411. }
  412. static int s5pv210_cpu_init(struct cpufreq_policy *policy)
  413. {
  414. unsigned long mem_type;
  415. int ret;
  416. policy->clk = clk_get(NULL, "armclk");
  417. if (IS_ERR(policy->clk))
  418. return PTR_ERR(policy->clk);
  419. dmc0_clk = clk_get(NULL, "sclk_dmc0");
  420. if (IS_ERR(dmc0_clk)) {
  421. ret = PTR_ERR(dmc0_clk);
  422. goto out_dmc0;
  423. }
  424. dmc1_clk = clk_get(NULL, "hclk_msys");
  425. if (IS_ERR(dmc1_clk)) {
  426. ret = PTR_ERR(dmc1_clk);
  427. goto out_dmc1;
  428. }
  429. if (policy->cpu != 0) {
  430. ret = -EINVAL;
  431. goto out_dmc1;
  432. }
  433. /*
  434. * check_mem_type : This driver only support LPDDR & LPDDR2.
  435. * other memory type is not supported.
  436. */
  437. mem_type = check_mem_type(dmc_base[0]);
  438. if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
  439. pr_err("CPUFreq doesn't support this memory type\n");
  440. ret = -EINVAL;
  441. goto out_dmc1;
  442. }
  443. /* Find current refresh counter and frequency each DMC */
  444. s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);
  445. s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
  446. s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);
  447. s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
  448. policy->suspend_freq = SLEEP_FREQ;
  449. cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
  450. return 0;
  451. out_dmc1:
  452. clk_put(dmc0_clk);
  453. out_dmc0:
  454. clk_put(policy->clk);
  455. return ret;
  456. }
  457. static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
  458. unsigned long event, void *ptr)
  459. {
  460. int ret;
  461. struct cpufreq_policy *policy;
  462. policy = cpufreq_cpu_get(0);
  463. if (!policy) {
  464. pr_debug("cpufreq: get no policy for cpu0\n");
  465. return NOTIFY_BAD;
  466. }
  467. ret = cpufreq_driver_target(policy, SLEEP_FREQ, 0);
  468. cpufreq_cpu_put(policy);
  469. if (ret < 0)
  470. return NOTIFY_BAD;
  471. no_cpufreq_access = true;
  472. return NOTIFY_DONE;
  473. }
  474. static struct cpufreq_driver s5pv210_driver = {
  475. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
  476. .verify = cpufreq_generic_frequency_table_verify,
  477. .target_index = s5pv210_target,
  478. .get = cpufreq_generic_get,
  479. .init = s5pv210_cpu_init,
  480. .name = "s5pv210",
  481. .suspend = cpufreq_generic_suspend,
  482. .resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
  483. };
  484. static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
  485. .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
  486. };
  487. static int s5pv210_cpufreq_probe(struct platform_device *pdev)
  488. {
  489. struct device *dev = &pdev->dev;
  490. struct device_node *np;
  491. int id, result = 0;
  492. /*
  493. * HACK: This is a temporary workaround to get access to clock
  494. * and DMC controller registers directly and remove static mappings
  495. * and dependencies on platform headers. It is necessary to enable
  496. * S5PV210 multi-platform support and will be removed together with
  497. * this whole driver as soon as S5PV210 gets migrated to use
  498. * cpufreq-dt driver.
  499. */
  500. arm_regulator = regulator_get(NULL, "vddarm");
  501. if (IS_ERR(arm_regulator))
  502. return dev_err_probe(dev, PTR_ERR(arm_regulator),
  503. "failed to get regulator vddarm\n");
  504. int_regulator = regulator_get(NULL, "vddint");
  505. if (IS_ERR(int_regulator)) {
  506. result = dev_err_probe(dev, PTR_ERR(int_regulator),
  507. "failed to get regulator vddint\n");
  508. goto err_int_regulator;
  509. }
  510. np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
  511. if (!np) {
  512. dev_err(dev, "failed to find clock controller DT node\n");
  513. result = -ENODEV;
  514. goto err_clock;
  515. }
  516. clk_base = of_iomap(np, 0);
  517. of_node_put(np);
  518. if (!clk_base) {
  519. dev_err(dev, "failed to map clock registers\n");
  520. result = -EFAULT;
  521. goto err_clock;
  522. }
  523. for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") {
  524. id = of_alias_get_id(np, "dmc");
  525. if (id < 0 || id >= ARRAY_SIZE(dmc_base)) {
  526. dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np);
  527. of_node_put(np);
  528. result = id;
  529. goto err_clk_base;
  530. }
  531. dmc_base[id] = of_iomap(np, 0);
  532. if (!dmc_base[id]) {
  533. dev_err(dev, "failed to map dmc%d registers\n", id);
  534. of_node_put(np);
  535. result = -EFAULT;
  536. goto err_dmc;
  537. }
  538. }
  539. for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) {
  540. if (!dmc_base[id]) {
  541. dev_err(dev, "failed to find dmc%d node\n", id);
  542. result = -ENODEV;
  543. goto err_dmc;
  544. }
  545. }
  546. register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
  547. return cpufreq_register_driver(&s5pv210_driver);
  548. err_dmc:
  549. for (id = 0; id < ARRAY_SIZE(dmc_base); ++id)
  550. if (dmc_base[id]) {
  551. iounmap(dmc_base[id]);
  552. dmc_base[id] = NULL;
  553. }
  554. err_clk_base:
  555. iounmap(clk_base);
  556. err_clock:
  557. regulator_put(int_regulator);
  558. err_int_regulator:
  559. regulator_put(arm_regulator);
  560. return result;
  561. }
  562. static struct platform_driver s5pv210_cpufreq_platdrv = {
  563. .driver = {
  564. .name = "s5pv210-cpufreq",
  565. },
  566. .probe = s5pv210_cpufreq_probe,
  567. };
  568. builtin_platform_driver(s5pv210_cpufreq_platdrv);