qcom-cpufreq-hw.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/cpufreq.h>
  7. #include <linux/init.h>
  8. #include <linux/interconnect.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pm_opp.h>
  14. #include <linux/slab.h>
  15. #define LUT_MAX_ENTRIES 40U
  16. #define LUT_SRC GENMASK(31, 30)
  17. #define LUT_L_VAL GENMASK(7, 0)
  18. #define LUT_CORE_COUNT GENMASK(18, 16)
  19. #define LUT_VOLT GENMASK(11, 0)
  20. #define CLK_HW_DIV 2
  21. #define LUT_TURBO_IND 1
  22. struct qcom_cpufreq_soc_data {
  23. u32 reg_enable;
  24. u32 reg_freq_lut;
  25. u32 reg_volt_lut;
  26. u32 reg_perf_state;
  27. u8 lut_row_size;
  28. };
  29. struct qcom_cpufreq_data {
  30. void __iomem *base;
  31. struct resource *res;
  32. const struct qcom_cpufreq_soc_data *soc_data;
  33. };
  34. static unsigned long cpu_hw_rate, xo_rate;
  35. static bool icc_scaling_enabled;
  36. static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  37. unsigned long freq_khz)
  38. {
  39. unsigned long freq_hz = freq_khz * 1000;
  40. struct dev_pm_opp *opp;
  41. struct device *dev;
  42. int ret;
  43. dev = get_cpu_device(policy->cpu);
  44. if (!dev)
  45. return -ENODEV;
  46. opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  47. if (IS_ERR(opp))
  48. return PTR_ERR(opp);
  49. ret = dev_pm_opp_set_bw(dev, opp);
  50. dev_pm_opp_put(opp);
  51. return ret;
  52. }
  53. static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  54. unsigned long freq_khz,
  55. unsigned long volt)
  56. {
  57. unsigned long freq_hz = freq_khz * 1000;
  58. int ret;
  59. /* Skip voltage update if the opp table is not available */
  60. if (!icc_scaling_enabled)
  61. return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  62. ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  63. if (ret) {
  64. dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  65. return ret;
  66. }
  67. return dev_pm_opp_enable(cpu_dev, freq_hz);
  68. }
  69. static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
  70. unsigned int index)
  71. {
  72. struct qcom_cpufreq_data *data = policy->driver_data;
  73. const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
  74. unsigned long freq = policy->freq_table[index].frequency;
  75. writel_relaxed(index, data->base + soc_data->reg_perf_state);
  76. if (icc_scaling_enabled)
  77. qcom_cpufreq_set_bw(policy, freq);
  78. return 0;
  79. }
  80. static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
  81. {
  82. struct qcom_cpufreq_data *data;
  83. const struct qcom_cpufreq_soc_data *soc_data;
  84. struct cpufreq_policy *policy;
  85. unsigned int index;
  86. policy = cpufreq_cpu_get_raw(cpu);
  87. if (!policy)
  88. return 0;
  89. data = policy->driver_data;
  90. soc_data = data->soc_data;
  91. index = readl_relaxed(data->base + soc_data->reg_perf_state);
  92. index = min(index, LUT_MAX_ENTRIES - 1);
  93. return policy->freq_table[index].frequency;
  94. }
  95. static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
  96. unsigned int target_freq)
  97. {
  98. struct qcom_cpufreq_data *data = policy->driver_data;
  99. const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
  100. unsigned int index;
  101. index = policy->cached_resolved_idx;
  102. writel_relaxed(index, data->base + soc_data->reg_perf_state);
  103. return policy->freq_table[index].frequency;
  104. }
  105. static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
  106. struct cpufreq_policy *policy)
  107. {
  108. u32 data, src, lval, i, core_count, prev_freq = 0, freq;
  109. u32 volt;
  110. struct cpufreq_frequency_table *table;
  111. struct dev_pm_opp *opp;
  112. unsigned long rate;
  113. int ret;
  114. struct qcom_cpufreq_data *drv_data = policy->driver_data;
  115. const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
  116. table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
  117. if (!table)
  118. return -ENOMEM;
  119. ret = dev_pm_opp_of_add_table(cpu_dev);
  120. if (!ret) {
  121. /* Disable all opps and cross-validate against LUT later */
  122. icc_scaling_enabled = true;
  123. for (rate = 0; ; rate++) {
  124. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
  125. if (IS_ERR(opp))
  126. break;
  127. dev_pm_opp_put(opp);
  128. dev_pm_opp_disable(cpu_dev, rate);
  129. }
  130. } else if (ret != -ENODEV) {
  131. dev_err(cpu_dev, "Invalid opp table in device tree\n");
  132. return ret;
  133. } else {
  134. policy->fast_switch_possible = true;
  135. icc_scaling_enabled = false;
  136. }
  137. for (i = 0; i < LUT_MAX_ENTRIES; i++) {
  138. data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
  139. i * soc_data->lut_row_size);
  140. src = FIELD_GET(LUT_SRC, data);
  141. lval = FIELD_GET(LUT_L_VAL, data);
  142. core_count = FIELD_GET(LUT_CORE_COUNT, data);
  143. data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
  144. i * soc_data->lut_row_size);
  145. volt = FIELD_GET(LUT_VOLT, data) * 1000;
  146. if (src)
  147. freq = xo_rate * lval / 1000;
  148. else
  149. freq = cpu_hw_rate / 1000;
  150. if (freq != prev_freq && core_count != LUT_TURBO_IND) {
  151. if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
  152. table[i].frequency = freq;
  153. dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
  154. freq, core_count);
  155. } else {
  156. dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
  157. table[i].frequency = CPUFREQ_ENTRY_INVALID;
  158. }
  159. } else if (core_count == LUT_TURBO_IND) {
  160. table[i].frequency = CPUFREQ_ENTRY_INVALID;
  161. }
  162. /*
  163. * Two of the same frequencies with the same core counts means
  164. * end of table
  165. */
  166. if (i > 0 && prev_freq == freq) {
  167. struct cpufreq_frequency_table *prev = &table[i - 1];
  168. /*
  169. * Only treat the last frequency that might be a boost
  170. * as the boost frequency
  171. */
  172. if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
  173. if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
  174. prev->frequency = prev_freq;
  175. prev->flags = CPUFREQ_BOOST_FREQ;
  176. } else {
  177. dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
  178. freq);
  179. }
  180. }
  181. break;
  182. }
  183. prev_freq = freq;
  184. }
  185. table[i].frequency = CPUFREQ_TABLE_END;
  186. policy->freq_table = table;
  187. dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
  188. return 0;
  189. }
  190. static void qcom_get_related_cpus(int index, struct cpumask *m)
  191. {
  192. struct device_node *cpu_np;
  193. struct of_phandle_args args;
  194. int cpu, ret;
  195. for_each_possible_cpu(cpu) {
  196. cpu_np = of_cpu_device_node_get(cpu);
  197. if (!cpu_np)
  198. continue;
  199. ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
  200. "#freq-domain-cells", 0,
  201. &args);
  202. of_node_put(cpu_np);
  203. if (ret < 0)
  204. continue;
  205. if (index == args.args[0])
  206. cpumask_set_cpu(cpu, m);
  207. }
  208. }
  209. static const struct qcom_cpufreq_soc_data qcom_soc_data = {
  210. .reg_enable = 0x0,
  211. .reg_freq_lut = 0x110,
  212. .reg_volt_lut = 0x114,
  213. .reg_perf_state = 0x920,
  214. .lut_row_size = 32,
  215. };
  216. static const struct qcom_cpufreq_soc_data epss_soc_data = {
  217. .reg_enable = 0x0,
  218. .reg_freq_lut = 0x100,
  219. .reg_volt_lut = 0x200,
  220. .reg_perf_state = 0x320,
  221. .lut_row_size = 4,
  222. };
  223. static const struct of_device_id qcom_cpufreq_hw_match[] = {
  224. { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
  225. { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
  226. {}
  227. };
  228. MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
  229. static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
  230. {
  231. struct platform_device *pdev = cpufreq_get_driver_data();
  232. struct device *dev = &pdev->dev;
  233. struct of_phandle_args args;
  234. struct device_node *cpu_np;
  235. struct device *cpu_dev;
  236. struct resource *res;
  237. void __iomem *base;
  238. struct qcom_cpufreq_data *data;
  239. int ret, index;
  240. cpu_dev = get_cpu_device(policy->cpu);
  241. if (!cpu_dev) {
  242. pr_err("%s: failed to get cpu%d device\n", __func__,
  243. policy->cpu);
  244. return -ENODEV;
  245. }
  246. cpu_np = of_cpu_device_node_get(policy->cpu);
  247. if (!cpu_np)
  248. return -EINVAL;
  249. ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
  250. "#freq-domain-cells", 0, &args);
  251. of_node_put(cpu_np);
  252. if (ret)
  253. return ret;
  254. index = args.args[0];
  255. res = platform_get_resource(pdev, IORESOURCE_MEM, index);
  256. if (!res) {
  257. dev_err(dev, "failed to get mem resource %d\n", index);
  258. return -ENODEV;
  259. }
  260. if (!request_mem_region(res->start, resource_size(res), res->name)) {
  261. dev_err(dev, "failed to request resource %pR\n", res);
  262. return -EBUSY;
  263. }
  264. base = ioremap(res->start, resource_size(res));
  265. if (!base) {
  266. dev_err(dev, "failed to map resource %pR\n", res);
  267. ret = -ENOMEM;
  268. goto release_region;
  269. }
  270. data = kzalloc(sizeof(*data), GFP_KERNEL);
  271. if (!data) {
  272. ret = -ENOMEM;
  273. goto unmap_base;
  274. }
  275. data->soc_data = of_device_get_match_data(&pdev->dev);
  276. data->base = base;
  277. data->res = res;
  278. /* HW should be in enabled state to proceed */
  279. if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
  280. dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
  281. ret = -ENODEV;
  282. goto error;
  283. }
  284. qcom_get_related_cpus(index, policy->cpus);
  285. if (!cpumask_weight(policy->cpus)) {
  286. dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
  287. ret = -ENOENT;
  288. goto error;
  289. }
  290. policy->driver_data = data;
  291. ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
  292. if (ret) {
  293. dev_err(dev, "Domain-%d failed to read LUT\n", index);
  294. goto error;
  295. }
  296. ret = dev_pm_opp_get_opp_count(cpu_dev);
  297. if (ret <= 0) {
  298. dev_err(cpu_dev, "Failed to add OPPs\n");
  299. ret = -ENODEV;
  300. goto error;
  301. }
  302. dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
  303. return 0;
  304. error:
  305. kfree(data);
  306. unmap_base:
  307. iounmap(base);
  308. release_region:
  309. release_mem_region(res->start, resource_size(res));
  310. return ret;
  311. }
  312. static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
  313. {
  314. struct device *cpu_dev = get_cpu_device(policy->cpu);
  315. struct qcom_cpufreq_data *data = policy->driver_data;
  316. struct resource *res = data->res;
  317. void __iomem *base = data->base;
  318. dev_pm_opp_remove_all_dynamic(cpu_dev);
  319. dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
  320. kfree(policy->freq_table);
  321. kfree(data);
  322. iounmap(base);
  323. release_mem_region(res->start, resource_size(res));
  324. return 0;
  325. }
  326. static struct freq_attr *qcom_cpufreq_hw_attr[] = {
  327. &cpufreq_freq_attr_scaling_available_freqs,
  328. &cpufreq_freq_attr_scaling_boost_freqs,
  329. NULL
  330. };
  331. static struct cpufreq_driver cpufreq_qcom_hw_driver = {
  332. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  333. CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
  334. CPUFREQ_IS_COOLING_DEV,
  335. .verify = cpufreq_generic_frequency_table_verify,
  336. .target_index = qcom_cpufreq_hw_target_index,
  337. .get = qcom_cpufreq_hw_get,
  338. .init = qcom_cpufreq_hw_cpu_init,
  339. .exit = qcom_cpufreq_hw_cpu_exit,
  340. .fast_switch = qcom_cpufreq_hw_fast_switch,
  341. .name = "qcom-cpufreq-hw",
  342. .attr = qcom_cpufreq_hw_attr,
  343. };
  344. static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
  345. {
  346. struct device *cpu_dev;
  347. struct clk *clk;
  348. int ret;
  349. clk = clk_get(&pdev->dev, "xo");
  350. if (IS_ERR(clk))
  351. return PTR_ERR(clk);
  352. xo_rate = clk_get_rate(clk);
  353. clk_put(clk);
  354. clk = clk_get(&pdev->dev, "alternate");
  355. if (IS_ERR(clk))
  356. return PTR_ERR(clk);
  357. cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
  358. clk_put(clk);
  359. cpufreq_qcom_hw_driver.driver_data = pdev;
  360. /* Check for optional interconnect paths on CPU0 */
  361. cpu_dev = get_cpu_device(0);
  362. if (!cpu_dev)
  363. return -EPROBE_DEFER;
  364. ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
  365. if (ret)
  366. return ret;
  367. ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
  368. if (ret)
  369. dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
  370. else
  371. dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
  372. return ret;
  373. }
  374. static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
  375. {
  376. return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
  377. }
  378. static struct platform_driver qcom_cpufreq_hw_driver = {
  379. .probe = qcom_cpufreq_hw_driver_probe,
  380. .remove = qcom_cpufreq_hw_driver_remove,
  381. .driver = {
  382. .name = "qcom-cpufreq-hw",
  383. .of_match_table = qcom_cpufreq_hw_match,
  384. },
  385. };
  386. static int __init qcom_cpufreq_hw_init(void)
  387. {
  388. return platform_driver_register(&qcom_cpufreq_hw_driver);
  389. }
  390. postcore_initcall(qcom_cpufreq_hw_init);
  391. static void __exit qcom_cpufreq_hw_exit(void)
  392. {
  393. platform_driver_unregister(&qcom_cpufreq_hw_driver);
  394. }
  395. module_exit(qcom_cpufreq_hw_exit);
  396. MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
  397. MODULE_LICENSE("GPL v2");