pmac64-cpufreq.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  4. * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
  5. *
  6. * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  7. * that is iMac G5 and latest single CPU desktop.
  8. */
  9. #undef DEBUG
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/module.h>
  12. #include <linux/types.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/sched.h>
  17. #include <linux/cpufreq.h>
  18. #include <linux/init.h>
  19. #include <linux/completion.h>
  20. #include <linux/mutex.h>
  21. #include <linux/of_device.h>
  22. #include <asm/prom.h>
  23. #include <asm/machdep.h>
  24. #include <asm/irq.h>
  25. #include <asm/sections.h>
  26. #include <asm/cputable.h>
  27. #include <asm/time.h>
  28. #include <asm/smu.h>
  29. #include <asm/pmac_pfunc.h>
  30. #define DBG(fmt...) pr_debug(fmt)
  31. /* see 970FX user manual */
  32. #define SCOM_PCR 0x0aa001 /* PCR scom addr */
  33. #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
  34. #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
  35. #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
  36. #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
  37. #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
  38. #define PCR_SPEED_SHIFT 17
  39. #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
  40. #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
  41. #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
  42. #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
  43. #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
  44. #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
  45. #define SCOM_PSR 0x408001 /* PSR scom addr */
  46. /* warning: PSR is a 64 bits register */
  47. #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
  48. #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
  49. #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
  50. #define PSR_CUR_SPEED_SHIFT (56)
  51. /*
  52. * The G5 only supports two frequencies (Quarter speed is not supported)
  53. */
  54. #define CPUFREQ_HIGH 0
  55. #define CPUFREQ_LOW 1
  56. static struct cpufreq_frequency_table g5_cpu_freqs[] = {
  57. {0, CPUFREQ_HIGH, 0},
  58. {0, CPUFREQ_LOW, 0},
  59. {0, 0, CPUFREQ_TABLE_END},
  60. };
  61. /* Power mode data is an array of the 32 bits PCR values to use for
  62. * the various frequencies, retrieved from the device-tree
  63. */
  64. static int g5_pmode_cur;
  65. static void (*g5_switch_volt)(int speed_mode);
  66. static int (*g5_switch_freq)(int speed_mode);
  67. static int (*g5_query_freq)(void);
  68. static unsigned long transition_latency;
  69. #ifdef CONFIG_PMAC_SMU
  70. static const u32 *g5_pmode_data;
  71. static int g5_pmode_max;
  72. static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
  73. static int g5_fvt_count; /* number of op. points */
  74. static int g5_fvt_cur; /* current op. point */
  75. /*
  76. * SMU based voltage switching for Neo2 platforms
  77. */
  78. static void g5_smu_switch_volt(int speed_mode)
  79. {
  80. struct smu_simple_cmd cmd;
  81. DECLARE_COMPLETION_ONSTACK(comp);
  82. smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
  83. &comp, 'V', 'S', 'L', 'E', 'W',
  84. 0xff, g5_fvt_cur+1, speed_mode);
  85. wait_for_completion(&comp);
  86. }
  87. /*
  88. * Platform function based voltage/vdnap switching for Neo2
  89. */
  90. static struct pmf_function *pfunc_set_vdnap0;
  91. static struct pmf_function *pfunc_vdnap0_complete;
  92. static void g5_vdnap_switch_volt(int speed_mode)
  93. {
  94. struct pmf_args args;
  95. u32 slew, done = 0;
  96. unsigned long timeout;
  97. slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
  98. args.count = 1;
  99. args.u[0].p = &slew;
  100. pmf_call_one(pfunc_set_vdnap0, &args);
  101. /* It's an irq GPIO so we should be able to just block here,
  102. * I'll do that later after I've properly tested the IRQ code for
  103. * platform functions
  104. */
  105. timeout = jiffies + HZ/10;
  106. while(!time_after(jiffies, timeout)) {
  107. args.count = 1;
  108. args.u[0].p = &done;
  109. pmf_call_one(pfunc_vdnap0_complete, &args);
  110. if (done)
  111. break;
  112. usleep_range(1000, 1000);
  113. }
  114. if (done == 0)
  115. pr_warn("Timeout in clock slewing !\n");
  116. }
  117. /*
  118. * SCOM based frequency switching for 970FX rev3
  119. */
  120. static int g5_scom_switch_freq(int speed_mode)
  121. {
  122. unsigned long flags;
  123. int to;
  124. /* If frequency is going up, first ramp up the voltage */
  125. if (speed_mode < g5_pmode_cur)
  126. g5_switch_volt(speed_mode);
  127. local_irq_save(flags);
  128. /* Clear PCR high */
  129. scom970_write(SCOM_PCR, 0);
  130. /* Clear PCR low */
  131. scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
  132. /* Set PCR low */
  133. scom970_write(SCOM_PCR, PCR_HILO_SELECT |
  134. g5_pmode_data[speed_mode]);
  135. /* Wait for completion */
  136. for (to = 0; to < 10; to++) {
  137. unsigned long psr = scom970_read(SCOM_PSR);
  138. if ((psr & PSR_CMD_RECEIVED) == 0 &&
  139. (((psr >> PSR_CUR_SPEED_SHIFT) ^
  140. (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
  141. == 0)
  142. break;
  143. if (psr & PSR_CMD_COMPLETED)
  144. break;
  145. udelay(100);
  146. }
  147. local_irq_restore(flags);
  148. /* If frequency is going down, last ramp the voltage */
  149. if (speed_mode > g5_pmode_cur)
  150. g5_switch_volt(speed_mode);
  151. g5_pmode_cur = speed_mode;
  152. ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
  153. return 0;
  154. }
  155. static int g5_scom_query_freq(void)
  156. {
  157. unsigned long psr = scom970_read(SCOM_PSR);
  158. int i;
  159. for (i = 0; i <= g5_pmode_max; i++)
  160. if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
  161. (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
  162. break;
  163. return i;
  164. }
  165. /*
  166. * Fake voltage switching for platforms with missing support
  167. */
  168. static void g5_dummy_switch_volt(int speed_mode)
  169. {
  170. }
  171. #endif /* CONFIG_PMAC_SMU */
  172. /*
  173. * Platform function based voltage switching for PowerMac7,2 & 7,3
  174. */
  175. static struct pmf_function *pfunc_cpu0_volt_high;
  176. static struct pmf_function *pfunc_cpu0_volt_low;
  177. static struct pmf_function *pfunc_cpu1_volt_high;
  178. static struct pmf_function *pfunc_cpu1_volt_low;
  179. static void g5_pfunc_switch_volt(int speed_mode)
  180. {
  181. if (speed_mode == CPUFREQ_HIGH) {
  182. if (pfunc_cpu0_volt_high)
  183. pmf_call_one(pfunc_cpu0_volt_high, NULL);
  184. if (pfunc_cpu1_volt_high)
  185. pmf_call_one(pfunc_cpu1_volt_high, NULL);
  186. } else {
  187. if (pfunc_cpu0_volt_low)
  188. pmf_call_one(pfunc_cpu0_volt_low, NULL);
  189. if (pfunc_cpu1_volt_low)
  190. pmf_call_one(pfunc_cpu1_volt_low, NULL);
  191. }
  192. usleep_range(10000, 10000); /* should be faster , to fix */
  193. }
  194. /*
  195. * Platform function based frequency switching for PowerMac7,2 & 7,3
  196. */
  197. static struct pmf_function *pfunc_cpu_setfreq_high;
  198. static struct pmf_function *pfunc_cpu_setfreq_low;
  199. static struct pmf_function *pfunc_cpu_getfreq;
  200. static struct pmf_function *pfunc_slewing_done;
  201. static int g5_pfunc_switch_freq(int speed_mode)
  202. {
  203. struct pmf_args args;
  204. u32 done = 0;
  205. unsigned long timeout;
  206. int rc;
  207. DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
  208. /* If frequency is going up, first ramp up the voltage */
  209. if (speed_mode < g5_pmode_cur)
  210. g5_switch_volt(speed_mode);
  211. /* Do it */
  212. if (speed_mode == CPUFREQ_HIGH)
  213. rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
  214. else
  215. rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
  216. if (rc)
  217. pr_warn("pfunc switch error %d\n", rc);
  218. /* It's an irq GPIO so we should be able to just block here,
  219. * I'll do that later after I've properly tested the IRQ code for
  220. * platform functions
  221. */
  222. timeout = jiffies + HZ/10;
  223. while(!time_after(jiffies, timeout)) {
  224. args.count = 1;
  225. args.u[0].p = &done;
  226. pmf_call_one(pfunc_slewing_done, &args);
  227. if (done)
  228. break;
  229. usleep_range(500, 500);
  230. }
  231. if (done == 0)
  232. pr_warn("Timeout in clock slewing !\n");
  233. /* If frequency is going down, last ramp the voltage */
  234. if (speed_mode > g5_pmode_cur)
  235. g5_switch_volt(speed_mode);
  236. g5_pmode_cur = speed_mode;
  237. ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
  238. return 0;
  239. }
  240. static int g5_pfunc_query_freq(void)
  241. {
  242. struct pmf_args args;
  243. u32 val = 0;
  244. args.count = 1;
  245. args.u[0].p = &val;
  246. pmf_call_one(pfunc_cpu_getfreq, &args);
  247. return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
  248. }
  249. /*
  250. * Common interface to the cpufreq core
  251. */
  252. static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
  253. {
  254. return g5_switch_freq(index);
  255. }
  256. static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
  257. {
  258. return g5_cpu_freqs[g5_pmode_cur].frequency;
  259. }
  260. static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
  261. {
  262. cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
  263. return 0;
  264. }
  265. static struct cpufreq_driver g5_cpufreq_driver = {
  266. .name = "powermac",
  267. .flags = CPUFREQ_CONST_LOOPS,
  268. .init = g5_cpufreq_cpu_init,
  269. .verify = cpufreq_generic_frequency_table_verify,
  270. .target_index = g5_cpufreq_target,
  271. .get = g5_cpufreq_get_speed,
  272. .attr = cpufreq_generic_attr,
  273. };
  274. #ifdef CONFIG_PMAC_SMU
  275. static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
  276. {
  277. unsigned int psize, ssize;
  278. unsigned long max_freq;
  279. char *freq_method, *volt_method;
  280. const u32 *valp;
  281. u32 pvr_hi;
  282. int use_volts_vdnap = 0;
  283. int use_volts_smu = 0;
  284. int rc = -ENODEV;
  285. /* Check supported platforms */
  286. if (of_machine_is_compatible("PowerMac8,1") ||
  287. of_machine_is_compatible("PowerMac8,2") ||
  288. of_machine_is_compatible("PowerMac9,1") ||
  289. of_machine_is_compatible("PowerMac12,1"))
  290. use_volts_smu = 1;
  291. else if (of_machine_is_compatible("PowerMac11,2"))
  292. use_volts_vdnap = 1;
  293. else
  294. return -ENODEV;
  295. /* Check 970FX for now */
  296. valp = of_get_property(cpunode, "cpu-version", NULL);
  297. if (!valp) {
  298. DBG("No cpu-version property !\n");
  299. goto bail_noprops;
  300. }
  301. pvr_hi = (*valp) >> 16;
  302. if (pvr_hi != 0x3c && pvr_hi != 0x44) {
  303. pr_err("Unsupported CPU version\n");
  304. goto bail_noprops;
  305. }
  306. /* Look for the powertune data in the device-tree */
  307. g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
  308. if (!g5_pmode_data) {
  309. DBG("No power-mode-data !\n");
  310. goto bail_noprops;
  311. }
  312. g5_pmode_max = psize / sizeof(u32) - 1;
  313. if (use_volts_smu) {
  314. const struct smu_sdbp_header *shdr;
  315. /* Look for the FVT table */
  316. shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
  317. if (!shdr)
  318. goto bail_noprops;
  319. g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
  320. ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
  321. g5_fvt_count = ssize / sizeof(*g5_fvt_table);
  322. g5_fvt_cur = 0;
  323. /* Sanity checking */
  324. if (g5_fvt_count < 1 || g5_pmode_max < 1)
  325. goto bail_noprops;
  326. g5_switch_volt = g5_smu_switch_volt;
  327. volt_method = "SMU";
  328. } else if (use_volts_vdnap) {
  329. struct device_node *root;
  330. root = of_find_node_by_path("/");
  331. if (root == NULL) {
  332. pr_err("Can't find root of device tree\n");
  333. goto bail_noprops;
  334. }
  335. pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
  336. pfunc_vdnap0_complete =
  337. pmf_find_function(root, "slewing-done");
  338. of_node_put(root);
  339. if (pfunc_set_vdnap0 == NULL ||
  340. pfunc_vdnap0_complete == NULL) {
  341. pr_err("Can't find required platform function\n");
  342. goto bail_noprops;
  343. }
  344. g5_switch_volt = g5_vdnap_switch_volt;
  345. volt_method = "GPIO";
  346. } else {
  347. g5_switch_volt = g5_dummy_switch_volt;
  348. volt_method = "none";
  349. }
  350. /*
  351. * From what I see, clock-frequency is always the maximal frequency.
  352. * The current driver can not slew sysclk yet, so we really only deal
  353. * with powertune steps for now. We also only implement full freq and
  354. * half freq in this version. So far, I haven't yet seen a machine
  355. * supporting anything else.
  356. */
  357. valp = of_get_property(cpunode, "clock-frequency", NULL);
  358. if (!valp)
  359. return -ENODEV;
  360. max_freq = (*valp)/1000;
  361. g5_cpu_freqs[0].frequency = max_freq;
  362. g5_cpu_freqs[1].frequency = max_freq/2;
  363. /* Set callbacks */
  364. transition_latency = 12000;
  365. g5_switch_freq = g5_scom_switch_freq;
  366. g5_query_freq = g5_scom_query_freq;
  367. freq_method = "SCOM";
  368. /* Force apply current frequency to make sure everything is in
  369. * sync (voltage is right for example). Firmware may leave us with
  370. * a strange setting ...
  371. */
  372. g5_switch_volt(CPUFREQ_HIGH);
  373. msleep(10);
  374. g5_pmode_cur = -1;
  375. g5_switch_freq(g5_query_freq());
  376. pr_info("Registering G5 CPU frequency driver\n");
  377. pr_info("Frequency method: %s, Voltage method: %s\n",
  378. freq_method, volt_method);
  379. pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
  380. g5_cpu_freqs[1].frequency/1000,
  381. g5_cpu_freqs[0].frequency/1000,
  382. g5_cpu_freqs[g5_pmode_cur].frequency/1000);
  383. rc = cpufreq_register_driver(&g5_cpufreq_driver);
  384. /* We keep the CPU node on hold... hopefully, Apple G5 don't have
  385. * hotplug CPU with a dynamic device-tree ...
  386. */
  387. return rc;
  388. bail_noprops:
  389. of_node_put(cpunode);
  390. return rc;
  391. }
  392. #endif /* CONFIG_PMAC_SMU */
  393. static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
  394. {
  395. struct device_node *cpuid = NULL, *hwclock = NULL;
  396. const u8 *eeprom = NULL;
  397. const u32 *valp;
  398. u64 max_freq, min_freq, ih, il;
  399. int has_volt = 1, rc = 0;
  400. DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
  401. " RackMac3,1...\n");
  402. /* Lookup the cpuid eeprom node */
  403. cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
  404. if (cpuid != NULL)
  405. eeprom = of_get_property(cpuid, "cpuid", NULL);
  406. if (eeprom == NULL) {
  407. pr_err("Can't find cpuid EEPROM !\n");
  408. rc = -ENODEV;
  409. goto bail;
  410. }
  411. /* Lookup the i2c hwclock */
  412. for_each_node_by_name(hwclock, "i2c-hwclock") {
  413. const char *loc = of_get_property(hwclock,
  414. "hwctrl-location", NULL);
  415. if (loc == NULL)
  416. continue;
  417. if (strcmp(loc, "CPU CLOCK"))
  418. continue;
  419. if (!of_get_property(hwclock, "platform-get-frequency", NULL))
  420. continue;
  421. break;
  422. }
  423. if (hwclock == NULL) {
  424. pr_err("Can't find i2c clock chip !\n");
  425. rc = -ENODEV;
  426. goto bail;
  427. }
  428. DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
  429. /* Now get all the platform functions */
  430. pfunc_cpu_getfreq =
  431. pmf_find_function(hwclock, "get-frequency");
  432. pfunc_cpu_setfreq_high =
  433. pmf_find_function(hwclock, "set-frequency-high");
  434. pfunc_cpu_setfreq_low =
  435. pmf_find_function(hwclock, "set-frequency-low");
  436. pfunc_slewing_done =
  437. pmf_find_function(hwclock, "slewing-done");
  438. pfunc_cpu0_volt_high =
  439. pmf_find_function(hwclock, "set-voltage-high-0");
  440. pfunc_cpu0_volt_low =
  441. pmf_find_function(hwclock, "set-voltage-low-0");
  442. pfunc_cpu1_volt_high =
  443. pmf_find_function(hwclock, "set-voltage-high-1");
  444. pfunc_cpu1_volt_low =
  445. pmf_find_function(hwclock, "set-voltage-low-1");
  446. /* Check we have minimum requirements */
  447. if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
  448. pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
  449. pr_err("Can't find platform functions !\n");
  450. rc = -ENODEV;
  451. goto bail;
  452. }
  453. /* Check that we have complete sets */
  454. if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
  455. pmf_put_function(pfunc_cpu0_volt_high);
  456. pmf_put_function(pfunc_cpu0_volt_low);
  457. pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
  458. has_volt = 0;
  459. }
  460. if (!has_volt ||
  461. pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
  462. pmf_put_function(pfunc_cpu1_volt_high);
  463. pmf_put_function(pfunc_cpu1_volt_low);
  464. pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
  465. }
  466. /* Note: The device tree also contains a "platform-set-values"
  467. * function for which I haven't quite figured out the usage. It
  468. * might have to be called on init and/or wakeup, I'm not too sure
  469. * but things seem to work fine without it so far ...
  470. */
  471. /* Get max frequency from device-tree */
  472. valp = of_get_property(cpunode, "clock-frequency", NULL);
  473. if (!valp) {
  474. pr_err("Can't find CPU frequency !\n");
  475. rc = -ENODEV;
  476. goto bail;
  477. }
  478. max_freq = (*valp)/1000;
  479. /* Now calculate reduced frequency by using the cpuid input freq
  480. * ratio. This requires 64 bits math unless we are willing to lose
  481. * some precision
  482. */
  483. ih = *((u32 *)(eeprom + 0x10));
  484. il = *((u32 *)(eeprom + 0x20));
  485. /* Check for machines with no useful settings */
  486. if (il == ih) {
  487. pr_warn("No low frequency mode available on this model !\n");
  488. rc = -ENODEV;
  489. goto bail;
  490. }
  491. min_freq = 0;
  492. if (ih != 0 && il != 0)
  493. min_freq = (max_freq * il) / ih;
  494. /* Sanity check */
  495. if (min_freq >= max_freq || min_freq < 1000) {
  496. pr_err("Can't calculate low frequency !\n");
  497. rc = -ENXIO;
  498. goto bail;
  499. }
  500. g5_cpu_freqs[0].frequency = max_freq;
  501. g5_cpu_freqs[1].frequency = min_freq;
  502. /* Based on a measurement on Xserve G5, rounded up. */
  503. transition_latency = 10 * NSEC_PER_MSEC;
  504. /* Set callbacks */
  505. g5_switch_volt = g5_pfunc_switch_volt;
  506. g5_switch_freq = g5_pfunc_switch_freq;
  507. g5_query_freq = g5_pfunc_query_freq;
  508. /* Force apply current frequency to make sure everything is in
  509. * sync (voltage is right for example). Firmware may leave us with
  510. * a strange setting ...
  511. */
  512. g5_switch_volt(CPUFREQ_HIGH);
  513. msleep(10);
  514. g5_pmode_cur = -1;
  515. g5_switch_freq(g5_query_freq());
  516. pr_info("Registering G5 CPU frequency driver\n");
  517. pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
  518. has_volt ? "i2c/pfunc" : "none");
  519. pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
  520. g5_cpu_freqs[1].frequency/1000,
  521. g5_cpu_freqs[0].frequency/1000,
  522. g5_cpu_freqs[g5_pmode_cur].frequency/1000);
  523. rc = cpufreq_register_driver(&g5_cpufreq_driver);
  524. bail:
  525. if (rc != 0) {
  526. pmf_put_function(pfunc_cpu_getfreq);
  527. pmf_put_function(pfunc_cpu_setfreq_high);
  528. pmf_put_function(pfunc_cpu_setfreq_low);
  529. pmf_put_function(pfunc_slewing_done);
  530. pmf_put_function(pfunc_cpu0_volt_high);
  531. pmf_put_function(pfunc_cpu0_volt_low);
  532. pmf_put_function(pfunc_cpu1_volt_high);
  533. pmf_put_function(pfunc_cpu1_volt_low);
  534. }
  535. of_node_put(hwclock);
  536. of_node_put(cpuid);
  537. of_node_put(cpunode);
  538. return rc;
  539. }
  540. static int __init g5_cpufreq_init(void)
  541. {
  542. struct device_node *cpunode;
  543. int rc = 0;
  544. /* Get first CPU node */
  545. cpunode = of_cpu_device_node_get(0);
  546. if (cpunode == NULL) {
  547. pr_err("Can't find any CPU node\n");
  548. return -ENODEV;
  549. }
  550. if (of_machine_is_compatible("PowerMac7,2") ||
  551. of_machine_is_compatible("PowerMac7,3") ||
  552. of_machine_is_compatible("RackMac3,1"))
  553. rc = g5_pm72_cpufreq_init(cpunode);
  554. #ifdef CONFIG_PMAC_SMU
  555. else
  556. rc = g5_neo2_cpufreq_init(cpunode);
  557. #endif /* CONFIG_PMAC_SMU */
  558. return rc;
  559. }
  560. module_init(g5_cpufreq_init);
  561. MODULE_LICENSE("GPL");