p4-clockmod.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Pentium 4/Xeon CPU on demand clock modulation/speed scaling
  4. * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
  5. * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
  6. * (C) 2002 Arjan van de Ven <arjanv@redhat.com>
  7. * (C) 2002 Tora T. Engstad
  8. * All Rights Reserved
  9. *
  10. * The author(s) of this software shall not be held liable for damages
  11. * of any nature resulting due to the use of this software. This
  12. * software is provided AS-IS with no warranties.
  13. *
  14. * Date Errata Description
  15. * 20020525 N44, O17 12.5% or 25% DC causes lockup
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/smp.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/cpumask.h>
  24. #include <linux/timex.h>
  25. #include <asm/processor.h>
  26. #include <asm/msr.h>
  27. #include <asm/timer.h>
  28. #include <asm/cpu_device_id.h>
  29. #include "speedstep-lib.h"
  30. /*
  31. * Duty Cycle (3bits), note DC_DISABLE is not specified in
  32. * intel docs i just use it to mean disable
  33. */
  34. enum {
  35. DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
  36. DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
  37. };
  38. #define DC_ENTRIES 8
  39. static int has_N44_O17_errata[NR_CPUS];
  40. static unsigned int stock_freq;
  41. static struct cpufreq_driver p4clockmod_driver;
  42. static unsigned int cpufreq_p4_get(unsigned int cpu);
  43. static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
  44. {
  45. u32 l, h;
  46. if ((newstate > DC_DISABLE) || (newstate == DC_RESV))
  47. return -EINVAL;
  48. rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
  49. if (l & 0x01)
  50. pr_debug("CPU#%d currently thermal throttled\n", cpu);
  51. if (has_N44_O17_errata[cpu] &&
  52. (newstate == DC_25PT || newstate == DC_DFLT))
  53. newstate = DC_38PT;
  54. rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
  55. if (newstate == DC_DISABLE) {
  56. pr_debug("CPU#%d disabling modulation\n", cpu);
  57. wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
  58. } else {
  59. pr_debug("CPU#%d setting duty cycle to %d%%\n",
  60. cpu, ((125 * newstate) / 10));
  61. /* bits 63 - 5 : reserved
  62. * bit 4 : enable/disable
  63. * bits 3-1 : duty cycle
  64. * bit 0 : reserved
  65. */
  66. l = (l & ~14);
  67. l = l | (1<<4) | ((newstate & 0x7)<<1);
  68. wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
  69. }
  70. return 0;
  71. }
  72. static struct cpufreq_frequency_table p4clockmod_table[] = {
  73. {0, DC_RESV, CPUFREQ_ENTRY_INVALID},
  74. {0, DC_DFLT, 0},
  75. {0, DC_25PT, 0},
  76. {0, DC_38PT, 0},
  77. {0, DC_50PT, 0},
  78. {0, DC_64PT, 0},
  79. {0, DC_75PT, 0},
  80. {0, DC_88PT, 0},
  81. {0, DC_DISABLE, 0},
  82. {0, DC_RESV, CPUFREQ_TABLE_END},
  83. };
  84. static int cpufreq_p4_target(struct cpufreq_policy *policy, unsigned int index)
  85. {
  86. int i;
  87. /* run on each logical CPU,
  88. * see section 13.15.3 of IA32 Intel Architecture Software
  89. * Developer's Manual, Volume 3
  90. */
  91. for_each_cpu(i, policy->cpus)
  92. cpufreq_p4_setdc(i, p4clockmod_table[index].driver_data);
  93. return 0;
  94. }
  95. static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
  96. {
  97. if (c->x86 == 0x06) {
  98. if (cpu_has(c, X86_FEATURE_EST))
  99. pr_warn_once("Warning: EST-capable CPU detected. The acpi-cpufreq module offers voltage scaling in addition to frequency scaling. You should use that instead of p4-clockmod, if possible.\n");
  100. switch (c->x86_model) {
  101. case 0x0E: /* Core */
  102. case 0x0F: /* Core Duo */
  103. case 0x16: /* Celeron Core */
  104. case 0x1C: /* Atom */
  105. p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
  106. return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
  107. case 0x0D: /* Pentium M (Dothan) */
  108. p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
  109. fallthrough;
  110. case 0x09: /* Pentium M (Banias) */
  111. return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
  112. }
  113. }
  114. if (c->x86 != 0xF)
  115. return 0;
  116. /* on P-4s, the TSC runs with constant frequency independent whether
  117. * throttling is active or not. */
  118. p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
  119. if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
  120. pr_warn("Warning: Pentium 4-M detected. The speedstep-ich or acpi cpufreq modules offer voltage scaling in addition of frequency scaling. You should use either one instead of p4-clockmod, if possible.\n");
  121. return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
  122. }
  123. return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
  124. }
  125. static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
  126. {
  127. struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
  128. int cpuid = 0;
  129. unsigned int i;
  130. #ifdef CONFIG_SMP
  131. cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu));
  132. #endif
  133. /* Errata workaround */
  134. cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
  135. switch (cpuid) {
  136. case 0x0f07:
  137. case 0x0f0a:
  138. case 0x0f11:
  139. case 0x0f12:
  140. has_N44_O17_errata[policy->cpu] = 1;
  141. pr_debug("has errata -- disabling low frequencies\n");
  142. }
  143. if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
  144. c->x86_model < 2) {
  145. /* switch to maximum frequency and measure result */
  146. cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
  147. recalibrate_cpu_khz();
  148. }
  149. /* get max frequency */
  150. stock_freq = cpufreq_p4_get_frequency(c);
  151. if (!stock_freq)
  152. return -EINVAL;
  153. /* table init */
  154. for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
  155. if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
  156. p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
  157. else
  158. p4clockmod_table[i].frequency = (stock_freq * i)/8;
  159. }
  160. /* cpuinfo and default policy values */
  161. /* the transition latency is set to be 1 higher than the maximum
  162. * transition latency of the ondemand governor */
  163. policy->cpuinfo.transition_latency = 10000001;
  164. policy->freq_table = &p4clockmod_table[0];
  165. return 0;
  166. }
  167. static unsigned int cpufreq_p4_get(unsigned int cpu)
  168. {
  169. u32 l, h;
  170. rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
  171. if (l & 0x10) {
  172. l = l >> 1;
  173. l &= 0x7;
  174. } else
  175. l = DC_DISABLE;
  176. if (l != DC_DISABLE)
  177. return stock_freq * l / 8;
  178. return stock_freq;
  179. }
  180. static struct cpufreq_driver p4clockmod_driver = {
  181. .verify = cpufreq_generic_frequency_table_verify,
  182. .target_index = cpufreq_p4_target,
  183. .init = cpufreq_p4_cpu_init,
  184. .get = cpufreq_p4_get,
  185. .name = "p4-clockmod",
  186. .attr = cpufreq_generic_attr,
  187. };
  188. static const struct x86_cpu_id cpufreq_p4_id[] = {
  189. X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_ACC, NULL),
  190. {}
  191. };
  192. /*
  193. * Intentionally no MODULE_DEVICE_TABLE here: this driver should not
  194. * be auto loaded. Please don't add one.
  195. */
  196. static int __init cpufreq_p4_init(void)
  197. {
  198. int ret;
  199. /*
  200. * THERM_CONTROL is architectural for IA32 now, so
  201. * we can rely on the capability checks
  202. */
  203. if (!x86_match_cpu(cpufreq_p4_id) || !boot_cpu_has(X86_FEATURE_ACPI))
  204. return -ENODEV;
  205. ret = cpufreq_register_driver(&p4clockmod_driver);
  206. if (!ret)
  207. pr_info("P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
  208. return ret;
  209. }
  210. static void __exit cpufreq_p4_exit(void)
  211. {
  212. cpufreq_unregister_driver(&p4clockmod_driver);
  213. }
  214. MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
  215. MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
  216. MODULE_LICENSE("GPL");
  217. late_initcall(cpufreq_p4_init);
  218. module_exit(cpufreq_p4_exit);