brcmstb-avs-cpufreq.c 20 KB

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  1. /*
  2. * CPU frequency scaling for Broadcom SoCs with AVS firmware that
  3. * supports DVS or DVFS
  4. *
  5. * Copyright (c) 2016 Broadcom
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. /*
  17. * "AVS" is the name of a firmware developed at Broadcom. It derives
  18. * its name from the technique called "Adaptive Voltage Scaling".
  19. * Adaptive voltage scaling was the original purpose of this firmware.
  20. * The AVS firmware still supports "AVS mode", where all it does is
  21. * adaptive voltage scaling. However, on some newer Broadcom SoCs, the
  22. * AVS Firmware, despite its unchanged name, also supports DFS mode and
  23. * DVFS mode.
  24. *
  25. * In the context of this document and the related driver, "AVS" by
  26. * itself always means the Broadcom firmware and never refers to the
  27. * technique called "Adaptive Voltage Scaling".
  28. *
  29. * The Broadcom STB AVS CPUfreq driver provides voltage and frequency
  30. * scaling on Broadcom SoCs using AVS firmware with support for DFS and
  31. * DVFS. The AVS firmware is running on its own co-processor. The
  32. * driver supports both uniprocessor (UP) and symmetric multiprocessor
  33. * (SMP) systems which share clock and voltage across all CPUs.
  34. *
  35. * Actual voltage and frequency scaling is done solely by the AVS
  36. * firmware. This driver does not change frequency or voltage itself.
  37. * It provides a standard CPUfreq interface to the rest of the kernel
  38. * and to userland. It interfaces with the AVS firmware to effect the
  39. * requested changes and to report back the current system status in a
  40. * way that is expected by existing tools.
  41. */
  42. #include <linux/cpufreq.h>
  43. #include <linux/delay.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/io.h>
  46. #include <linux/module.h>
  47. #include <linux/of_address.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/semaphore.h>
  50. /* Max number of arguments AVS calls take */
  51. #define AVS_MAX_CMD_ARGS 4
  52. /*
  53. * This macro is used to generate AVS parameter register offsets. For
  54. * x >= AVS_MAX_CMD_ARGS, it returns 0 to protect against accidental memory
  55. * access outside of the parameter range. (Offset 0 is the first parameter.)
  56. */
  57. #define AVS_PARAM_MULT(x) ((x) < AVS_MAX_CMD_ARGS ? (x) : 0)
  58. /* AVS Mailbox Register offsets */
  59. #define AVS_MBOX_COMMAND 0x00
  60. #define AVS_MBOX_STATUS 0x04
  61. #define AVS_MBOX_VOLTAGE0 0x08
  62. #define AVS_MBOX_TEMP0 0x0c
  63. #define AVS_MBOX_PV0 0x10
  64. #define AVS_MBOX_MV0 0x14
  65. #define AVS_MBOX_PARAM(x) (0x18 + AVS_PARAM_MULT(x) * sizeof(u32))
  66. #define AVS_MBOX_REVISION 0x28
  67. #define AVS_MBOX_PSTATE 0x2c
  68. #define AVS_MBOX_HEARTBEAT 0x30
  69. #define AVS_MBOX_MAGIC 0x34
  70. #define AVS_MBOX_SIGMA_HVT 0x38
  71. #define AVS_MBOX_SIGMA_SVT 0x3c
  72. #define AVS_MBOX_VOLTAGE1 0x40
  73. #define AVS_MBOX_TEMP1 0x44
  74. #define AVS_MBOX_PV1 0x48
  75. #define AVS_MBOX_MV1 0x4c
  76. #define AVS_MBOX_FREQUENCY 0x50
  77. /* AVS Commands */
  78. #define AVS_CMD_AVAILABLE 0x00
  79. #define AVS_CMD_DISABLE 0x10
  80. #define AVS_CMD_ENABLE 0x11
  81. #define AVS_CMD_S2_ENTER 0x12
  82. #define AVS_CMD_S2_EXIT 0x13
  83. #define AVS_CMD_BBM_ENTER 0x14
  84. #define AVS_CMD_BBM_EXIT 0x15
  85. #define AVS_CMD_S3_ENTER 0x16
  86. #define AVS_CMD_S3_EXIT 0x17
  87. #define AVS_CMD_BALANCE 0x18
  88. /* PMAP and P-STATE commands */
  89. #define AVS_CMD_GET_PMAP 0x30
  90. #define AVS_CMD_SET_PMAP 0x31
  91. #define AVS_CMD_GET_PSTATE 0x40
  92. #define AVS_CMD_SET_PSTATE 0x41
  93. /* Different modes AVS supports (for GET_PMAP/SET_PMAP) */
  94. #define AVS_MODE_AVS 0x0
  95. #define AVS_MODE_DFS 0x1
  96. #define AVS_MODE_DVS 0x2
  97. #define AVS_MODE_DVFS 0x3
  98. /*
  99. * PMAP parameter p1
  100. * unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0
  101. */
  102. #define NDIV_INT_SHIFT 0
  103. #define NDIV_INT_MASK 0x3ff
  104. #define PDIV_SHIFT 10
  105. #define PDIV_MASK 0xf
  106. #define MDIV_P0_SHIFT 16
  107. #define MDIV_P0_MASK 0xff
  108. /*
  109. * PMAP parameter p2
  110. * mdiv_p4:31-24, mdiv_p3:23-16, mdiv_p2:15:8, mdiv_p1:7:0
  111. */
  112. #define MDIV_P1_SHIFT 0
  113. #define MDIV_P1_MASK 0xff
  114. #define MDIV_P2_SHIFT 8
  115. #define MDIV_P2_MASK 0xff
  116. #define MDIV_P3_SHIFT 16
  117. #define MDIV_P3_MASK 0xff
  118. #define MDIV_P4_SHIFT 24
  119. #define MDIV_P4_MASK 0xff
  120. /* Different P-STATES AVS supports (for GET_PSTATE/SET_PSTATE) */
  121. #define AVS_PSTATE_P0 0x0
  122. #define AVS_PSTATE_P1 0x1
  123. #define AVS_PSTATE_P2 0x2
  124. #define AVS_PSTATE_P3 0x3
  125. #define AVS_PSTATE_P4 0x4
  126. #define AVS_PSTATE_MAX AVS_PSTATE_P4
  127. /* CPU L2 Interrupt Controller Registers */
  128. #define AVS_CPU_L2_SET0 0x04
  129. #define AVS_CPU_L2_INT_MASK BIT(31)
  130. /* AVS Command Status Values */
  131. #define AVS_STATUS_CLEAR 0x00
  132. /* Command/notification accepted */
  133. #define AVS_STATUS_SUCCESS 0xf0
  134. /* Command/notification rejected */
  135. #define AVS_STATUS_FAILURE 0xff
  136. /* Invalid command/notification (unknown) */
  137. #define AVS_STATUS_INVALID 0xf1
  138. /* Non-AVS modes are not supported */
  139. #define AVS_STATUS_NO_SUPP 0xf2
  140. /* Cannot set P-State until P-Map supplied */
  141. #define AVS_STATUS_NO_MAP 0xf3
  142. /* Cannot change P-Map after initial P-Map set */
  143. #define AVS_STATUS_MAP_SET 0xf4
  144. /* Max AVS status; higher numbers are used for debugging */
  145. #define AVS_STATUS_MAX 0xff
  146. /* Other AVS related constants */
  147. #define AVS_LOOP_LIMIT 10000
  148. #define AVS_TIMEOUT 300 /* in ms; expected completion is < 10ms */
  149. #define AVS_FIRMWARE_MAGIC 0xa11600d1
  150. #define BRCM_AVS_CPUFREQ_PREFIX "brcmstb-avs"
  151. #define BRCM_AVS_CPUFREQ_NAME BRCM_AVS_CPUFREQ_PREFIX "-cpufreq"
  152. #define BRCM_AVS_CPU_DATA "brcm,avs-cpu-data-mem"
  153. #define BRCM_AVS_CPU_INTR "brcm,avs-cpu-l2-intr"
  154. #define BRCM_AVS_HOST_INTR "sw_intr"
  155. struct pmap {
  156. unsigned int mode;
  157. unsigned int p1;
  158. unsigned int p2;
  159. unsigned int state;
  160. };
  161. struct private_data {
  162. void __iomem *base;
  163. void __iomem *avs_intr_base;
  164. struct device *dev;
  165. struct completion done;
  166. struct semaphore sem;
  167. struct pmap pmap;
  168. int host_irq;
  169. };
  170. static void __iomem *__map_region(const char *name)
  171. {
  172. struct device_node *np;
  173. void __iomem *ptr;
  174. np = of_find_compatible_node(NULL, NULL, name);
  175. if (!np)
  176. return NULL;
  177. ptr = of_iomap(np, 0);
  178. of_node_put(np);
  179. return ptr;
  180. }
  181. static unsigned long wait_for_avs_command(struct private_data *priv,
  182. unsigned long timeout)
  183. {
  184. unsigned long time_left = 0;
  185. u32 val;
  186. /* Event driven, wait for the command interrupt */
  187. if (priv->host_irq >= 0)
  188. return wait_for_completion_timeout(&priv->done,
  189. msecs_to_jiffies(timeout));
  190. /* Polling for command completion */
  191. do {
  192. time_left = timeout;
  193. val = readl(priv->base + AVS_MBOX_STATUS);
  194. if (val)
  195. break;
  196. usleep_range(1000, 2000);
  197. } while (--timeout);
  198. return time_left;
  199. }
  200. static int __issue_avs_command(struct private_data *priv, unsigned int cmd,
  201. unsigned int num_in, unsigned int num_out,
  202. u32 args[])
  203. {
  204. void __iomem *base = priv->base;
  205. unsigned long time_left;
  206. unsigned int i;
  207. int ret;
  208. u32 val;
  209. ret = down_interruptible(&priv->sem);
  210. if (ret)
  211. return ret;
  212. /*
  213. * Make sure no other command is currently running: cmd is 0 if AVS
  214. * co-processor is idle. Due to the guard above, we should almost never
  215. * have to wait here.
  216. */
  217. for (i = 0, val = 1; val != 0 && i < AVS_LOOP_LIMIT; i++)
  218. val = readl(base + AVS_MBOX_COMMAND);
  219. /* Give the caller a chance to retry if AVS is busy. */
  220. if (i == AVS_LOOP_LIMIT) {
  221. ret = -EAGAIN;
  222. goto out;
  223. }
  224. /* Clear status before we begin. */
  225. writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
  226. /* Provide input parameters */
  227. for (i = 0; i < num_in; i++)
  228. writel(args[i], base + AVS_MBOX_PARAM(i));
  229. /* Protect from spurious interrupts. */
  230. reinit_completion(&priv->done);
  231. /* Now issue the command & tell firmware to wake up to process it. */
  232. writel(cmd, base + AVS_MBOX_COMMAND);
  233. writel(AVS_CPU_L2_INT_MASK, priv->avs_intr_base + AVS_CPU_L2_SET0);
  234. /* Wait for AVS co-processor to finish processing the command. */
  235. time_left = wait_for_avs_command(priv, AVS_TIMEOUT);
  236. /*
  237. * If the AVS status is not in the expected range, it means AVS didn't
  238. * complete our command in time, and we return an error. Also, if there
  239. * is no "time left", we timed out waiting for the interrupt.
  240. */
  241. val = readl(base + AVS_MBOX_STATUS);
  242. if (time_left == 0 || val == 0 || val > AVS_STATUS_MAX) {
  243. dev_err(priv->dev, "AVS command %#x didn't complete in time\n",
  244. cmd);
  245. dev_err(priv->dev, " Time left: %u ms, AVS status: %#x\n",
  246. jiffies_to_msecs(time_left), val);
  247. ret = -ETIMEDOUT;
  248. goto out;
  249. }
  250. /* Process returned values */
  251. for (i = 0; i < num_out; i++)
  252. args[i] = readl(base + AVS_MBOX_PARAM(i));
  253. /* Clear status to tell AVS co-processor we are done. */
  254. writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
  255. /* Convert firmware errors to errno's as much as possible. */
  256. switch (val) {
  257. case AVS_STATUS_INVALID:
  258. ret = -EINVAL;
  259. break;
  260. case AVS_STATUS_NO_SUPP:
  261. ret = -ENOTSUPP;
  262. break;
  263. case AVS_STATUS_NO_MAP:
  264. ret = -ENOENT;
  265. break;
  266. case AVS_STATUS_MAP_SET:
  267. ret = -EEXIST;
  268. break;
  269. case AVS_STATUS_FAILURE:
  270. ret = -EIO;
  271. break;
  272. }
  273. out:
  274. up(&priv->sem);
  275. return ret;
  276. }
  277. static irqreturn_t irq_handler(int irq, void *data)
  278. {
  279. struct private_data *priv = data;
  280. /* AVS command completed execution. Wake up __issue_avs_command(). */
  281. complete(&priv->done);
  282. return IRQ_HANDLED;
  283. }
  284. static char *brcm_avs_mode_to_string(unsigned int mode)
  285. {
  286. switch (mode) {
  287. case AVS_MODE_AVS:
  288. return "AVS";
  289. case AVS_MODE_DFS:
  290. return "DFS";
  291. case AVS_MODE_DVS:
  292. return "DVS";
  293. case AVS_MODE_DVFS:
  294. return "DVFS";
  295. }
  296. return NULL;
  297. }
  298. static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv,
  299. unsigned int *ndiv)
  300. {
  301. *mdiv_p0 = (p1 >> MDIV_P0_SHIFT) & MDIV_P0_MASK;
  302. *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK;
  303. *ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK;
  304. }
  305. static void brcm_avs_parse_p2(u32 p2, unsigned int *mdiv_p1,
  306. unsigned int *mdiv_p2, unsigned int *mdiv_p3,
  307. unsigned int *mdiv_p4)
  308. {
  309. *mdiv_p4 = (p2 >> MDIV_P4_SHIFT) & MDIV_P4_MASK;
  310. *mdiv_p3 = (p2 >> MDIV_P3_SHIFT) & MDIV_P3_MASK;
  311. *mdiv_p2 = (p2 >> MDIV_P2_SHIFT) & MDIV_P2_MASK;
  312. *mdiv_p1 = (p2 >> MDIV_P1_SHIFT) & MDIV_P1_MASK;
  313. }
  314. static int brcm_avs_get_pmap(struct private_data *priv, struct pmap *pmap)
  315. {
  316. u32 args[AVS_MAX_CMD_ARGS];
  317. int ret;
  318. ret = __issue_avs_command(priv, AVS_CMD_GET_PMAP, 0, 4, args);
  319. if (ret || !pmap)
  320. return ret;
  321. pmap->mode = args[0];
  322. pmap->p1 = args[1];
  323. pmap->p2 = args[2];
  324. pmap->state = args[3];
  325. return 0;
  326. }
  327. static int brcm_avs_set_pmap(struct private_data *priv, struct pmap *pmap)
  328. {
  329. u32 args[AVS_MAX_CMD_ARGS];
  330. args[0] = pmap->mode;
  331. args[1] = pmap->p1;
  332. args[2] = pmap->p2;
  333. args[3] = pmap->state;
  334. return __issue_avs_command(priv, AVS_CMD_SET_PMAP, 4, 0, args);
  335. }
  336. static int brcm_avs_get_pstate(struct private_data *priv, unsigned int *pstate)
  337. {
  338. u32 args[AVS_MAX_CMD_ARGS];
  339. int ret;
  340. ret = __issue_avs_command(priv, AVS_CMD_GET_PSTATE, 0, 1, args);
  341. if (ret)
  342. return ret;
  343. *pstate = args[0];
  344. return 0;
  345. }
  346. static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate)
  347. {
  348. u32 args[AVS_MAX_CMD_ARGS];
  349. args[0] = pstate;
  350. return __issue_avs_command(priv, AVS_CMD_SET_PSTATE, 1, 0, args);
  351. }
  352. static u32 brcm_avs_get_voltage(void __iomem *base)
  353. {
  354. return readl(base + AVS_MBOX_VOLTAGE1);
  355. }
  356. static u32 brcm_avs_get_frequency(void __iomem *base)
  357. {
  358. return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */
  359. }
  360. /*
  361. * We determine which frequencies are supported by cycling through all P-states
  362. * and reading back what frequency we are running at for each P-state.
  363. */
  364. static struct cpufreq_frequency_table *
  365. brcm_avs_get_freq_table(struct device *dev, struct private_data *priv)
  366. {
  367. struct cpufreq_frequency_table *table;
  368. unsigned int pstate;
  369. int i, ret;
  370. /* Remember P-state for later */
  371. ret = brcm_avs_get_pstate(priv, &pstate);
  372. if (ret)
  373. return ERR_PTR(ret);
  374. table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1, sizeof(*table),
  375. GFP_KERNEL);
  376. if (!table)
  377. return ERR_PTR(-ENOMEM);
  378. for (i = AVS_PSTATE_P0; i <= AVS_PSTATE_MAX; i++) {
  379. ret = brcm_avs_set_pstate(priv, i);
  380. if (ret)
  381. return ERR_PTR(ret);
  382. table[i].frequency = brcm_avs_get_frequency(priv->base);
  383. table[i].driver_data = i;
  384. }
  385. table[i].frequency = CPUFREQ_TABLE_END;
  386. /* Restore P-state */
  387. ret = brcm_avs_set_pstate(priv, pstate);
  388. if (ret)
  389. return ERR_PTR(ret);
  390. return table;
  391. }
  392. /*
  393. * To ensure the right firmware is running we need to
  394. * - check the MAGIC matches what we expect
  395. * - brcm_avs_get_pmap() doesn't return -ENOTSUPP or -EINVAL
  396. * We need to set up our interrupt handling before calling brcm_avs_get_pmap()!
  397. */
  398. static bool brcm_avs_is_firmware_loaded(struct private_data *priv)
  399. {
  400. u32 magic;
  401. int rc;
  402. rc = brcm_avs_get_pmap(priv, NULL);
  403. magic = readl(priv->base + AVS_MBOX_MAGIC);
  404. return (magic == AVS_FIRMWARE_MAGIC) && ((rc != -ENOTSUPP) ||
  405. (rc != -EINVAL));
  406. }
  407. static unsigned int brcm_avs_cpufreq_get(unsigned int cpu)
  408. {
  409. struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
  410. struct private_data *priv = policy->driver_data;
  411. cpufreq_cpu_put(policy);
  412. return brcm_avs_get_frequency(priv->base);
  413. }
  414. static int brcm_avs_target_index(struct cpufreq_policy *policy,
  415. unsigned int index)
  416. {
  417. return brcm_avs_set_pstate(policy->driver_data,
  418. policy->freq_table[index].driver_data);
  419. }
  420. static int brcm_avs_suspend(struct cpufreq_policy *policy)
  421. {
  422. struct private_data *priv = policy->driver_data;
  423. int ret;
  424. ret = brcm_avs_get_pmap(priv, &priv->pmap);
  425. if (ret)
  426. return ret;
  427. /*
  428. * We can't use the P-state returned by brcm_avs_get_pmap(), since
  429. * that's the initial P-state from when the P-map was downloaded to the
  430. * AVS co-processor, not necessarily the P-state we are running at now.
  431. * So, we get the current P-state explicitly.
  432. */
  433. ret = brcm_avs_get_pstate(priv, &priv->pmap.state);
  434. if (ret)
  435. return ret;
  436. /* This is best effort. Nothing to do if it fails. */
  437. (void)__issue_avs_command(priv, AVS_CMD_S2_ENTER, 0, 0, NULL);
  438. return 0;
  439. }
  440. static int brcm_avs_resume(struct cpufreq_policy *policy)
  441. {
  442. struct private_data *priv = policy->driver_data;
  443. int ret;
  444. /* This is best effort. Nothing to do if it fails. */
  445. (void)__issue_avs_command(priv, AVS_CMD_S2_EXIT, 0, 0, NULL);
  446. ret = brcm_avs_set_pmap(priv, &priv->pmap);
  447. if (ret == -EEXIST) {
  448. struct platform_device *pdev = cpufreq_get_driver_data();
  449. struct device *dev = &pdev->dev;
  450. dev_warn(dev, "PMAP was already set\n");
  451. ret = 0;
  452. }
  453. return ret;
  454. }
  455. /*
  456. * All initialization code that we only want to execute once goes here. Setup
  457. * code that can be re-tried on every core (if it failed before) can go into
  458. * brcm_avs_cpufreq_init().
  459. */
  460. static int brcm_avs_prepare_init(struct platform_device *pdev)
  461. {
  462. struct private_data *priv;
  463. struct device *dev;
  464. int ret;
  465. dev = &pdev->dev;
  466. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  467. if (!priv)
  468. return -ENOMEM;
  469. priv->dev = dev;
  470. sema_init(&priv->sem, 1);
  471. init_completion(&priv->done);
  472. platform_set_drvdata(pdev, priv);
  473. priv->base = __map_region(BRCM_AVS_CPU_DATA);
  474. if (!priv->base) {
  475. dev_err(dev, "Couldn't find property %s in device tree.\n",
  476. BRCM_AVS_CPU_DATA);
  477. return -ENOENT;
  478. }
  479. priv->avs_intr_base = __map_region(BRCM_AVS_CPU_INTR);
  480. if (!priv->avs_intr_base) {
  481. dev_err(dev, "Couldn't find property %s in device tree.\n",
  482. BRCM_AVS_CPU_INTR);
  483. ret = -ENOENT;
  484. goto unmap_base;
  485. }
  486. priv->host_irq = platform_get_irq_byname(pdev, BRCM_AVS_HOST_INTR);
  487. ret = devm_request_irq(dev, priv->host_irq, irq_handler,
  488. IRQF_TRIGGER_RISING,
  489. BRCM_AVS_HOST_INTR, priv);
  490. if (ret && priv->host_irq >= 0) {
  491. dev_err(dev, "IRQ request failed: %s (%d) -- %d\n",
  492. BRCM_AVS_HOST_INTR, priv->host_irq, ret);
  493. goto unmap_intr_base;
  494. }
  495. if (brcm_avs_is_firmware_loaded(priv))
  496. return 0;
  497. dev_err(dev, "AVS firmware is not loaded or doesn't support DVFS\n");
  498. ret = -ENODEV;
  499. unmap_intr_base:
  500. iounmap(priv->avs_intr_base);
  501. unmap_base:
  502. iounmap(priv->base);
  503. return ret;
  504. }
  505. static void brcm_avs_prepare_uninit(struct platform_device *pdev)
  506. {
  507. struct private_data *priv;
  508. priv = platform_get_drvdata(pdev);
  509. iounmap(priv->avs_intr_base);
  510. iounmap(priv->base);
  511. }
  512. static int brcm_avs_cpufreq_init(struct cpufreq_policy *policy)
  513. {
  514. struct cpufreq_frequency_table *freq_table;
  515. struct platform_device *pdev;
  516. struct private_data *priv;
  517. struct device *dev;
  518. int ret;
  519. pdev = cpufreq_get_driver_data();
  520. priv = platform_get_drvdata(pdev);
  521. policy->driver_data = priv;
  522. dev = &pdev->dev;
  523. freq_table = brcm_avs_get_freq_table(dev, priv);
  524. if (IS_ERR(freq_table)) {
  525. ret = PTR_ERR(freq_table);
  526. dev_err(dev, "Couldn't determine frequency table (%d).\n", ret);
  527. return ret;
  528. }
  529. policy->freq_table = freq_table;
  530. /* All cores share the same clock and thus the same policy. */
  531. cpumask_setall(policy->cpus);
  532. ret = __issue_avs_command(priv, AVS_CMD_ENABLE, 0, 0, NULL);
  533. if (!ret) {
  534. unsigned int pstate;
  535. ret = brcm_avs_get_pstate(priv, &pstate);
  536. if (!ret) {
  537. policy->cur = freq_table[pstate].frequency;
  538. dev_info(dev, "registered\n");
  539. return 0;
  540. }
  541. }
  542. dev_err(dev, "couldn't initialize driver (%d)\n", ret);
  543. return ret;
  544. }
  545. static ssize_t show_brcm_avs_pstate(struct cpufreq_policy *policy, char *buf)
  546. {
  547. struct private_data *priv = policy->driver_data;
  548. unsigned int pstate;
  549. if (brcm_avs_get_pstate(priv, &pstate))
  550. return sprintf(buf, "<unknown>\n");
  551. return sprintf(buf, "%u\n", pstate);
  552. }
  553. static ssize_t show_brcm_avs_mode(struct cpufreq_policy *policy, char *buf)
  554. {
  555. struct private_data *priv = policy->driver_data;
  556. struct pmap pmap;
  557. if (brcm_avs_get_pmap(priv, &pmap))
  558. return sprintf(buf, "<unknown>\n");
  559. return sprintf(buf, "%s %u\n", brcm_avs_mode_to_string(pmap.mode),
  560. pmap.mode);
  561. }
  562. static ssize_t show_brcm_avs_pmap(struct cpufreq_policy *policy, char *buf)
  563. {
  564. unsigned int mdiv_p0, mdiv_p1, mdiv_p2, mdiv_p3, mdiv_p4;
  565. struct private_data *priv = policy->driver_data;
  566. unsigned int ndiv, pdiv;
  567. struct pmap pmap;
  568. if (brcm_avs_get_pmap(priv, &pmap))
  569. return sprintf(buf, "<unknown>\n");
  570. brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv);
  571. brcm_avs_parse_p2(pmap.p2, &mdiv_p1, &mdiv_p2, &mdiv_p3, &mdiv_p4);
  572. return sprintf(buf, "0x%08x 0x%08x %u %u %u %u %u %u %u %u %u\n",
  573. pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2,
  574. mdiv_p3, mdiv_p4, pmap.mode, pmap.state);
  575. }
  576. static ssize_t show_brcm_avs_voltage(struct cpufreq_policy *policy, char *buf)
  577. {
  578. struct private_data *priv = policy->driver_data;
  579. return sprintf(buf, "0x%08x\n", brcm_avs_get_voltage(priv->base));
  580. }
  581. static ssize_t show_brcm_avs_frequency(struct cpufreq_policy *policy, char *buf)
  582. {
  583. struct private_data *priv = policy->driver_data;
  584. return sprintf(buf, "0x%08x\n", brcm_avs_get_frequency(priv->base));
  585. }
  586. cpufreq_freq_attr_ro(brcm_avs_pstate);
  587. cpufreq_freq_attr_ro(brcm_avs_mode);
  588. cpufreq_freq_attr_ro(brcm_avs_pmap);
  589. cpufreq_freq_attr_ro(brcm_avs_voltage);
  590. cpufreq_freq_attr_ro(brcm_avs_frequency);
  591. static struct freq_attr *brcm_avs_cpufreq_attr[] = {
  592. &cpufreq_freq_attr_scaling_available_freqs,
  593. &brcm_avs_pstate,
  594. &brcm_avs_mode,
  595. &brcm_avs_pmap,
  596. &brcm_avs_voltage,
  597. &brcm_avs_frequency,
  598. NULL
  599. };
  600. static struct cpufreq_driver brcm_avs_driver = {
  601. .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
  602. .verify = cpufreq_generic_frequency_table_verify,
  603. .target_index = brcm_avs_target_index,
  604. .get = brcm_avs_cpufreq_get,
  605. .suspend = brcm_avs_suspend,
  606. .resume = brcm_avs_resume,
  607. .init = brcm_avs_cpufreq_init,
  608. .attr = brcm_avs_cpufreq_attr,
  609. .name = BRCM_AVS_CPUFREQ_PREFIX,
  610. };
  611. static int brcm_avs_cpufreq_probe(struct platform_device *pdev)
  612. {
  613. int ret;
  614. ret = brcm_avs_prepare_init(pdev);
  615. if (ret)
  616. return ret;
  617. brcm_avs_driver.driver_data = pdev;
  618. ret = cpufreq_register_driver(&brcm_avs_driver);
  619. if (ret)
  620. brcm_avs_prepare_uninit(pdev);
  621. return ret;
  622. }
  623. static int brcm_avs_cpufreq_remove(struct platform_device *pdev)
  624. {
  625. int ret;
  626. ret = cpufreq_unregister_driver(&brcm_avs_driver);
  627. WARN_ON(ret);
  628. brcm_avs_prepare_uninit(pdev);
  629. return 0;
  630. }
  631. static const struct of_device_id brcm_avs_cpufreq_match[] = {
  632. { .compatible = BRCM_AVS_CPU_DATA },
  633. { }
  634. };
  635. MODULE_DEVICE_TABLE(of, brcm_avs_cpufreq_match);
  636. static struct platform_driver brcm_avs_cpufreq_platdrv = {
  637. .driver = {
  638. .name = BRCM_AVS_CPUFREQ_NAME,
  639. .of_match_table = brcm_avs_cpufreq_match,
  640. },
  641. .probe = brcm_avs_cpufreq_probe,
  642. .remove = brcm_avs_cpufreq_remove,
  643. };
  644. module_platform_driver(brcm_avs_cpufreq_platdrv);
  645. MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
  646. MODULE_DESCRIPTION("CPUfreq driver for Broadcom STB AVS");
  647. MODULE_LICENSE("GPL");