pll.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Zynq UltraScale+ MPSoC PLL driver
  4. *
  5. * Copyright (C) 2016-2018 Xilinx
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/slab.h>
  10. #include "clk-zynqmp.h"
  11. /**
  12. * struct zynqmp_pll - PLL clock
  13. * @hw: Handle between common and hardware-specific interfaces
  14. * @clk_id: PLL clock ID
  15. * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
  16. */
  17. struct zynqmp_pll {
  18. struct clk_hw hw;
  19. u32 clk_id;
  20. bool set_pll_mode;
  21. };
  22. #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
  23. #define PLL_FBDIV_MIN 25
  24. #define PLL_FBDIV_MAX 125
  25. #define PS_PLL_VCO_MIN 1500000000
  26. #define PS_PLL_VCO_MAX 3000000000UL
  27. enum pll_mode {
  28. PLL_MODE_INT,
  29. PLL_MODE_FRAC,
  30. };
  31. #define FRAC_OFFSET 0x8
  32. #define PLLFCFG_FRAC_EN BIT(31)
  33. #define FRAC_DIV BIT(16) /* 2^16 */
  34. /**
  35. * zynqmp_pll_get_mode() - Get mode of PLL
  36. * @hw: Handle between common and hardware-specific interfaces
  37. *
  38. * Return: Mode of PLL
  39. */
  40. static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
  41. {
  42. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  43. u32 clk_id = clk->clk_id;
  44. const char *clk_name = clk_hw_get_name(hw);
  45. u32 ret_payload[PAYLOAD_ARG_CNT];
  46. int ret;
  47. ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
  48. if (ret)
  49. pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
  50. __func__, clk_name, ret);
  51. return ret_payload[1];
  52. }
  53. /**
  54. * zynqmp_pll_set_mode() - Set the PLL mode
  55. * @hw: Handle between common and hardware-specific interfaces
  56. * @on: Flag to determine the mode
  57. */
  58. static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
  59. {
  60. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  61. u32 clk_id = clk->clk_id;
  62. const char *clk_name = clk_hw_get_name(hw);
  63. int ret;
  64. u32 mode;
  65. if (on)
  66. mode = PLL_MODE_FRAC;
  67. else
  68. mode = PLL_MODE_INT;
  69. ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
  70. if (ret)
  71. pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
  72. __func__, clk_name, ret);
  73. else
  74. clk->set_pll_mode = true;
  75. }
  76. /**
  77. * zynqmp_pll_round_rate() - Round a clock frequency
  78. * @hw: Handle between common and hardware-specific interfaces
  79. * @rate: Desired clock frequency
  80. * @prate: Clock frequency of parent clock
  81. *
  82. * Return: Frequency closest to @rate the hardware can generate
  83. */
  84. static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  85. unsigned long *prate)
  86. {
  87. u32 fbdiv;
  88. long rate_div, f;
  89. /* Enable the fractional mode if needed */
  90. rate_div = (rate * FRAC_DIV) / *prate;
  91. f = rate_div % FRAC_DIV;
  92. if (f) {
  93. if (rate > PS_PLL_VCO_MAX) {
  94. fbdiv = rate / PS_PLL_VCO_MAX;
  95. rate = rate / (fbdiv + 1);
  96. }
  97. if (rate < PS_PLL_VCO_MIN) {
  98. fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
  99. rate = rate * fbdiv;
  100. }
  101. return rate;
  102. }
  103. fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
  104. fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
  105. return *prate * fbdiv;
  106. }
  107. /**
  108. * zynqmp_pll_recalc_rate() - Recalculate clock frequency
  109. * @hw: Handle between common and hardware-specific interfaces
  110. * @parent_rate: Clock frequency of parent clock
  111. *
  112. * Return: Current clock frequency
  113. */
  114. static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
  115. unsigned long parent_rate)
  116. {
  117. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  118. u32 clk_id = clk->clk_id;
  119. const char *clk_name = clk_hw_get_name(hw);
  120. u32 fbdiv, data;
  121. unsigned long rate, frac;
  122. u32 ret_payload[PAYLOAD_ARG_CNT];
  123. int ret;
  124. ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
  125. if (ret)
  126. pr_warn_once("%s() get divider failed for %s, ret = %d\n",
  127. __func__, clk_name, ret);
  128. rate = parent_rate * fbdiv;
  129. if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
  130. zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
  131. data = ret_payload[1];
  132. frac = (parent_rate * data) / FRAC_DIV;
  133. rate = rate + frac;
  134. }
  135. return rate;
  136. }
  137. /**
  138. * zynqmp_pll_set_rate() - Set rate of PLL
  139. * @hw: Handle between common and hardware-specific interfaces
  140. * @rate: Frequency of clock to be set
  141. * @parent_rate: Clock frequency of parent clock
  142. *
  143. * Set PLL divider to set desired rate.
  144. *
  145. * Returns: rate which is set on success else error code
  146. */
  147. static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  148. unsigned long parent_rate)
  149. {
  150. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  151. u32 clk_id = clk->clk_id;
  152. const char *clk_name = clk_hw_get_name(hw);
  153. u32 fbdiv;
  154. long rate_div, frac, m, f;
  155. int ret;
  156. rate_div = (rate * FRAC_DIV) / parent_rate;
  157. f = rate_div % FRAC_DIV;
  158. zynqmp_pll_set_mode(hw, !!f);
  159. if (f) {
  160. m = rate_div / FRAC_DIV;
  161. m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
  162. rate = parent_rate * m;
  163. frac = (parent_rate * f) / FRAC_DIV;
  164. ret = zynqmp_pm_clock_setdivider(clk_id, m);
  165. if (ret == -EUSERS)
  166. WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
  167. clk_name);
  168. else if (ret)
  169. pr_warn_once("%s() set divider failed for %s, ret = %d\n",
  170. __func__, clk_name, ret);
  171. zynqmp_pm_set_pll_frac_data(clk_id, f);
  172. return rate + frac;
  173. }
  174. fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
  175. fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
  176. ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
  177. if (ret)
  178. pr_warn_once("%s() set divider failed for %s, ret = %d\n",
  179. __func__, clk_name, ret);
  180. return parent_rate * fbdiv;
  181. }
  182. /**
  183. * zynqmp_pll_is_enabled() - Check if a clock is enabled
  184. * @hw: Handle between common and hardware-specific interfaces
  185. *
  186. * Return: 1 if the clock is enabled, 0 otherwise
  187. */
  188. static int zynqmp_pll_is_enabled(struct clk_hw *hw)
  189. {
  190. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  191. const char *clk_name = clk_hw_get_name(hw);
  192. u32 clk_id = clk->clk_id;
  193. unsigned int state;
  194. int ret;
  195. ret = zynqmp_pm_clock_getstate(clk_id, &state);
  196. if (ret) {
  197. pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
  198. __func__, clk_name, ret);
  199. return -EIO;
  200. }
  201. return state ? 1 : 0;
  202. }
  203. /**
  204. * zynqmp_pll_enable() - Enable clock
  205. * @hw: Handle between common and hardware-specific interfaces
  206. *
  207. * Return: 0 on success else error code
  208. */
  209. static int zynqmp_pll_enable(struct clk_hw *hw)
  210. {
  211. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  212. const char *clk_name = clk_hw_get_name(hw);
  213. u32 clk_id = clk->clk_id;
  214. int ret;
  215. /*
  216. * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
  217. * that has been sent to ATF.
  218. */
  219. if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
  220. return 0;
  221. clk->set_pll_mode = false;
  222. ret = zynqmp_pm_clock_enable(clk_id);
  223. if (ret)
  224. pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
  225. __func__, clk_name, ret);
  226. return ret;
  227. }
  228. /**
  229. * zynqmp_pll_disable() - Disable clock
  230. * @hw: Handle between common and hardware-specific interfaces
  231. */
  232. static void zynqmp_pll_disable(struct clk_hw *hw)
  233. {
  234. struct zynqmp_pll *clk = to_zynqmp_pll(hw);
  235. const char *clk_name = clk_hw_get_name(hw);
  236. u32 clk_id = clk->clk_id;
  237. int ret;
  238. if (!zynqmp_pll_is_enabled(hw))
  239. return;
  240. ret = zynqmp_pm_clock_disable(clk_id);
  241. if (ret)
  242. pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
  243. __func__, clk_name, ret);
  244. }
  245. static const struct clk_ops zynqmp_pll_ops = {
  246. .enable = zynqmp_pll_enable,
  247. .disable = zynqmp_pll_disable,
  248. .is_enabled = zynqmp_pll_is_enabled,
  249. .round_rate = zynqmp_pll_round_rate,
  250. .recalc_rate = zynqmp_pll_recalc_rate,
  251. .set_rate = zynqmp_pll_set_rate,
  252. };
  253. /**
  254. * zynqmp_clk_register_pll() - Register PLL with the clock framework
  255. * @name: PLL name
  256. * @clk_id: Clock ID
  257. * @parents: Name of this clock's parents
  258. * @num_parents: Number of parents
  259. * @nodes: Clock topology node
  260. *
  261. * Return: clock hardware to the registered clock
  262. */
  263. struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
  264. const char * const *parents,
  265. u8 num_parents,
  266. const struct clock_topology *nodes)
  267. {
  268. struct zynqmp_pll *pll;
  269. struct clk_hw *hw;
  270. struct clk_init_data init;
  271. int ret;
  272. init.name = name;
  273. init.ops = &zynqmp_pll_ops;
  274. init.flags = nodes->flag;
  275. init.parent_names = parents;
  276. init.num_parents = 1;
  277. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  278. if (!pll)
  279. return ERR_PTR(-ENOMEM);
  280. pll->hw.init = &init;
  281. pll->clk_id = clk_id;
  282. hw = &pll->hw;
  283. ret = clk_hw_register(NULL, hw);
  284. if (ret) {
  285. kfree(pll);
  286. return ERR_PTR(ret);
  287. }
  288. clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
  289. if (ret < 0)
  290. pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
  291. return hw;
  292. }