divider.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Zynq UltraScale+ MPSoC Divider support
  4. *
  5. * Copyright (C) 2016-2019 Xilinx
  6. *
  7. * Adjustable divider clock implementation
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/slab.h>
  12. #include "clk-zynqmp.h"
  13. /*
  14. * DOC: basic adjustable divider clock that cannot gate
  15. *
  16. * Traits of this clock:
  17. * prepare - clk_prepare only ensures that parents are prepared
  18. * enable - clk_enable only ensures that parents are enabled
  19. * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
  20. * parent - fixed parent. No clk_set_parent support
  21. */
  22. #define to_zynqmp_clk_divider(_hw) \
  23. container_of(_hw, struct zynqmp_clk_divider, hw)
  24. #define CLK_FRAC BIT(13) /* has a fractional parent */
  25. #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
  26. /**
  27. * struct zynqmp_clk_divider - adjustable divider clock
  28. * @hw: handle between common and hardware-specific interfaces
  29. * @flags: Hardware specific flags
  30. * @is_frac: The divider is a fractional divider
  31. * @clk_id: Id of clock
  32. * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
  33. */
  34. struct zynqmp_clk_divider {
  35. struct clk_hw hw;
  36. u8 flags;
  37. bool is_frac;
  38. u32 clk_id;
  39. u32 div_type;
  40. u16 max_div;
  41. };
  42. static inline int zynqmp_divider_get_val(unsigned long parent_rate,
  43. unsigned long rate, u16 flags)
  44. {
  45. int up, down;
  46. unsigned long up_rate, down_rate;
  47. if (flags & CLK_DIVIDER_POWER_OF_TWO) {
  48. up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  49. down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
  50. up = __roundup_pow_of_two(up);
  51. down = __rounddown_pow_of_two(down);
  52. up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
  53. down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
  54. return (rate - up_rate) <= (down_rate - rate) ? up : down;
  55. } else {
  56. return DIV_ROUND_CLOSEST(parent_rate, rate);
  57. }
  58. }
  59. /**
  60. * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
  61. * @hw: handle between common and hardware-specific interfaces
  62. * @parent_rate: rate of parent clock
  63. *
  64. * Return: 0 on success else error+reason
  65. */
  66. static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
  67. unsigned long parent_rate)
  68. {
  69. struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
  70. const char *clk_name = clk_hw_get_name(hw);
  71. u32 clk_id = divider->clk_id;
  72. u32 div_type = divider->div_type;
  73. u32 div, value;
  74. int ret;
  75. ret = zynqmp_pm_clock_getdivider(clk_id, &div);
  76. if (ret)
  77. pr_warn_once("%s() get divider failed for %s, ret = %d\n",
  78. __func__, clk_name, ret);
  79. if (div_type == TYPE_DIV1)
  80. value = div & 0xFFFF;
  81. else
  82. value = div >> 16;
  83. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  84. value = 1 << value;
  85. if (!value) {
  86. WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
  87. "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  88. clk_name);
  89. return parent_rate;
  90. }
  91. return DIV_ROUND_UP_ULL(parent_rate, value);
  92. }
  93. static void zynqmp_get_divider2_val(struct clk_hw *hw,
  94. unsigned long rate,
  95. struct zynqmp_clk_divider *divider,
  96. int *bestdiv)
  97. {
  98. int div1;
  99. int div2;
  100. long error = LONG_MAX;
  101. unsigned long div1_prate;
  102. struct clk_hw *div1_parent_hw;
  103. struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
  104. struct zynqmp_clk_divider *pdivider =
  105. to_zynqmp_clk_divider(div2_parent_hw);
  106. if (!pdivider)
  107. return;
  108. div1_parent_hw = clk_hw_get_parent(div2_parent_hw);
  109. if (!div1_parent_hw)
  110. return;
  111. div1_prate = clk_hw_get_rate(div1_parent_hw);
  112. *bestdiv = 1;
  113. for (div1 = 1; div1 <= pdivider->max_div;) {
  114. for (div2 = 1; div2 <= divider->max_div;) {
  115. long new_error = ((div1_prate / div1) / div2) - rate;
  116. if (abs(new_error) < abs(error)) {
  117. *bestdiv = div2;
  118. error = new_error;
  119. }
  120. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  121. div2 = div2 << 1;
  122. else
  123. div2++;
  124. }
  125. if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)
  126. div1 = div1 << 1;
  127. else
  128. div1++;
  129. }
  130. }
  131. /**
  132. * zynqmp_clk_divider_round_rate() - Round rate of divider clock
  133. * @hw: handle between common and hardware-specific interfaces
  134. * @rate: rate of clock to be set
  135. * @prate: rate of parent clock
  136. *
  137. * Return: 0 on success else error+reason
  138. */
  139. static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
  140. unsigned long rate,
  141. unsigned long *prate)
  142. {
  143. struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
  144. const char *clk_name = clk_hw_get_name(hw);
  145. u32 clk_id = divider->clk_id;
  146. u32 div_type = divider->div_type;
  147. u32 bestdiv;
  148. int ret;
  149. /* if read only, just return current value */
  150. if (divider->flags & CLK_DIVIDER_READ_ONLY) {
  151. ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);
  152. if (ret)
  153. pr_warn_once("%s() get divider failed for %s, ret = %d\n",
  154. __func__, clk_name, ret);
  155. if (div_type == TYPE_DIV1)
  156. bestdiv = bestdiv & 0xFFFF;
  157. else
  158. bestdiv = bestdiv >> 16;
  159. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  160. bestdiv = 1 << bestdiv;
  161. return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
  162. }
  163. bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
  164. /*
  165. * In case of two divisors, compute best divider values and return
  166. * divider2 value based on compute value. div1 will be automatically
  167. * set to optimum based on required total divider value.
  168. */
  169. if (div_type == TYPE_DIV2 &&
  170. (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
  171. zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
  172. }
  173. if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
  174. bestdiv = rate % *prate ? 1 : bestdiv;
  175. bestdiv = min_t(u32, bestdiv, divider->max_div);
  176. *prate = rate * bestdiv;
  177. return rate;
  178. }
  179. /**
  180. * zynqmp_clk_divider_set_rate() - Set rate of divider clock
  181. * @hw: handle between common and hardware-specific interfaces
  182. * @rate: rate of clock to be set
  183. * @parent_rate: rate of parent clock
  184. *
  185. * Return: 0 on success else error+reason
  186. */
  187. static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
  188. unsigned long parent_rate)
  189. {
  190. struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
  191. const char *clk_name = clk_hw_get_name(hw);
  192. u32 clk_id = divider->clk_id;
  193. u32 div_type = divider->div_type;
  194. u32 value, div;
  195. int ret;
  196. value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
  197. if (div_type == TYPE_DIV1) {
  198. div = value & 0xFFFF;
  199. div |= 0xffff << 16;
  200. } else {
  201. div = 0xffff;
  202. div |= value << 16;
  203. }
  204. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  205. div = __ffs(div);
  206. ret = zynqmp_pm_clock_setdivider(clk_id, div);
  207. if (ret)
  208. pr_warn_once("%s() set divider failed for %s, ret = %d\n",
  209. __func__, clk_name, ret);
  210. return ret;
  211. }
  212. static const struct clk_ops zynqmp_clk_divider_ops = {
  213. .recalc_rate = zynqmp_clk_divider_recalc_rate,
  214. .round_rate = zynqmp_clk_divider_round_rate,
  215. .set_rate = zynqmp_clk_divider_set_rate,
  216. };
  217. /**
  218. * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
  219. * @clk_id: Id of clock
  220. * @type: Divider type
  221. *
  222. * Return: Maximum divisor of a clock if query data is successful
  223. * U16_MAX in case of query data is not success
  224. */
  225. static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
  226. {
  227. struct zynqmp_pm_query_data qdata = {0};
  228. u32 ret_payload[PAYLOAD_ARG_CNT];
  229. int ret;
  230. qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
  231. qdata.arg1 = clk_id;
  232. qdata.arg2 = type;
  233. ret = zynqmp_pm_query_data(qdata, ret_payload);
  234. /*
  235. * To maintain backward compatibility return maximum possible value
  236. * (0xFFFF) if query for max divisor is not successful.
  237. */
  238. if (ret)
  239. return U16_MAX;
  240. return ret_payload[1];
  241. }
  242. /**
  243. * zynqmp_clk_register_divider() - Register a divider clock
  244. * @name: Name of this clock
  245. * @clk_id: Id of clock
  246. * @parents: Name of this clock's parents
  247. * @num_parents: Number of parents
  248. * @nodes: Clock topology node
  249. *
  250. * Return: clock hardware to registered clock divider
  251. */
  252. struct clk_hw *zynqmp_clk_register_divider(const char *name,
  253. u32 clk_id,
  254. const char * const *parents,
  255. u8 num_parents,
  256. const struct clock_topology *nodes)
  257. {
  258. struct zynqmp_clk_divider *div;
  259. struct clk_hw *hw;
  260. struct clk_init_data init;
  261. int ret;
  262. /* allocate the divider */
  263. div = kzalloc(sizeof(*div), GFP_KERNEL);
  264. if (!div)
  265. return ERR_PTR(-ENOMEM);
  266. init.name = name;
  267. init.ops = &zynqmp_clk_divider_ops;
  268. /* CLK_FRAC is not defined in the common clk framework */
  269. init.flags = nodes->flag & ~CLK_FRAC;
  270. init.parent_names = parents;
  271. init.num_parents = 1;
  272. /* struct clk_divider assignments */
  273. div->is_frac = !!((nodes->flag & CLK_FRAC) |
  274. (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
  275. div->flags = nodes->type_flag;
  276. div->hw.init = &init;
  277. div->clk_id = clk_id;
  278. div->div_type = nodes->type;
  279. /*
  280. * To achieve best possible rate, maximum limit of divider is required
  281. * while computation.
  282. */
  283. div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
  284. hw = &div->hw;
  285. ret = clk_hw_register(NULL, hw);
  286. if (ret) {
  287. kfree(div);
  288. hw = ERR_PTR(ret);
  289. }
  290. return hw;
  291. }