clk-zynqmp.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2016-2018 Xilinx
  4. */
  5. #ifndef __LINUX_CLK_ZYNQMP_H_
  6. #define __LINUX_CLK_ZYNQMP_H_
  7. #include <linux/spinlock.h>
  8. #include <linux/firmware/xlnx-zynqmp.h>
  9. enum topology_type {
  10. TYPE_INVALID,
  11. TYPE_MUX,
  12. TYPE_PLL,
  13. TYPE_FIXEDFACTOR,
  14. TYPE_DIV1,
  15. TYPE_DIV2,
  16. TYPE_GATE,
  17. };
  18. /**
  19. * struct clock_topology - Clock topology
  20. * @type: Type of topology
  21. * @flag: Topology flags
  22. * @type_flag: Topology type specific flag
  23. */
  24. struct clock_topology {
  25. u32 type;
  26. u32 flag;
  27. u32 type_flag;
  28. u8 custom_type_flag;
  29. };
  30. struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
  31. const char * const *parents,
  32. u8 num_parents,
  33. const struct clock_topology *nodes);
  34. struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
  35. const char * const *parents,
  36. u8 num_parents,
  37. const struct clock_topology *nodes);
  38. struct clk_hw *zynqmp_clk_register_divider(const char *name,
  39. u32 clk_id,
  40. const char * const *parents,
  41. u8 num_parents,
  42. const struct clock_topology *nodes);
  43. struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
  44. const char * const *parents,
  45. u8 num_parents,
  46. const struct clock_topology *nodes);
  47. struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
  48. u32 clk_id,
  49. const char * const *parents,
  50. u8 num_parents,
  51. const struct clock_topology *nodes);
  52. #endif