clk-mux-zynqmp.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Zynq UltraScale+ MPSoC mux
  4. *
  5. * Copyright (C) 2016-2018 Xilinx
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/slab.h>
  9. #include "clk-zynqmp.h"
  10. /*
  11. * DOC: basic adjustable multiplexer clock that cannot gate
  12. *
  13. * Traits of this clock:
  14. * prepare - clk_prepare only ensures that parents are prepared
  15. * enable - clk_enable only ensures that parents are enabled
  16. * rate - rate is only affected by parent switching. No clk_set_rate support
  17. * parent - parent is adjustable through clk_set_parent
  18. */
  19. /**
  20. * struct zynqmp_clk_mux - multiplexer clock
  21. *
  22. * @hw: handle between common and hardware-specific interfaces
  23. * @flags: hardware-specific flags
  24. * @clk_id: Id of clock
  25. */
  26. struct zynqmp_clk_mux {
  27. struct clk_hw hw;
  28. u8 flags;
  29. u32 clk_id;
  30. };
  31. #define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
  32. /**
  33. * zynqmp_clk_mux_get_parent() - Get parent of clock
  34. * @hw: handle between common and hardware-specific interfaces
  35. *
  36. * Return: Parent index
  37. */
  38. static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
  39. {
  40. struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
  41. const char *clk_name = clk_hw_get_name(hw);
  42. u32 clk_id = mux->clk_id;
  43. u32 val;
  44. int ret;
  45. ret = zynqmp_pm_clock_getparent(clk_id, &val);
  46. if (ret)
  47. pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
  48. __func__, clk_name, ret);
  49. return val;
  50. }
  51. /**
  52. * zynqmp_clk_mux_set_parent() - Set parent of clock
  53. * @hw: handle between common and hardware-specific interfaces
  54. * @index: Parent index
  55. *
  56. * Return: 0 on success else error+reason
  57. */
  58. static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  59. {
  60. struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
  61. const char *clk_name = clk_hw_get_name(hw);
  62. u32 clk_id = mux->clk_id;
  63. int ret;
  64. ret = zynqmp_pm_clock_setparent(clk_id, index);
  65. if (ret)
  66. pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
  67. __func__, clk_name, ret);
  68. return ret;
  69. }
  70. static const struct clk_ops zynqmp_clk_mux_ops = {
  71. .get_parent = zynqmp_clk_mux_get_parent,
  72. .set_parent = zynqmp_clk_mux_set_parent,
  73. .determine_rate = __clk_mux_determine_rate,
  74. };
  75. static const struct clk_ops zynqmp_clk_mux_ro_ops = {
  76. .get_parent = zynqmp_clk_mux_get_parent,
  77. };
  78. /**
  79. * zynqmp_clk_register_mux() - Register a mux table with the clock
  80. * framework
  81. * @name: Name of this clock
  82. * @clk_id: Id of this clock
  83. * @parents: Name of this clock's parents
  84. * @num_parents: Number of parents
  85. * @nodes: Clock topology node
  86. *
  87. * Return: clock hardware of the registered clock mux
  88. */
  89. struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
  90. const char * const *parents,
  91. u8 num_parents,
  92. const struct clock_topology *nodes)
  93. {
  94. struct zynqmp_clk_mux *mux;
  95. struct clk_hw *hw;
  96. struct clk_init_data init;
  97. int ret;
  98. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  99. if (!mux)
  100. return ERR_PTR(-ENOMEM);
  101. init.name = name;
  102. if (nodes->type_flag & CLK_MUX_READ_ONLY)
  103. init.ops = &zynqmp_clk_mux_ro_ops;
  104. else
  105. init.ops = &zynqmp_clk_mux_ops;
  106. init.flags = nodes->flag;
  107. init.parent_names = parents;
  108. init.num_parents = num_parents;
  109. mux->flags = nodes->type_flag;
  110. mux->hw.init = &init;
  111. mux->clk_id = clk_id;
  112. hw = &mux->hw;
  113. ret = clk_hw_register(NULL, hw);
  114. if (ret) {
  115. kfree(hw);
  116. hw = ERR_PTR(ret);
  117. }
  118. return hw;
  119. }