pll.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Zynq PLL driver
  4. *
  5. * Copyright (C) 2013 Xilinx
  6. *
  7. * Sören Brinkmann <soren.brinkmann@xilinx.com>
  8. */
  9. #include <linux/clk/zynq.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/slab.h>
  12. #include <linux/io.h>
  13. /**
  14. * struct zynq_pll
  15. * @hw: Handle between common and hardware-specific interfaces
  16. * @pll_ctrl: PLL control register
  17. * @pll_status: PLL status register
  18. * @lock: Register lock
  19. * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
  20. * register.
  21. */
  22. struct zynq_pll {
  23. struct clk_hw hw;
  24. void __iomem *pll_ctrl;
  25. void __iomem *pll_status;
  26. spinlock_t *lock;
  27. u8 lockbit;
  28. };
  29. #define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw)
  30. /* Register bitfield defines */
  31. #define PLLCTRL_FBDIV_MASK 0x7f000
  32. #define PLLCTRL_FBDIV_SHIFT 12
  33. #define PLLCTRL_BPQUAL_MASK (1 << 3)
  34. #define PLLCTRL_PWRDWN_MASK 2
  35. #define PLLCTRL_PWRDWN_SHIFT 1
  36. #define PLLCTRL_RESET_MASK 1
  37. #define PLLCTRL_RESET_SHIFT 0
  38. #define PLL_FBDIV_MIN 13
  39. #define PLL_FBDIV_MAX 66
  40. /**
  41. * zynq_pll_round_rate() - Round a clock frequency
  42. * @hw: Handle between common and hardware-specific interfaces
  43. * @rate: Desired clock frequency
  44. * @prate: Clock frequency of parent clock
  45. * Returns frequency closest to @rate the hardware can generate.
  46. */
  47. static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  48. unsigned long *prate)
  49. {
  50. u32 fbdiv;
  51. fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
  52. if (fbdiv < PLL_FBDIV_MIN)
  53. fbdiv = PLL_FBDIV_MIN;
  54. else if (fbdiv > PLL_FBDIV_MAX)
  55. fbdiv = PLL_FBDIV_MAX;
  56. return *prate * fbdiv;
  57. }
  58. /**
  59. * zynq_pll_recalc_rate() - Recalculate clock frequency
  60. * @hw: Handle between common and hardware-specific interfaces
  61. * @parent_rate: Clock frequency of parent clock
  62. * Returns current clock frequency.
  63. */
  64. static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
  65. unsigned long parent_rate)
  66. {
  67. struct zynq_pll *clk = to_zynq_pll(hw);
  68. u32 fbdiv;
  69. /*
  70. * makes probably sense to redundantly save fbdiv in the struct
  71. * zynq_pll to save the IO access.
  72. */
  73. fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
  74. PLLCTRL_FBDIV_SHIFT;
  75. return parent_rate * fbdiv;
  76. }
  77. /**
  78. * zynq_pll_is_enabled - Check if a clock is enabled
  79. * @hw: Handle between common and hardware-specific interfaces
  80. * Returns 1 if the clock is enabled, 0 otherwise.
  81. *
  82. * Not sure this is a good idea, but since disabled means bypassed for
  83. * this clock implementation we say we are always enabled.
  84. */
  85. static int zynq_pll_is_enabled(struct clk_hw *hw)
  86. {
  87. unsigned long flags = 0;
  88. u32 reg;
  89. struct zynq_pll *clk = to_zynq_pll(hw);
  90. spin_lock_irqsave(clk->lock, flags);
  91. reg = readl(clk->pll_ctrl);
  92. spin_unlock_irqrestore(clk->lock, flags);
  93. return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
  94. }
  95. /**
  96. * zynq_pll_enable - Enable clock
  97. * @hw: Handle between common and hardware-specific interfaces
  98. * Returns 0 on success
  99. */
  100. static int zynq_pll_enable(struct clk_hw *hw)
  101. {
  102. unsigned long flags = 0;
  103. u32 reg;
  104. struct zynq_pll *clk = to_zynq_pll(hw);
  105. if (zynq_pll_is_enabled(hw))
  106. return 0;
  107. pr_info("PLL: enable\n");
  108. /* Power up PLL and wait for lock */
  109. spin_lock_irqsave(clk->lock, flags);
  110. reg = readl(clk->pll_ctrl);
  111. reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
  112. writel(reg, clk->pll_ctrl);
  113. while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
  114. ;
  115. spin_unlock_irqrestore(clk->lock, flags);
  116. return 0;
  117. }
  118. /**
  119. * zynq_pll_disable - Disable clock
  120. * @hw: Handle between common and hardware-specific interfaces
  121. * Returns 0 on success
  122. */
  123. static void zynq_pll_disable(struct clk_hw *hw)
  124. {
  125. unsigned long flags = 0;
  126. u32 reg;
  127. struct zynq_pll *clk = to_zynq_pll(hw);
  128. if (!zynq_pll_is_enabled(hw))
  129. return;
  130. pr_info("PLL: shutdown\n");
  131. /* shut down PLL */
  132. spin_lock_irqsave(clk->lock, flags);
  133. reg = readl(clk->pll_ctrl);
  134. reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
  135. writel(reg, clk->pll_ctrl);
  136. spin_unlock_irqrestore(clk->lock, flags);
  137. }
  138. static const struct clk_ops zynq_pll_ops = {
  139. .enable = zynq_pll_enable,
  140. .disable = zynq_pll_disable,
  141. .is_enabled = zynq_pll_is_enabled,
  142. .round_rate = zynq_pll_round_rate,
  143. .recalc_rate = zynq_pll_recalc_rate
  144. };
  145. /**
  146. * clk_register_zynq_pll() - Register PLL with the clock framework
  147. * @name PLL name
  148. * @parent Parent clock name
  149. * @pll_ctrl Pointer to PLL control register
  150. * @pll_status Pointer to PLL status register
  151. * @lock_index Bit index to this PLL's lock status bit in @pll_status
  152. * @lock Register lock
  153. * Returns handle to the registered clock.
  154. */
  155. struct clk *clk_register_zynq_pll(const char *name, const char *parent,
  156. void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
  157. spinlock_t *lock)
  158. {
  159. struct zynq_pll *pll;
  160. struct clk *clk;
  161. u32 reg;
  162. const char *parent_arr[1] = {parent};
  163. unsigned long flags = 0;
  164. struct clk_init_data initd = {
  165. .name = name,
  166. .parent_names = parent_arr,
  167. .ops = &zynq_pll_ops,
  168. .num_parents = 1,
  169. .flags = 0
  170. };
  171. pll = kmalloc(sizeof(*pll), GFP_KERNEL);
  172. if (!pll)
  173. return ERR_PTR(-ENOMEM);
  174. /* Populate the struct */
  175. pll->hw.init = &initd;
  176. pll->pll_ctrl = pll_ctrl;
  177. pll->pll_status = pll_status;
  178. pll->lockbit = lock_index;
  179. pll->lock = lock;
  180. spin_lock_irqsave(pll->lock, flags);
  181. reg = readl(pll->pll_ctrl);
  182. reg &= ~PLLCTRL_BPQUAL_MASK;
  183. writel(reg, pll->pll_ctrl);
  184. spin_unlock_irqrestore(pll->lock, flags);
  185. clk = clk_register(NULL, &pll->hw);
  186. if (WARN_ON(IS_ERR(clk)))
  187. goto free_pll;
  188. return clk;
  189. free_pll:
  190. kfree(pll);
  191. return clk;
  192. }