clkc.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Zynq clock controller
  4. *
  5. * Copyright (C) 2012 - 2013 Xilinx
  6. *
  7. * Sören Brinkmann <soren.brinkmann@xilinx.com>
  8. */
  9. #include <linux/clk/zynq.h>
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <linux/string.h>
  16. #include <linux/io.h>
  17. static void __iomem *zynq_clkc_base;
  18. #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
  19. #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
  20. #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
  21. #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
  22. #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
  23. #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
  24. #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
  25. #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
  26. #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
  27. #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
  28. #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
  29. #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
  30. #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
  31. #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
  32. #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
  33. #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
  34. #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
  35. #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
  36. #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
  37. #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
  38. #define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
  39. #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
  40. #define NUM_MIO_PINS 54
  41. #define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
  42. #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
  43. enum zynq_clk {
  44. armpll, ddrpll, iopll,
  45. cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
  46. ddr2x, ddr3x, dci,
  47. lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
  48. sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
  49. usb0_aper, usb1_aper, gem0_aper, gem1_aper,
  50. sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
  51. i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
  52. smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
  53. static struct clk *ps_clk;
  54. static struct clk *clks[clk_max];
  55. static struct clk_onecell_data clk_data;
  56. static DEFINE_SPINLOCK(armpll_lock);
  57. static DEFINE_SPINLOCK(ddrpll_lock);
  58. static DEFINE_SPINLOCK(iopll_lock);
  59. static DEFINE_SPINLOCK(armclk_lock);
  60. static DEFINE_SPINLOCK(swdtclk_lock);
  61. static DEFINE_SPINLOCK(ddrclk_lock);
  62. static DEFINE_SPINLOCK(dciclk_lock);
  63. static DEFINE_SPINLOCK(gem0clk_lock);
  64. static DEFINE_SPINLOCK(gem1clk_lock);
  65. static DEFINE_SPINLOCK(canclk_lock);
  66. static DEFINE_SPINLOCK(canmioclk_lock);
  67. static DEFINE_SPINLOCK(dbgclk_lock);
  68. static DEFINE_SPINLOCK(aperclk_lock);
  69. static const char *const armpll_parents[] __initconst = {"armpll_int",
  70. "ps_clk"};
  71. static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
  72. "ps_clk"};
  73. static const char *const iopll_parents[] __initconst = {"iopll_int",
  74. "ps_clk"};
  75. static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
  76. static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
  77. static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
  78. "can0_mio_mux"};
  79. static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
  80. "can1_mio_mux"};
  81. static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
  82. "dummy_name"};
  83. static const char *const dbgtrc_emio_input_names[] __initconst = {
  84. "trace_emio_clk"};
  85. static const char *const gem0_emio_input_names[] __initconst = {
  86. "gem0_emio_clk"};
  87. static const char *const gem1_emio_input_names[] __initconst = {
  88. "gem1_emio_clk"};
  89. static const char *const swdt_ext_clk_input_names[] __initconst = {
  90. "swdt_ext_clk"};
  91. static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
  92. const char *clk_name, void __iomem *fclk_ctrl_reg,
  93. const char **parents, int enable)
  94. {
  95. struct clk *clk;
  96. u32 enable_reg;
  97. char *mux_name;
  98. char *div0_name;
  99. char *div1_name;
  100. spinlock_t *fclk_lock;
  101. spinlock_t *fclk_gate_lock;
  102. void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
  103. fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
  104. if (!fclk_lock)
  105. goto err;
  106. fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
  107. if (!fclk_gate_lock)
  108. goto err_fclk_gate_lock;
  109. spin_lock_init(fclk_lock);
  110. spin_lock_init(fclk_gate_lock);
  111. mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
  112. if (!mux_name)
  113. goto err_mux_name;
  114. div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
  115. if (!div0_name)
  116. goto err_div0_name;
  117. div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
  118. if (!div1_name)
  119. goto err_div1_name;
  120. clk = clk_register_mux(NULL, mux_name, parents, 4,
  121. CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
  122. fclk_lock);
  123. clk = clk_register_divider(NULL, div0_name, mux_name,
  124. 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
  125. CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
  126. clk = clk_register_divider(NULL, div1_name, div0_name,
  127. CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
  128. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  129. fclk_lock);
  130. clks[fclk] = clk_register_gate(NULL, clk_name,
  131. div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
  132. 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
  133. enable_reg = readl(fclk_gate_reg) & 1;
  134. if (enable && !enable_reg) {
  135. if (clk_prepare_enable(clks[fclk]))
  136. pr_warn("%s: FCLK%u enable failed\n", __func__,
  137. fclk - fclk0);
  138. }
  139. kfree(mux_name);
  140. kfree(div0_name);
  141. kfree(div1_name);
  142. return;
  143. err_div1_name:
  144. kfree(div0_name);
  145. err_div0_name:
  146. kfree(mux_name);
  147. err_mux_name:
  148. kfree(fclk_gate_lock);
  149. err_fclk_gate_lock:
  150. kfree(fclk_lock);
  151. err:
  152. clks[fclk] = ERR_PTR(-ENOMEM);
  153. }
  154. static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
  155. enum zynq_clk clk1, const char *clk_name0,
  156. const char *clk_name1, void __iomem *clk_ctrl,
  157. const char **parents, unsigned int two_gates)
  158. {
  159. struct clk *clk;
  160. char *mux_name;
  161. char *div_name;
  162. spinlock_t *lock;
  163. lock = kmalloc(sizeof(*lock), GFP_KERNEL);
  164. if (!lock)
  165. goto err;
  166. spin_lock_init(lock);
  167. mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
  168. div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
  169. clk = clk_register_mux(NULL, mux_name, parents, 4,
  170. CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
  171. clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
  172. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
  173. clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
  174. CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
  175. if (two_gates)
  176. clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
  177. CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
  178. kfree(mux_name);
  179. kfree(div_name);
  180. return;
  181. err:
  182. clks[clk0] = ERR_PTR(-ENOMEM);
  183. if (two_gates)
  184. clks[clk1] = ERR_PTR(-ENOMEM);
  185. }
  186. static void __init zynq_clk_setup(struct device_node *np)
  187. {
  188. int i;
  189. u32 tmp;
  190. int ret;
  191. struct clk *clk;
  192. char *clk_name;
  193. unsigned int fclk_enable = 0;
  194. const char *clk_output_name[clk_max];
  195. const char *cpu_parents[4];
  196. const char *periph_parents[4];
  197. const char *swdt_ext_clk_mux_parents[2];
  198. const char *can_mio_mux_parents[NUM_MIO_PINS];
  199. const char *dummy_nm = "dummy_name";
  200. pr_info("Zynq clock init\n");
  201. /* get clock output names from DT */
  202. for (i = 0; i < clk_max; i++) {
  203. if (of_property_read_string_index(np, "clock-output-names",
  204. i, &clk_output_name[i])) {
  205. pr_err("%s: clock output name not in DT\n", __func__);
  206. BUG();
  207. }
  208. }
  209. cpu_parents[0] = clk_output_name[armpll];
  210. cpu_parents[1] = clk_output_name[armpll];
  211. cpu_parents[2] = clk_output_name[ddrpll];
  212. cpu_parents[3] = clk_output_name[iopll];
  213. periph_parents[0] = clk_output_name[iopll];
  214. periph_parents[1] = clk_output_name[iopll];
  215. periph_parents[2] = clk_output_name[armpll];
  216. periph_parents[3] = clk_output_name[ddrpll];
  217. of_property_read_u32(np, "fclk-enable", &fclk_enable);
  218. /* ps_clk */
  219. ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
  220. if (ret) {
  221. pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
  222. tmp = 33333333;
  223. }
  224. ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
  225. /* PLLs */
  226. clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
  227. SLCR_PLL_STATUS, 0, &armpll_lock);
  228. clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
  229. armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
  230. SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
  231. clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
  232. SLCR_PLL_STATUS, 1, &ddrpll_lock);
  233. clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
  234. ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
  235. SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
  236. clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
  237. SLCR_PLL_STATUS, 2, &iopll_lock);
  238. clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
  239. iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
  240. SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
  241. /* CPU clocks */
  242. tmp = readl(SLCR_621_TRUE) & 1;
  243. clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
  244. CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
  245. &armclk_lock);
  246. clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
  247. SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  248. CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
  249. clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
  250. "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
  251. SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
  252. clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
  253. 1, 2);
  254. clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
  255. "cpu_3or2x_div", CLK_IGNORE_UNUSED,
  256. SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
  257. clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
  258. 2 + tmp);
  259. clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
  260. "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
  261. 26, 0, &armclk_lock);
  262. clk_prepare_enable(clks[cpu_2x]);
  263. clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
  264. 4 + 2 * tmp);
  265. clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
  266. "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
  267. 0, &armclk_lock);
  268. /* Timers */
  269. swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
  270. for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
  271. int idx = of_property_match_string(np, "clock-names",
  272. swdt_ext_clk_input_names[i]);
  273. if (idx >= 0)
  274. swdt_ext_clk_mux_parents[i + 1] =
  275. of_clk_get_parent_name(np, idx);
  276. else
  277. swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
  278. }
  279. clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
  280. swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
  281. CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
  282. &swdtclk_lock);
  283. /* DDR clocks */
  284. clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
  285. SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
  286. CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
  287. clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
  288. "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
  289. clk_prepare_enable(clks[ddr2x]);
  290. clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
  291. SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
  292. CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
  293. clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
  294. "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
  295. clk_prepare_enable(clks[ddr3x]);
  296. clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
  297. SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  298. CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
  299. clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
  300. CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
  301. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  302. &dciclk_lock);
  303. clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
  304. CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
  305. &dciclk_lock);
  306. clk_prepare_enable(clks[dci]);
  307. /* Peripheral clocks */
  308. for (i = fclk0; i <= fclk3; i++) {
  309. int enable = !!(fclk_enable & BIT(i - fclk0));
  310. zynq_clk_register_fclk(i, clk_output_name[i],
  311. SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
  312. periph_parents, enable);
  313. }
  314. zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
  315. SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
  316. zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
  317. SLCR_SMC_CLK_CTRL, periph_parents, 0);
  318. zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
  319. SLCR_PCAP_CLK_CTRL, periph_parents, 0);
  320. zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
  321. clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
  322. periph_parents, 1);
  323. zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
  324. clk_output_name[uart1], SLCR_UART_CLK_CTRL,
  325. periph_parents, 1);
  326. zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
  327. clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
  328. periph_parents, 1);
  329. for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
  330. int idx = of_property_match_string(np, "clock-names",
  331. gem0_emio_input_names[i]);
  332. if (idx >= 0)
  333. gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
  334. idx);
  335. }
  336. clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
  337. CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
  338. &gem0clk_lock);
  339. clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
  340. SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  341. CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
  342. clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
  343. CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
  344. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  345. &gem0clk_lock);
  346. clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
  347. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  348. SLCR_GEM0_CLK_CTRL, 6, 1, 0,
  349. &gem0clk_lock);
  350. clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
  351. "gem0_emio_mux", CLK_SET_RATE_PARENT,
  352. SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
  353. for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
  354. int idx = of_property_match_string(np, "clock-names",
  355. gem1_emio_input_names[i]);
  356. if (idx >= 0)
  357. gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
  358. idx);
  359. }
  360. clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
  361. CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
  362. &gem1clk_lock);
  363. clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
  364. SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  365. CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
  366. clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
  367. CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
  368. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  369. &gem1clk_lock);
  370. clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
  371. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  372. SLCR_GEM1_CLK_CTRL, 6, 1, 0,
  373. &gem1clk_lock);
  374. clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
  375. "gem1_emio_mux", CLK_SET_RATE_PARENT,
  376. SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
  377. tmp = strlen("mio_clk_00x");
  378. clk_name = kmalloc(tmp, GFP_KERNEL);
  379. for (i = 0; i < NUM_MIO_PINS; i++) {
  380. int idx;
  381. snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
  382. idx = of_property_match_string(np, "clock-names", clk_name);
  383. if (idx >= 0)
  384. can_mio_mux_parents[i] = of_clk_get_parent_name(np,
  385. idx);
  386. else
  387. can_mio_mux_parents[i] = dummy_nm;
  388. }
  389. kfree(clk_name);
  390. clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
  391. CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
  392. &canclk_lock);
  393. clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
  394. SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  395. CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
  396. clk = clk_register_divider(NULL, "can_div1", "can_div0",
  397. CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
  398. CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  399. &canclk_lock);
  400. clk = clk_register_gate(NULL, "can0_gate", "can_div1",
  401. CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
  402. &canclk_lock);
  403. clk = clk_register_gate(NULL, "can1_gate", "can_div1",
  404. CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
  405. &canclk_lock);
  406. clk = clk_register_mux(NULL, "can0_mio_mux",
  407. can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
  408. CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
  409. &canmioclk_lock);
  410. clk = clk_register_mux(NULL, "can1_mio_mux",
  411. can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
  412. CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
  413. 0, &canmioclk_lock);
  414. clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
  415. can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
  416. CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
  417. &canmioclk_lock);
  418. clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
  419. can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
  420. CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
  421. 0, &canmioclk_lock);
  422. for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
  423. int idx = of_property_match_string(np, "clock-names",
  424. dbgtrc_emio_input_names[i]);
  425. if (idx >= 0)
  426. dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
  427. idx);
  428. }
  429. clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
  430. CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
  431. &dbgclk_lock);
  432. clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
  433. SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
  434. CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
  435. clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
  436. CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
  437. &dbgclk_lock);
  438. clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
  439. "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
  440. 0, 0, &dbgclk_lock);
  441. clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
  442. clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
  443. &dbgclk_lock);
  444. /* leave debug clocks in the state the bootloader set them up to */
  445. tmp = readl(SLCR_DBG_CLK_CTRL);
  446. if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
  447. if (clk_prepare_enable(clks[dbg_trc]))
  448. pr_warn("%s: trace clk enable failed\n", __func__);
  449. if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
  450. if (clk_prepare_enable(clks[dbg_apb]))
  451. pr_warn("%s: debug APB clk enable failed\n", __func__);
  452. /* One gated clock for all APER clocks. */
  453. clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
  454. clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
  455. &aperclk_lock);
  456. clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
  457. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
  458. &aperclk_lock);
  459. clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
  460. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
  461. &aperclk_lock);
  462. clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
  463. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
  464. &aperclk_lock);
  465. clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
  466. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
  467. &aperclk_lock);
  468. clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
  469. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
  470. &aperclk_lock);
  471. clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
  472. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
  473. &aperclk_lock);
  474. clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
  475. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
  476. &aperclk_lock);
  477. clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
  478. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
  479. &aperclk_lock);
  480. clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
  481. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
  482. &aperclk_lock);
  483. clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
  484. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
  485. &aperclk_lock);
  486. clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
  487. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
  488. &aperclk_lock);
  489. clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
  490. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
  491. &aperclk_lock);
  492. clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
  493. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
  494. &aperclk_lock);
  495. clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
  496. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
  497. &aperclk_lock);
  498. clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
  499. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
  500. &aperclk_lock);
  501. clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
  502. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
  503. &aperclk_lock);
  504. clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
  505. clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
  506. &aperclk_lock);
  507. for (i = 0; i < ARRAY_SIZE(clks); i++) {
  508. if (IS_ERR(clks[i])) {
  509. pr_err("Zynq clk %d: register failed with %ld\n",
  510. i, PTR_ERR(clks[i]));
  511. BUG();
  512. }
  513. }
  514. clk_data.clks = clks;
  515. clk_data.clk_num = ARRAY_SIZE(clks);
  516. of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  517. }
  518. CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
  519. void __init zynq_clock_init(void)
  520. {
  521. struct device_node *np;
  522. struct device_node *slcr;
  523. struct resource res;
  524. np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
  525. if (!np) {
  526. pr_err("%s: clkc node not found\n", __func__);
  527. goto np_err;
  528. }
  529. if (of_address_to_resource(np, 0, &res)) {
  530. pr_err("%pOFn: failed to get resource\n", np);
  531. goto np_err;
  532. }
  533. slcr = of_get_parent(np);
  534. if (slcr->data) {
  535. zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
  536. } else {
  537. pr_err("%pOFn: Unable to get I/O memory\n", np);
  538. of_node_put(slcr);
  539. goto np_err;
  540. }
  541. pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
  542. of_node_put(slcr);
  543. of_node_put(np);
  544. return;
  545. np_err:
  546. of_node_put(np);
  547. BUG();
  548. }