clk-cgu.h 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright(c) 2020 Intel Corporation.
  4. * Zhu YiXin <yixin.zhu@intel.com>
  5. * Rahul Tanwar <rahul.tanwar@intel.com>
  6. */
  7. #ifndef __CLK_CGU_H
  8. #define __CLK_CGU_H
  9. #include <linux/io.h>
  10. struct lgm_clk_mux {
  11. struct clk_hw hw;
  12. void __iomem *membase;
  13. unsigned int reg;
  14. u8 shift;
  15. u8 width;
  16. unsigned long flags;
  17. spinlock_t lock;
  18. };
  19. struct lgm_clk_divider {
  20. struct clk_hw hw;
  21. void __iomem *membase;
  22. unsigned int reg;
  23. u8 shift;
  24. u8 width;
  25. u8 shift_gate;
  26. u8 width_gate;
  27. unsigned long flags;
  28. const struct clk_div_table *table;
  29. spinlock_t lock;
  30. };
  31. struct lgm_clk_ddiv {
  32. struct clk_hw hw;
  33. void __iomem *membase;
  34. unsigned int reg;
  35. u8 shift0;
  36. u8 width0;
  37. u8 shift1;
  38. u8 width1;
  39. u8 shift2;
  40. u8 width2;
  41. u8 shift_gate;
  42. u8 width_gate;
  43. unsigned int mult;
  44. unsigned int div;
  45. unsigned long flags;
  46. spinlock_t lock;
  47. };
  48. struct lgm_clk_gate {
  49. struct clk_hw hw;
  50. void __iomem *membase;
  51. unsigned int reg;
  52. u8 shift;
  53. unsigned long flags;
  54. spinlock_t lock;
  55. };
  56. enum lgm_clk_type {
  57. CLK_TYPE_FIXED,
  58. CLK_TYPE_MUX,
  59. CLK_TYPE_DIVIDER,
  60. CLK_TYPE_FIXED_FACTOR,
  61. CLK_TYPE_GATE,
  62. CLK_TYPE_NONE,
  63. };
  64. /**
  65. * struct lgm_clk_provider
  66. * @membase: IO mem base address for CGU.
  67. * @np: device node
  68. * @dev: device
  69. * @clk_data: array of hw clocks and clk number.
  70. */
  71. struct lgm_clk_provider {
  72. void __iomem *membase;
  73. struct device_node *np;
  74. struct device *dev;
  75. struct clk_hw_onecell_data clk_data;
  76. spinlock_t lock;
  77. };
  78. enum pll_type {
  79. TYPE_ROPLL,
  80. TYPE_LJPLL,
  81. TYPE_NONE,
  82. };
  83. struct lgm_clk_pll {
  84. struct clk_hw hw;
  85. void __iomem *membase;
  86. unsigned int reg;
  87. unsigned long flags;
  88. enum pll_type type;
  89. spinlock_t lock;
  90. };
  91. /**
  92. * struct lgm_pll_clk_data
  93. * @id: platform specific id of the clock.
  94. * @name: name of this pll clock.
  95. * @parent_data: parent clock data.
  96. * @num_parents: number of parents.
  97. * @flags: optional flags for basic clock.
  98. * @type: platform type of pll.
  99. * @reg: offset of the register.
  100. */
  101. struct lgm_pll_clk_data {
  102. unsigned int id;
  103. const char *name;
  104. const struct clk_parent_data *parent_data;
  105. u8 num_parents;
  106. unsigned long flags;
  107. enum pll_type type;
  108. int reg;
  109. };
  110. #define LGM_PLL(_id, _name, _pdata, _flags, \
  111. _reg, _type) \
  112. { \
  113. .id = _id, \
  114. .name = _name, \
  115. .parent_data = _pdata, \
  116. .num_parents = ARRAY_SIZE(_pdata), \
  117. .flags = _flags, \
  118. .reg = _reg, \
  119. .type = _type, \
  120. }
  121. struct lgm_clk_ddiv_data {
  122. unsigned int id;
  123. const char *name;
  124. const struct clk_parent_data *parent_data;
  125. u8 flags;
  126. unsigned long div_flags;
  127. unsigned int reg;
  128. u8 shift0;
  129. u8 width0;
  130. u8 shift1;
  131. u8 width1;
  132. u8 shift_gate;
  133. u8 width_gate;
  134. u8 ex_shift;
  135. u8 ex_width;
  136. };
  137. #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
  138. _shft0, _wdth0, _shft1, _wdth1, \
  139. _shft_gate, _wdth_gate, _xshft, _df) \
  140. { \
  141. .id = _id, \
  142. .name = _name, \
  143. .parent_data = &(const struct clk_parent_data){ \
  144. .fw_name = _pname, \
  145. .name = _pname, \
  146. }, \
  147. .flags = _flags, \
  148. .reg = _reg, \
  149. .shift0 = _shft0, \
  150. .width0 = _wdth0, \
  151. .shift1 = _shft1, \
  152. .width1 = _wdth1, \
  153. .shift_gate = _shft_gate, \
  154. .width_gate = _wdth_gate, \
  155. .ex_shift = _xshft, \
  156. .ex_width = 1, \
  157. .div_flags = _df, \
  158. }
  159. struct lgm_clk_branch {
  160. unsigned int id;
  161. enum lgm_clk_type type;
  162. const char *name;
  163. const struct clk_parent_data *parent_data;
  164. u8 num_parents;
  165. unsigned long flags;
  166. unsigned int mux_off;
  167. u8 mux_shift;
  168. u8 mux_width;
  169. unsigned long mux_flags;
  170. unsigned int mux_val;
  171. unsigned int div_off;
  172. u8 div_shift;
  173. u8 div_width;
  174. u8 div_shift_gate;
  175. u8 div_width_gate;
  176. unsigned long div_flags;
  177. unsigned int div_val;
  178. const struct clk_div_table *div_table;
  179. unsigned int gate_off;
  180. u8 gate_shift;
  181. unsigned long gate_flags;
  182. unsigned int gate_val;
  183. unsigned int mult;
  184. unsigned int div;
  185. };
  186. /* clock flags definition */
  187. #define CLOCK_FLAG_VAL_INIT BIT(16)
  188. #define MUX_CLK_SW BIT(17)
  189. #define LGM_MUX(_id, _name, _pdata, _f, _reg, \
  190. _shift, _width, _cf, _v) \
  191. { \
  192. .id = _id, \
  193. .type = CLK_TYPE_MUX, \
  194. .name = _name, \
  195. .parent_data = _pdata, \
  196. .num_parents = ARRAY_SIZE(_pdata), \
  197. .flags = _f, \
  198. .mux_off = _reg, \
  199. .mux_shift = _shift, \
  200. .mux_width = _width, \
  201. .mux_flags = _cf, \
  202. .mux_val = _v, \
  203. }
  204. #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
  205. _shift_gate, _width_gate, _cf, _v, _dtable) \
  206. { \
  207. .id = _id, \
  208. .type = CLK_TYPE_DIVIDER, \
  209. .name = _name, \
  210. .parent_data = &(const struct clk_parent_data){ \
  211. .fw_name = _pname, \
  212. .name = _pname, \
  213. }, \
  214. .num_parents = 1, \
  215. .flags = _f, \
  216. .div_off = _reg, \
  217. .div_shift = _shift, \
  218. .div_width = _width, \
  219. .div_shift_gate = _shift_gate, \
  220. .div_width_gate = _width_gate, \
  221. .div_flags = _cf, \
  222. .div_val = _v, \
  223. .div_table = _dtable, \
  224. }
  225. #define LGM_GATE(_id, _name, _pname, _f, _reg, \
  226. _shift, _cf, _v) \
  227. { \
  228. .id = _id, \
  229. .type = CLK_TYPE_GATE, \
  230. .name = _name, \
  231. .parent_data = &(const struct clk_parent_data){ \
  232. .fw_name = _pname, \
  233. .name = _pname, \
  234. }, \
  235. .num_parents = !_pname ? 0 : 1, \
  236. .flags = _f, \
  237. .gate_off = _reg, \
  238. .gate_shift = _shift, \
  239. .gate_flags = _cf, \
  240. .gate_val = _v, \
  241. }
  242. #define LGM_FIXED(_id, _name, _pname, _f, _reg, \
  243. _shift, _width, _cf, _freq, _v) \
  244. { \
  245. .id = _id, \
  246. .type = CLK_TYPE_FIXED, \
  247. .name = _name, \
  248. .parent_data = &(const struct clk_parent_data){ \
  249. .fw_name = _pname, \
  250. .name = _pname, \
  251. }, \
  252. .num_parents = !_pname ? 0 : 1, \
  253. .flags = _f, \
  254. .div_off = _reg, \
  255. .div_shift = _shift, \
  256. .div_width = _width, \
  257. .div_flags = _cf, \
  258. .div_val = _v, \
  259. .mux_flags = _freq, \
  260. }
  261. #define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
  262. _shift, _width, _cf, _v, _m, _d) \
  263. { \
  264. .id = _id, \
  265. .type = CLK_TYPE_FIXED_FACTOR, \
  266. .name = _name, \
  267. .parent_data = &(const struct clk_parent_data){ \
  268. .fw_name = _pname, \
  269. .name = _pname, \
  270. }, \
  271. .num_parents = 1, \
  272. .flags = _f, \
  273. .div_off = _reg, \
  274. .div_shift = _shift, \
  275. .div_width = _width, \
  276. .div_flags = _cf, \
  277. .div_val = _v, \
  278. .mult = _m, \
  279. .div = _d, \
  280. }
  281. static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
  282. u8 shift, u8 width, u32 set_val)
  283. {
  284. u32 mask = (GENMASK(width - 1, 0) << shift);
  285. u32 regval;
  286. regval = readl(membase + reg);
  287. regval = (regval & ~mask) | ((set_val << shift) & mask);
  288. writel(regval, membase + reg);
  289. }
  290. static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
  291. u8 shift, u8 width)
  292. {
  293. u32 mask = (GENMASK(width - 1, 0) << shift);
  294. u32 val;
  295. val = readl(membase + reg);
  296. val = (val & mask) >> shift;
  297. return val;
  298. }
  299. int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
  300. const struct lgm_clk_branch *list,
  301. unsigned int nr_clk);
  302. int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
  303. const struct lgm_pll_clk_data *list,
  304. unsigned int nr_clk);
  305. int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
  306. const struct lgm_clk_ddiv_data *list,
  307. unsigned int nr_clk);
  308. #endif /* __CLK_CGU_H */