clk-icst.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the ICST307 VCO clock found in the ARM Reference designs.
  4. * We wrap the custom interface from <asm/hardware/icst.h> into the generic
  5. * clock framework.
  6. *
  7. * Copyright (C) 2012-2015 Linus Walleij
  8. *
  9. * TODO: when all ARM reference designs are migrated to generic clocks, the
  10. * ICST clock code from the ARM tree should probably be merged into this
  11. * file.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/export.h>
  16. #include <linux/err.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/io.h>
  19. #include <linux/regmap.h>
  20. #include <linux/mfd/syscon.h>
  21. #include "icst.h"
  22. #include "clk-icst.h"
  23. /* Magic unlocking token used on all Versatile boards */
  24. #define VERSATILE_LOCK_VAL 0xA05F
  25. #define VERSATILE_AUX_OSC_BITS 0x7FFFF
  26. #define INTEGRATOR_AP_CM_BITS 0xFF
  27. #define INTEGRATOR_AP_SYS_BITS 0xFF
  28. #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
  29. #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
  30. #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
  31. /**
  32. * struct clk_icst - ICST VCO clock wrapper
  33. * @hw: corresponding clock hardware entry
  34. * @vcoreg: VCO register address
  35. * @lockreg: VCO lock register address
  36. * @params: parameters for this ICST instance
  37. * @rate: current rate
  38. * @ctype: the type of control register for the ICST
  39. */
  40. struct clk_icst {
  41. struct clk_hw hw;
  42. struct regmap *map;
  43. u32 vcoreg_off;
  44. u32 lockreg_off;
  45. struct icst_params *params;
  46. unsigned long rate;
  47. enum icst_control_type ctype;
  48. };
  49. #define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
  50. /**
  51. * vco_get() - get ICST VCO settings from a certain ICST
  52. * @icst: the ICST clock to get
  53. * @vco: the VCO struct to return the value in
  54. */
  55. static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
  56. {
  57. u32 val;
  58. int ret;
  59. ret = regmap_read(icst->map, icst->vcoreg_off, &val);
  60. if (ret)
  61. return ret;
  62. /*
  63. * The Integrator/AP core clock can only access the low eight
  64. * bits of the v PLL divider. Bit 8 is tied low and always zero,
  65. * r is hardwired to 22 and output divider s is hardwired to 1
  66. * (divide by 2) according to the document
  67. * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
  68. * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
  69. */
  70. if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
  71. vco->v = val & INTEGRATOR_AP_CM_BITS;
  72. vco->r = 22;
  73. vco->s = 1;
  74. return 0;
  75. }
  76. /*
  77. * The Integrator/AP system clock on the base board can only
  78. * access the low eight bits of the v PLL divider. Bit 8 is tied low
  79. * and always zero, r is hardwired to 46, and the output divider is
  80. * hardwired to 3 (divide by 4) according to the document
  81. * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
  82. * page 3-16.
  83. */
  84. if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
  85. vco->v = val & INTEGRATOR_AP_SYS_BITS;
  86. vco->r = 46;
  87. vco->s = 3;
  88. return 0;
  89. }
  90. /*
  91. * The Integrator/AP PCI clock is using an odd pattern to create
  92. * the child clock, basically a single bit called DIVX/Y is used
  93. * to select between two different hardwired values: setting the
  94. * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
  95. * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
  96. * 33 or 25 MHz respectively.
  97. */
  98. if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
  99. bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
  100. vco->v = divxy ? 17 : 14;
  101. vco->r = divxy ? 22 : 14;
  102. vco->s = 1;
  103. return 0;
  104. }
  105. /*
  106. * The Integrator/CP core clock can access the low eight bits
  107. * of the v PLL divider. Bit 8 is tied low and always zero,
  108. * r is hardwired to 22 and the output divider s is accessible
  109. * in bits 8 thru 10 according to the document
  110. * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
  111. * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
  112. */
  113. if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
  114. vco->v = val & 0xFF;
  115. vco->r = 22;
  116. vco->s = (val >> 8) & 7;
  117. return 0;
  118. }
  119. if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
  120. vco->v = (val >> 12) & 0xFF;
  121. vco->r = 22;
  122. vco->s = (val >> 20) & 7;
  123. return 0;
  124. }
  125. vco->v = val & 0x1ff;
  126. vco->r = (val >> 9) & 0x7f;
  127. vco->s = (val >> 16) & 03;
  128. return 0;
  129. }
  130. /**
  131. * vco_set() - commit changes to an ICST VCO
  132. * @icst: the ICST clock to set
  133. * @vco: the VCO struct to set the changes from
  134. */
  135. static int vco_set(struct clk_icst *icst, struct icst_vco vco)
  136. {
  137. u32 mask;
  138. u32 val;
  139. int ret;
  140. /* Mask the bits used by the VCO */
  141. switch (icst->ctype) {
  142. case ICST_INTEGRATOR_AP_CM:
  143. mask = INTEGRATOR_AP_CM_BITS;
  144. val = vco.v & 0xFF;
  145. if (vco.v & 0x100)
  146. pr_err("ICST error: tried to set bit 8 of VDW\n");
  147. if (vco.s != 1)
  148. pr_err("ICST error: tried to use VOD != 1\n");
  149. if (vco.r != 22)
  150. pr_err("ICST error: tried to use RDW != 22\n");
  151. break;
  152. case ICST_INTEGRATOR_AP_SYS:
  153. mask = INTEGRATOR_AP_SYS_BITS;
  154. val = vco.v & 0xFF;
  155. if (vco.v & 0x100)
  156. pr_err("ICST error: tried to set bit 8 of VDW\n");
  157. if (vco.s != 3)
  158. pr_err("ICST error: tried to use VOD != 1\n");
  159. if (vco.r != 46)
  160. pr_err("ICST error: tried to use RDW != 22\n");
  161. break;
  162. case ICST_INTEGRATOR_CP_CM_CORE:
  163. mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
  164. val = (vco.v & 0xFF) | vco.s << 8;
  165. if (vco.v & 0x100)
  166. pr_err("ICST error: tried to set bit 8 of VDW\n");
  167. if (vco.r != 22)
  168. pr_err("ICST error: tried to use RDW != 22\n");
  169. break;
  170. case ICST_INTEGRATOR_CP_CM_MEM:
  171. mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
  172. val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
  173. if (vco.v & 0x100)
  174. pr_err("ICST error: tried to set bit 8 of VDW\n");
  175. if (vco.r != 22)
  176. pr_err("ICST error: tried to use RDW != 22\n");
  177. break;
  178. default:
  179. /* Regular auxilary oscillator */
  180. mask = VERSATILE_AUX_OSC_BITS;
  181. val = vco.v | (vco.r << 9) | (vco.s << 16);
  182. break;
  183. }
  184. pr_debug("ICST: new val = 0x%08x\n", val);
  185. /* This magic unlocks the VCO so it can be controlled */
  186. ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
  187. if (ret)
  188. return ret;
  189. ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
  190. if (ret)
  191. return ret;
  192. /* This locks the VCO again */
  193. ret = regmap_write(icst->map, icst->lockreg_off, 0);
  194. if (ret)
  195. return ret;
  196. return 0;
  197. }
  198. static unsigned long icst_recalc_rate(struct clk_hw *hw,
  199. unsigned long parent_rate)
  200. {
  201. struct clk_icst *icst = to_icst(hw);
  202. struct icst_vco vco;
  203. int ret;
  204. if (parent_rate)
  205. icst->params->ref = parent_rate;
  206. ret = vco_get(icst, &vco);
  207. if (ret) {
  208. pr_err("ICST: could not get VCO setting\n");
  209. return 0;
  210. }
  211. icst->rate = icst_hz(icst->params, vco);
  212. return icst->rate;
  213. }
  214. static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
  215. unsigned long *prate)
  216. {
  217. struct clk_icst *icst = to_icst(hw);
  218. struct icst_vco vco;
  219. if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
  220. icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
  221. if (rate <= 12000000)
  222. return 12000000;
  223. if (rate >= 160000000)
  224. return 160000000;
  225. /* Slam to closest megahertz */
  226. return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000;
  227. }
  228. if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
  229. if (rate <= 6000000)
  230. return 6000000;
  231. if (rate >= 66000000)
  232. return 66000000;
  233. /* Slam to closest 0.5 megahertz */
  234. return DIV_ROUND_CLOSEST(rate, 500000) * 500000;
  235. }
  236. if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
  237. /* Divides between 3 and 50 MHz in steps of 0.25 MHz */
  238. if (rate <= 3000000)
  239. return 3000000;
  240. if (rate >= 50000000)
  241. return 5000000;
  242. /* Slam to closest 0.25 MHz */
  243. return DIV_ROUND_CLOSEST(rate, 250000) * 250000;
  244. }
  245. if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
  246. /*
  247. * If we're below or less than halfway from 25 to 33 MHz
  248. * select 25 MHz
  249. */
  250. if (rate <= 25000000 || rate < 29000000)
  251. return 25000000;
  252. /* Else just return the default frequency */
  253. return 33000000;
  254. }
  255. vco = icst_hz_to_vco(icst->params, rate);
  256. return icst_hz(icst->params, vco);
  257. }
  258. static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
  259. unsigned long parent_rate)
  260. {
  261. struct clk_icst *icst = to_icst(hw);
  262. struct icst_vco vco;
  263. if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
  264. /* This clock is especially primitive */
  265. unsigned int val;
  266. int ret;
  267. if (rate == 25000000) {
  268. val = 0;
  269. } else if (rate == 33000000) {
  270. val = INTEGRATOR_AP_PCI_25_33_MHZ;
  271. } else {
  272. pr_err("ICST: cannot set PCI frequency %lu\n",
  273. rate);
  274. return -EINVAL;
  275. }
  276. ret = regmap_write(icst->map, icst->lockreg_off,
  277. VERSATILE_LOCK_VAL);
  278. if (ret)
  279. return ret;
  280. ret = regmap_update_bits(icst->map, icst->vcoreg_off,
  281. INTEGRATOR_AP_PCI_25_33_MHZ,
  282. val);
  283. if (ret)
  284. return ret;
  285. /* This locks the VCO again */
  286. ret = regmap_write(icst->map, icst->lockreg_off, 0);
  287. if (ret)
  288. return ret;
  289. return 0;
  290. }
  291. if (parent_rate)
  292. icst->params->ref = parent_rate;
  293. vco = icst_hz_to_vco(icst->params, rate);
  294. icst->rate = icst_hz(icst->params, vco);
  295. return vco_set(icst, vco);
  296. }
  297. static const struct clk_ops icst_ops = {
  298. .recalc_rate = icst_recalc_rate,
  299. .round_rate = icst_round_rate,
  300. .set_rate = icst_set_rate,
  301. };
  302. struct clk *icst_clk_setup(struct device *dev,
  303. const struct clk_icst_desc *desc,
  304. const char *name,
  305. const char *parent_name,
  306. struct regmap *map,
  307. enum icst_control_type ctype)
  308. {
  309. struct clk *clk;
  310. struct clk_icst *icst;
  311. struct clk_init_data init;
  312. struct icst_params *pclone;
  313. icst = kzalloc(sizeof(*icst), GFP_KERNEL);
  314. if (!icst)
  315. return ERR_PTR(-ENOMEM);
  316. pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
  317. if (!pclone) {
  318. kfree(icst);
  319. return ERR_PTR(-ENOMEM);
  320. }
  321. init.name = name;
  322. init.ops = &icst_ops;
  323. init.flags = 0;
  324. init.parent_names = (parent_name ? &parent_name : NULL);
  325. init.num_parents = (parent_name ? 1 : 0);
  326. icst->map = map;
  327. icst->hw.init = &init;
  328. icst->params = pclone;
  329. icst->vcoreg_off = desc->vco_offset;
  330. icst->lockreg_off = desc->lock_offset;
  331. icst->ctype = ctype;
  332. clk = clk_register(dev, &icst->hw);
  333. if (IS_ERR(clk)) {
  334. kfree(pclone);
  335. kfree(icst);
  336. }
  337. return clk;
  338. }
  339. EXPORT_SYMBOL_GPL(icst_clk_setup);
  340. struct clk *icst_clk_register(struct device *dev,
  341. const struct clk_icst_desc *desc,
  342. const char *name,
  343. const char *parent_name,
  344. void __iomem *base)
  345. {
  346. struct regmap_config icst_regmap_conf = {
  347. .reg_bits = 32,
  348. .val_bits = 32,
  349. .reg_stride = 4,
  350. };
  351. struct regmap *map;
  352. map = regmap_init_mmio(dev, base, &icst_regmap_conf);
  353. if (IS_ERR(map)) {
  354. pr_err("could not initialize ICST regmap\n");
  355. return ERR_CAST(map);
  356. }
  357. return icst_clk_setup(dev, desc, name, parent_name, map,
  358. ICST_VERSATILE);
  359. }
  360. EXPORT_SYMBOL_GPL(icst_clk_register);
  361. #ifdef CONFIG_OF
  362. /*
  363. * In a device tree, an memory-mapped ICST clock appear as a child
  364. * of a syscon node. Assume this and probe it only as a child of a
  365. * syscon.
  366. */
  367. static const struct icst_params icst525_params = {
  368. .vco_max = ICST525_VCO_MAX_5V,
  369. .vco_min = ICST525_VCO_MIN,
  370. .vd_min = 8,
  371. .vd_max = 263,
  372. .rd_min = 3,
  373. .rd_max = 65,
  374. .s2div = icst525_s2div,
  375. .idx2s = icst525_idx2s,
  376. };
  377. static const struct icst_params icst307_params = {
  378. .vco_max = ICST307_VCO_MAX,
  379. .vco_min = ICST307_VCO_MIN,
  380. .vd_min = 4 + 8,
  381. .vd_max = 511 + 8,
  382. .rd_min = 1 + 2,
  383. .rd_max = 127 + 2,
  384. .s2div = icst307_s2div,
  385. .idx2s = icst307_idx2s,
  386. };
  387. /**
  388. * The core modules on the Integrator/AP and Integrator/CP have
  389. * especially crippled ICST525 control.
  390. */
  391. static const struct icst_params icst525_apcp_cm_params = {
  392. .vco_max = ICST525_VCO_MAX_5V,
  393. .vco_min = ICST525_VCO_MIN,
  394. /* Minimum 12 MHz, VDW = 4 */
  395. .vd_min = 12,
  396. /*
  397. * Maximum 160 MHz, VDW = 152 for all core modules, but
  398. * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
  399. * go to 200 MHz (max VDW = 192).
  400. */
  401. .vd_max = 192,
  402. /* r is hardcoded to 22 and this is the actual divisor, +2 */
  403. .rd_min = 24,
  404. .rd_max = 24,
  405. .s2div = icst525_s2div,
  406. .idx2s = icst525_idx2s,
  407. };
  408. static const struct icst_params icst525_ap_sys_params = {
  409. .vco_max = ICST525_VCO_MAX_5V,
  410. .vco_min = ICST525_VCO_MIN,
  411. /* Minimum 3 MHz, VDW = 4 */
  412. .vd_min = 3,
  413. /* Maximum 50 MHz, VDW = 192 */
  414. .vd_max = 50,
  415. /* r is hardcoded to 46 and this is the actual divisor, +2 */
  416. .rd_min = 48,
  417. .rd_max = 48,
  418. .s2div = icst525_s2div,
  419. .idx2s = icst525_idx2s,
  420. };
  421. static const struct icst_params icst525_ap_pci_params = {
  422. .vco_max = ICST525_VCO_MAX_5V,
  423. .vco_min = ICST525_VCO_MIN,
  424. /* Minimum 25 MHz */
  425. .vd_min = 25,
  426. /* Maximum 33 MHz */
  427. .vd_max = 33,
  428. /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
  429. .rd_min = 16,
  430. .rd_max = 24,
  431. .s2div = icst525_s2div,
  432. .idx2s = icst525_idx2s,
  433. };
  434. static void __init of_syscon_icst_setup(struct device_node *np)
  435. {
  436. struct device_node *parent;
  437. struct regmap *map;
  438. struct clk_icst_desc icst_desc;
  439. const char *name = np->name;
  440. const char *parent_name;
  441. struct clk *regclk;
  442. enum icst_control_type ctype;
  443. /* We do not release this reference, we are using it perpetually */
  444. parent = of_get_parent(np);
  445. if (!parent) {
  446. pr_err("no parent node for syscon ICST clock\n");
  447. return;
  448. }
  449. map = syscon_node_to_regmap(parent);
  450. if (IS_ERR(map)) {
  451. pr_err("no regmap for syscon ICST clock parent\n");
  452. return;
  453. }
  454. if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
  455. pr_err("no VCO register offset for ICST clock\n");
  456. return;
  457. }
  458. if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
  459. pr_err("no lock register offset for ICST clock\n");
  460. return;
  461. }
  462. if (of_device_is_compatible(np, "arm,syscon-icst525")) {
  463. icst_desc.params = &icst525_params;
  464. ctype = ICST_VERSATILE;
  465. } else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
  466. icst_desc.params = &icst307_params;
  467. ctype = ICST_VERSATILE;
  468. } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
  469. icst_desc.params = &icst525_apcp_cm_params;
  470. ctype = ICST_INTEGRATOR_AP_CM;
  471. } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
  472. icst_desc.params = &icst525_ap_sys_params;
  473. ctype = ICST_INTEGRATOR_AP_SYS;
  474. } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
  475. icst_desc.params = &icst525_ap_pci_params;
  476. ctype = ICST_INTEGRATOR_AP_PCI;
  477. } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
  478. icst_desc.params = &icst525_apcp_cm_params;
  479. ctype = ICST_INTEGRATOR_CP_CM_CORE;
  480. } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
  481. icst_desc.params = &icst525_apcp_cm_params;
  482. ctype = ICST_INTEGRATOR_CP_CM_MEM;
  483. } else {
  484. pr_err("unknown ICST clock %s\n", name);
  485. return;
  486. }
  487. /* Parent clock name is not the same as node parent */
  488. parent_name = of_clk_get_parent_name(np, 0);
  489. regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
  490. if (IS_ERR(regclk)) {
  491. pr_err("error setting up syscon ICST clock %s\n", name);
  492. return;
  493. }
  494. of_clk_add_provider(np, of_clk_src_simple_get, regclk);
  495. pr_debug("registered syscon ICST clock %s\n", name);
  496. }
  497. CLK_OF_DECLARE(arm_syscon_icst525_clk,
  498. "arm,syscon-icst525", of_syscon_icst_setup);
  499. CLK_OF_DECLARE(arm_syscon_icst307_clk,
  500. "arm,syscon-icst307", of_syscon_icst_setup);
  501. CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
  502. "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
  503. CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
  504. "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
  505. CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
  506. "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
  507. CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
  508. "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
  509. CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
  510. "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);
  511. #endif