u8500_of_clk.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Clock definitions for u8500 platform.
  4. *
  5. * Copyright (C) 2012 ST-Ericsson SA
  6. * Author: Ulf Hansson <ulf.hansson@linaro.org>
  7. */
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/mfd/dbx500-prcmu.h>
  12. #include "clk.h"
  13. #define PRCC_NUM_PERIPH_CLUSTERS 6
  14. #define PRCC_PERIPHS_PER_CLUSTER 32
  15. static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  16. static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  17. static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  18. #define PRCC_SHOW(clk, base, bit) \
  19. clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  20. #define PRCC_PCLK_STORE(clk, base, bit) \
  21. prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  22. #define PRCC_KCLK_STORE(clk, base, bit) \
  23. prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  24. static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
  25. void *data)
  26. {
  27. struct clk **clk_data = data;
  28. unsigned int base, bit;
  29. if (clkspec->args_count != 2)
  30. return ERR_PTR(-EINVAL);
  31. base = clkspec->args[0];
  32. bit = clkspec->args[1];
  33. if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  34. pr_err("%s: invalid PRCC base %d\n", __func__, base);
  35. return ERR_PTR(-EINVAL);
  36. }
  37. return PRCC_SHOW(clk_data, base, bit);
  38. }
  39. /* CLKRST4 is missing making it hard to index things */
  40. enum clkrst_index {
  41. CLKRST1_INDEX = 0,
  42. CLKRST2_INDEX,
  43. CLKRST3_INDEX,
  44. CLKRST5_INDEX,
  45. CLKRST6_INDEX,
  46. CLKRST_MAX,
  47. };
  48. static void u8500_clk_init(struct device_node *np)
  49. {
  50. struct prcmu_fw_version *fw_version;
  51. struct device_node *child = NULL;
  52. const char *sgaclk_parent = NULL;
  53. struct clk *clk, *rtc_clk, *twd_clk;
  54. u32 bases[CLKRST_MAX];
  55. int i;
  56. for (i = 0; i < ARRAY_SIZE(bases); i++) {
  57. struct resource r;
  58. if (of_address_to_resource(np, i, &r))
  59. /* Not much choice but to continue */
  60. pr_err("failed to get CLKRST %d base address\n",
  61. i + 1);
  62. bases[i] = r.start;
  63. }
  64. /* Clock sources */
  65. clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  66. CLK_IGNORE_UNUSED);
  67. prcmu_clk[PRCMU_PLLSOC0] = clk;
  68. clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  69. CLK_IGNORE_UNUSED);
  70. prcmu_clk[PRCMU_PLLSOC1] = clk;
  71. clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  72. CLK_IGNORE_UNUSED);
  73. prcmu_clk[PRCMU_PLLDDR] = clk;
  74. /* FIXME: Add sys, ulp and int clocks here. */
  75. rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  76. CLK_IGNORE_UNUSED,
  77. 32768);
  78. /* PRCMU clocks */
  79. fw_version = prcmu_get_fw_version();
  80. if (fw_version != NULL) {
  81. switch (fw_version->project) {
  82. case PRCMU_FW_PROJECT_U8500_C2:
  83. case PRCMU_FW_PROJECT_U8500_MBL:
  84. case PRCMU_FW_PROJECT_U8520:
  85. case PRCMU_FW_PROJECT_U8420:
  86. case PRCMU_FW_PROJECT_U8420_SYSCLK:
  87. sgaclk_parent = "soc0_pll";
  88. break;
  89. default:
  90. break;
  91. }
  92. }
  93. if (sgaclk_parent)
  94. clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
  95. PRCMU_SGACLK, 0);
  96. else
  97. clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
  98. prcmu_clk[PRCMU_SGACLK] = clk;
  99. clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
  100. prcmu_clk[PRCMU_UARTCLK] = clk;
  101. clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
  102. prcmu_clk[PRCMU_MSP02CLK] = clk;
  103. clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
  104. prcmu_clk[PRCMU_MSP1CLK] = clk;
  105. clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
  106. prcmu_clk[PRCMU_I2CCLK] = clk;
  107. clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
  108. prcmu_clk[PRCMU_SLIMCLK] = clk;
  109. clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
  110. prcmu_clk[PRCMU_PER1CLK] = clk;
  111. clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
  112. prcmu_clk[PRCMU_PER2CLK] = clk;
  113. clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
  114. prcmu_clk[PRCMU_PER3CLK] = clk;
  115. clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
  116. prcmu_clk[PRCMU_PER5CLK] = clk;
  117. clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
  118. prcmu_clk[PRCMU_PER6CLK] = clk;
  119. clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
  120. prcmu_clk[PRCMU_PER7CLK] = clk;
  121. clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
  122. CLK_SET_RATE_GATE);
  123. prcmu_clk[PRCMU_LCDCLK] = clk;
  124. clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
  125. prcmu_clk[PRCMU_BMLCLK] = clk;
  126. clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
  127. CLK_SET_RATE_GATE);
  128. prcmu_clk[PRCMU_HSITXCLK] = clk;
  129. clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
  130. CLK_SET_RATE_GATE);
  131. prcmu_clk[PRCMU_HSIRXCLK] = clk;
  132. clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
  133. CLK_SET_RATE_GATE);
  134. prcmu_clk[PRCMU_HDMICLK] = clk;
  135. clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
  136. prcmu_clk[PRCMU_APEATCLK] = clk;
  137. clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
  138. CLK_SET_RATE_GATE);
  139. prcmu_clk[PRCMU_APETRACECLK] = clk;
  140. clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
  141. prcmu_clk[PRCMU_MCDECLK] = clk;
  142. clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
  143. prcmu_clk[PRCMU_IPI2CCLK] = clk;
  144. clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
  145. prcmu_clk[PRCMU_DSIALTCLK] = clk;
  146. clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
  147. prcmu_clk[PRCMU_DMACLK] = clk;
  148. clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
  149. prcmu_clk[PRCMU_B2R2CLK] = clk;
  150. clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
  151. CLK_SET_RATE_GATE);
  152. prcmu_clk[PRCMU_TVCLK] = clk;
  153. clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
  154. prcmu_clk[PRCMU_SSPCLK] = clk;
  155. clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
  156. prcmu_clk[PRCMU_RNGCLK] = clk;
  157. clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
  158. prcmu_clk[PRCMU_UICCCLK] = clk;
  159. clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
  160. prcmu_clk[PRCMU_TIMCLK] = clk;
  161. clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
  162. prcmu_clk[PRCMU_SYSCLK] = clk;
  163. clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
  164. 100000000, CLK_SET_RATE_GATE);
  165. prcmu_clk[PRCMU_SDMMCCLK] = clk;
  166. clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
  167. PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
  168. prcmu_clk[PRCMU_PLLDSI] = clk;
  169. clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
  170. PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
  171. prcmu_clk[PRCMU_DSI0CLK] = clk;
  172. clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
  173. PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
  174. prcmu_clk[PRCMU_DSI1CLK] = clk;
  175. clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
  176. PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
  177. prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
  178. clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
  179. PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
  180. prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
  181. clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
  182. PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
  183. prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
  184. clk = clk_reg_prcmu_scalable_rate("armss", NULL,
  185. PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
  186. prcmu_clk[PRCMU_ARMSS] = clk;
  187. twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
  188. CLK_IGNORE_UNUSED, 1, 2);
  189. /*
  190. * FIXME: Add special handled PRCMU clocks here:
  191. * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
  192. * 2. ab9540_clkout1yuv, see clkout0yuv
  193. */
  194. /* PRCC P-clocks */
  195. clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
  196. BIT(0), 0);
  197. PRCC_PCLK_STORE(clk, 1, 0);
  198. clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
  199. BIT(1), 0);
  200. PRCC_PCLK_STORE(clk, 1, 1);
  201. clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
  202. BIT(2), 0);
  203. PRCC_PCLK_STORE(clk, 1, 2);
  204. clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
  205. BIT(3), 0);
  206. PRCC_PCLK_STORE(clk, 1, 3);
  207. clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
  208. BIT(4), 0);
  209. PRCC_PCLK_STORE(clk, 1, 4);
  210. clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
  211. BIT(5), 0);
  212. PRCC_PCLK_STORE(clk, 1, 5);
  213. clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
  214. BIT(6), 0);
  215. PRCC_PCLK_STORE(clk, 1, 6);
  216. clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
  217. BIT(7), 0);
  218. PRCC_PCLK_STORE(clk, 1, 7);
  219. clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
  220. BIT(8), 0);
  221. PRCC_PCLK_STORE(clk, 1, 8);
  222. clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
  223. BIT(9), 0);
  224. PRCC_PCLK_STORE(clk, 1, 9);
  225. clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
  226. BIT(10), 0);
  227. PRCC_PCLK_STORE(clk, 1, 10);
  228. clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
  229. BIT(11), 0);
  230. PRCC_PCLK_STORE(clk, 1, 11);
  231. clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
  232. BIT(0), 0);
  233. PRCC_PCLK_STORE(clk, 2, 0);
  234. clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
  235. BIT(1), 0);
  236. PRCC_PCLK_STORE(clk, 2, 1);
  237. clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
  238. BIT(2), 0);
  239. PRCC_PCLK_STORE(clk, 2, 2);
  240. clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
  241. BIT(3), 0);
  242. PRCC_PCLK_STORE(clk, 2, 3);
  243. clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
  244. BIT(4), 0);
  245. PRCC_PCLK_STORE(clk, 2, 4);
  246. clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
  247. BIT(5), 0);
  248. PRCC_PCLK_STORE(clk, 2, 5);
  249. clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
  250. BIT(6), 0);
  251. PRCC_PCLK_STORE(clk, 2, 6);
  252. clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
  253. BIT(7), 0);
  254. PRCC_PCLK_STORE(clk, 2, 7);
  255. clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
  256. BIT(8), 0);
  257. PRCC_PCLK_STORE(clk, 2, 8);
  258. clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
  259. BIT(9), 0);
  260. PRCC_PCLK_STORE(clk, 2, 9);
  261. clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
  262. BIT(10), 0);
  263. PRCC_PCLK_STORE(clk, 2, 10);
  264. clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
  265. BIT(11), 0);
  266. PRCC_PCLK_STORE(clk, 2, 11);
  267. clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
  268. BIT(12), 0);
  269. PRCC_PCLK_STORE(clk, 2, 12);
  270. clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
  271. BIT(0), 0);
  272. PRCC_PCLK_STORE(clk, 3, 0);
  273. clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
  274. BIT(1), 0);
  275. PRCC_PCLK_STORE(clk, 3, 1);
  276. clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
  277. BIT(2), 0);
  278. PRCC_PCLK_STORE(clk, 3, 2);
  279. clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
  280. BIT(3), 0);
  281. PRCC_PCLK_STORE(clk, 3, 3);
  282. clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
  283. BIT(4), 0);
  284. PRCC_PCLK_STORE(clk, 3, 4);
  285. clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
  286. BIT(5), 0);
  287. PRCC_PCLK_STORE(clk, 3, 5);
  288. clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
  289. BIT(6), 0);
  290. PRCC_PCLK_STORE(clk, 3, 6);
  291. clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
  292. BIT(7), 0);
  293. PRCC_PCLK_STORE(clk, 3, 7);
  294. clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
  295. BIT(8), 0);
  296. PRCC_PCLK_STORE(clk, 3, 8);
  297. clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
  298. BIT(0), 0);
  299. PRCC_PCLK_STORE(clk, 5, 0);
  300. clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
  301. BIT(1), 0);
  302. PRCC_PCLK_STORE(clk, 5, 1);
  303. clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
  304. BIT(0), 0);
  305. PRCC_PCLK_STORE(clk, 6, 0);
  306. clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
  307. BIT(1), 0);
  308. PRCC_PCLK_STORE(clk, 6, 1);
  309. clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
  310. BIT(2), 0);
  311. PRCC_PCLK_STORE(clk, 6, 2);
  312. clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
  313. BIT(3), 0);
  314. PRCC_PCLK_STORE(clk, 6, 3);
  315. clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
  316. BIT(4), 0);
  317. PRCC_PCLK_STORE(clk, 6, 4);
  318. clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
  319. BIT(5), 0);
  320. PRCC_PCLK_STORE(clk, 6, 5);
  321. clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
  322. BIT(6), 0);
  323. PRCC_PCLK_STORE(clk, 6, 6);
  324. clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
  325. BIT(7), 0);
  326. PRCC_PCLK_STORE(clk, 6, 7);
  327. /* PRCC K-clocks
  328. *
  329. * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
  330. * by enabling just the K-clock, even if it is not a valid parent to
  331. * the K-clock. Until drivers get fixed we might need some kind of
  332. * "parent muxed join".
  333. */
  334. /* Periph1 */
  335. clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
  336. bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
  337. PRCC_KCLK_STORE(clk, 1, 0);
  338. clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
  339. bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
  340. PRCC_KCLK_STORE(clk, 1, 1);
  341. clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
  342. bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
  343. PRCC_KCLK_STORE(clk, 1, 2);
  344. clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
  345. bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
  346. PRCC_KCLK_STORE(clk, 1, 3);
  347. clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
  348. bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
  349. PRCC_KCLK_STORE(clk, 1, 4);
  350. clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
  351. bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
  352. PRCC_KCLK_STORE(clk, 1, 5);
  353. clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
  354. bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
  355. PRCC_KCLK_STORE(clk, 1, 6);
  356. clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
  357. bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
  358. PRCC_KCLK_STORE(clk, 1, 8);
  359. clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
  360. bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
  361. PRCC_KCLK_STORE(clk, 1, 9);
  362. clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
  363. bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
  364. PRCC_KCLK_STORE(clk, 1, 10);
  365. /* Periph2 */
  366. clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
  367. bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
  368. PRCC_KCLK_STORE(clk, 2, 0);
  369. clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
  370. bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
  371. PRCC_KCLK_STORE(clk, 2, 2);
  372. clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
  373. bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
  374. PRCC_KCLK_STORE(clk, 2, 3);
  375. clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
  376. bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
  377. PRCC_KCLK_STORE(clk, 2, 4);
  378. clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
  379. bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
  380. PRCC_KCLK_STORE(clk, 2, 5);
  381. /* Note that rate is received from parent. */
  382. clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
  383. bases[CLKRST2_INDEX], BIT(6),
  384. CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
  385. PRCC_KCLK_STORE(clk, 2, 6);
  386. clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
  387. bases[CLKRST2_INDEX], BIT(7),
  388. CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
  389. PRCC_KCLK_STORE(clk, 2, 7);
  390. /* Periph3 */
  391. clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
  392. bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
  393. PRCC_KCLK_STORE(clk, 3, 1);
  394. clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
  395. bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
  396. PRCC_KCLK_STORE(clk, 3, 2);
  397. clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
  398. bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
  399. PRCC_KCLK_STORE(clk, 3, 3);
  400. clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
  401. bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
  402. PRCC_KCLK_STORE(clk, 3, 4);
  403. clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
  404. bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
  405. PRCC_KCLK_STORE(clk, 3, 5);
  406. clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
  407. bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
  408. PRCC_KCLK_STORE(clk, 3, 6);
  409. clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
  410. bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
  411. PRCC_KCLK_STORE(clk, 3, 7);
  412. /* Periph6 */
  413. clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
  414. bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
  415. PRCC_KCLK_STORE(clk, 6, 0);
  416. for_each_child_of_node(np, child) {
  417. static struct clk_onecell_data clk_data;
  418. if (of_node_name_eq(child, "prcmu-clock")) {
  419. clk_data.clks = prcmu_clk;
  420. clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
  421. of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
  422. }
  423. if (of_node_name_eq(child, "prcc-periph-clock"))
  424. of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
  425. if (of_node_name_eq(child, "prcc-kernel-clock"))
  426. of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
  427. if (of_node_name_eq(child, "rtc32k-clock"))
  428. of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
  429. if (of_node_name_eq(child, "smp-twd-clock"))
  430. of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
  431. }
  432. }
  433. CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);