abx500-clk.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * abx500 clock implementation for ux500 platform.
  4. *
  5. * Copyright (C) 2012 ST-Ericsson SA
  6. * Author: Ulf Hansson <ulf.hansson@linaro.org>
  7. */
  8. #include <linux/err.h>
  9. #include <linux/module.h>
  10. #include <linux/device.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mfd/abx500/ab8500.h>
  14. #include <linux/mfd/abx500/ab8500-sysctrl.h>
  15. #include <linux/clkdev.h>
  16. #include <linux/clk-provider.h>
  17. #include <dt-bindings/clock/ste-ab8500.h>
  18. #include "clk.h"
  19. #define AB8500_NUM_CLKS 6
  20. static struct clk *ab8500_clks[AB8500_NUM_CLKS];
  21. static struct clk_onecell_data ab8500_clk_data;
  22. /* Clock definitions for ab8500 */
  23. static int ab8500_reg_clks(struct device *dev)
  24. {
  25. int ret;
  26. struct clk *clk;
  27. struct device_node *np = dev->of_node;
  28. const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
  29. u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
  30. u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
  31. u8 intclk_reg_bits[] = {
  32. 0 ,
  33. (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
  34. };
  35. /* Enable SWAT */
  36. ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
  37. if (ret)
  38. return ret;
  39. /* ab8500_sysclk2 */
  40. clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
  41. AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
  42. AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
  43. ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
  44. /* ab8500_sysclk3 */
  45. clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
  46. AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
  47. AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
  48. ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
  49. /* ab8500_sysclk4 */
  50. clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
  51. AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
  52. AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
  53. ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
  54. /* ab_ulpclk */
  55. clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
  56. AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
  57. AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
  58. 38400000, 9000, 0);
  59. ab8500_clks[AB8500_SYSCLK_ULP] = clk;
  60. /* ab8500_intclk */
  61. clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
  62. intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
  63. ab8500_clks[AB8500_SYSCLK_INT] = clk;
  64. /* ab8500_audioclk */
  65. clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
  66. AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
  67. AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
  68. ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
  69. ab8500_clk_data.clks = ab8500_clks;
  70. ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
  71. of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
  72. dev_info(dev, "registered clocks for ab850x\n");
  73. return 0;
  74. }
  75. static int abx500_clk_probe(struct platform_device *pdev)
  76. {
  77. struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
  78. int ret;
  79. if (is_ab8500(parent) || is_ab8505(parent)) {
  80. ret = ab8500_reg_clks(&pdev->dev);
  81. } else {
  82. dev_err(&pdev->dev, "non supported plf id\n");
  83. return -ENODEV;
  84. }
  85. return ret;
  86. }
  87. static const struct of_device_id abx500_clk_match[] = {
  88. { .compatible = "stericsson,ab8500-clk", },
  89. {}
  90. };
  91. static struct platform_driver abx500_clk_driver = {
  92. .driver = {
  93. .name = "abx500-clk",
  94. .of_match_table = abx500_clk_match,
  95. },
  96. .probe = abx500_clk_probe,
  97. };
  98. static int __init abx500_clk_init(void)
  99. {
  100. return platform_driver_register(&abx500_clk_driver);
  101. }
  102. arch_initcall(abx500_clk_init);
  103. MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
  104. MODULE_DESCRIPTION("ABX500 clk driver");
  105. MODULE_LICENSE("GPL v2");