dpll3xxx.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP3/4 - specific DPLL control functions
  4. *
  5. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  6. * Copyright (C) 2009-2010 Nokia Corporation
  7. *
  8. * Written by Paul Walmsley
  9. * Testing and integration fixes by Jouni Högander
  10. *
  11. * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
  12. * Menon
  13. *
  14. * Parts of this code are based on code written by
  15. * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/list.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/bitops.h>
  25. #include <linux/clkdev.h>
  26. #include <linux/clk/ti.h>
  27. #include "clock.h"
  28. /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
  29. #define DPLL_AUTOIDLE_DISABLE 0x0
  30. #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
  31. #define MAX_DPLL_WAIT_TRIES 1000000
  32. #define OMAP3XXX_EN_DPLL_LOCKED 0x7
  33. /* Forward declarations */
  34. static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
  35. static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
  36. static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
  37. /* Private functions */
  38. /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
  39. static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
  40. {
  41. const struct dpll_data *dd;
  42. u32 v;
  43. dd = clk->dpll_data;
  44. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  45. v &= ~dd->enable_mask;
  46. v |= clken_bits << __ffs(dd->enable_mask);
  47. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  48. }
  49. /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
  50. static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
  51. {
  52. const struct dpll_data *dd;
  53. int i = 0;
  54. int ret = -EINVAL;
  55. const char *clk_name;
  56. dd = clk->dpll_data;
  57. clk_name = clk_hw_get_name(&clk->hw);
  58. state <<= __ffs(dd->idlest_mask);
  59. while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
  60. != state) && i < MAX_DPLL_WAIT_TRIES) {
  61. i++;
  62. udelay(1);
  63. }
  64. if (i == MAX_DPLL_WAIT_TRIES) {
  65. pr_err("clock: %s failed transition to '%s'\n",
  66. clk_name, (state) ? "locked" : "bypassed");
  67. } else {
  68. pr_debug("clock: %s transition to '%s' in %d loops\n",
  69. clk_name, (state) ? "locked" : "bypassed", i);
  70. ret = 0;
  71. }
  72. return ret;
  73. }
  74. /* From 3430 TRM ES2 4.7.6.2 */
  75. static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
  76. {
  77. unsigned long fint;
  78. u16 f = 0;
  79. fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
  80. pr_debug("clock: fint is %lu\n", fint);
  81. if (fint >= 750000 && fint <= 1000000)
  82. f = 0x3;
  83. else if (fint > 1000000 && fint <= 1250000)
  84. f = 0x4;
  85. else if (fint > 1250000 && fint <= 1500000)
  86. f = 0x5;
  87. else if (fint > 1500000 && fint <= 1750000)
  88. f = 0x6;
  89. else if (fint > 1750000 && fint <= 2100000)
  90. f = 0x7;
  91. else if (fint > 7500000 && fint <= 10000000)
  92. f = 0xB;
  93. else if (fint > 10000000 && fint <= 12500000)
  94. f = 0xC;
  95. else if (fint > 12500000 && fint <= 15000000)
  96. f = 0xD;
  97. else if (fint > 15000000 && fint <= 17500000)
  98. f = 0xE;
  99. else if (fint > 17500000 && fint <= 21000000)
  100. f = 0xF;
  101. else
  102. pr_debug("clock: unknown freqsel setting for %d\n", n);
  103. return f;
  104. }
  105. /*
  106. * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
  107. * @clk: pointer to a DPLL struct clk
  108. *
  109. * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
  110. * readiness before returning. Will save and restore the DPLL's
  111. * autoidle state across the enable, per the CDP code. If the DPLL
  112. * locked successfully, return 0; if the DPLL did not lock in the time
  113. * allotted, or DPLL3 was passed in, return -EINVAL.
  114. */
  115. static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
  116. {
  117. const struct dpll_data *dd;
  118. u8 ai;
  119. u8 state = 1;
  120. int r = 0;
  121. pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
  122. dd = clk->dpll_data;
  123. state <<= __ffs(dd->idlest_mask);
  124. /* Check if already locked */
  125. if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
  126. state)
  127. goto done;
  128. ai = omap3_dpll_autoidle_read(clk);
  129. if (ai)
  130. omap3_dpll_deny_idle(clk);
  131. _omap3_dpll_write_clken(clk, DPLL_LOCKED);
  132. r = _omap3_wait_dpll_status(clk, 1);
  133. if (ai)
  134. omap3_dpll_allow_idle(clk);
  135. done:
  136. return r;
  137. }
  138. /*
  139. * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
  140. * @clk: pointer to a DPLL struct clk
  141. *
  142. * Instructs a non-CORE DPLL to enter low-power bypass mode. In
  143. * bypass mode, the DPLL's rate is set equal to its parent clock's
  144. * rate. Waits for the DPLL to report readiness before returning.
  145. * Will save and restore the DPLL's autoidle state across the enable,
  146. * per the CDP code. If the DPLL entered bypass mode successfully,
  147. * return 0; if the DPLL did not enter bypass in the time allotted, or
  148. * DPLL3 was passed in, or the DPLL does not support low-power bypass,
  149. * return -EINVAL.
  150. */
  151. static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
  152. {
  153. int r;
  154. u8 ai;
  155. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
  156. return -EINVAL;
  157. pr_debug("clock: configuring DPLL %s for low-power bypass\n",
  158. clk_hw_get_name(&clk->hw));
  159. ai = omap3_dpll_autoidle_read(clk);
  160. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
  161. r = _omap3_wait_dpll_status(clk, 0);
  162. if (ai)
  163. omap3_dpll_allow_idle(clk);
  164. return r;
  165. }
  166. /*
  167. * _omap3_noncore_dpll_stop - instruct a DPLL to stop
  168. * @clk: pointer to a DPLL struct clk
  169. *
  170. * Instructs a non-CORE DPLL to enter low-power stop. Will save and
  171. * restore the DPLL's autoidle state across the stop, per the CDP
  172. * code. If DPLL3 was passed in, or the DPLL does not support
  173. * low-power stop, return -EINVAL; otherwise, return 0.
  174. */
  175. static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
  176. {
  177. u8 ai;
  178. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
  179. return -EINVAL;
  180. pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
  181. ai = omap3_dpll_autoidle_read(clk);
  182. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
  183. if (ai)
  184. omap3_dpll_allow_idle(clk);
  185. return 0;
  186. }
  187. /**
  188. * _lookup_dco - Lookup DCO used by j-type DPLL
  189. * @clk: pointer to a DPLL struct clk
  190. * @dco: digital control oscillator selector
  191. * @m: DPLL multiplier to set
  192. * @n: DPLL divider to set
  193. *
  194. * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
  195. *
  196. * XXX This code is not needed for 3430/AM35xx; can it be optimized
  197. * out in non-multi-OMAP builds for those chips?
  198. */
  199. static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
  200. {
  201. unsigned long fint, clkinp; /* watch out for overflow */
  202. clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
  203. fint = (clkinp / n) * m;
  204. if (fint < 1000000000)
  205. *dco = 2;
  206. else
  207. *dco = 4;
  208. }
  209. /**
  210. * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
  211. * @clk: pointer to a DPLL struct clk
  212. * @sd_div: target sigma-delta divider
  213. * @m: DPLL multiplier to set
  214. * @n: DPLL divider to set
  215. *
  216. * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
  217. *
  218. * XXX This code is not needed for 3430/AM35xx; can it be optimized
  219. * out in non-multi-OMAP builds for those chips?
  220. */
  221. static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
  222. {
  223. unsigned long clkinp, sd; /* watch out for overflow */
  224. int mod1, mod2;
  225. clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
  226. /*
  227. * target sigma-delta to near 250MHz
  228. * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
  229. */
  230. clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
  231. mod1 = (clkinp * m) % (250 * n);
  232. sd = (clkinp * m) / (250 * n);
  233. mod2 = sd % 10;
  234. sd /= 10;
  235. if (mod1 || mod2)
  236. sd++;
  237. *sd_div = sd;
  238. }
  239. /*
  240. * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
  241. * @clk: struct clk * of DPLL to set
  242. * @freqsel: FREQSEL value to set
  243. *
  244. * Program the DPLL with the last M, N values calculated, and wait for
  245. * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
  246. */
  247. static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
  248. {
  249. struct dpll_data *dd = clk->dpll_data;
  250. u8 dco, sd_div, ai = 0;
  251. u32 v;
  252. bool errata_i810;
  253. /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
  254. _omap3_noncore_dpll_bypass(clk);
  255. /*
  256. * Set jitter correction. Jitter correction applicable for OMAP343X
  257. * only since freqsel field is no longer present on other devices.
  258. */
  259. if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
  260. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  261. v &= ~dd->freqsel_mask;
  262. v |= freqsel << __ffs(dd->freqsel_mask);
  263. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  264. }
  265. /* Set DPLL multiplier, divider */
  266. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  267. /* Handle Duty Cycle Correction */
  268. if (dd->dcc_mask) {
  269. if (dd->last_rounded_rate >= dd->dcc_rate)
  270. v |= dd->dcc_mask; /* Enable DCC */
  271. else
  272. v &= ~dd->dcc_mask; /* Disable DCC */
  273. }
  274. v &= ~(dd->mult_mask | dd->div1_mask);
  275. v |= dd->last_rounded_m << __ffs(dd->mult_mask);
  276. v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
  277. /* Configure dco and sd_div for dplls that have these fields */
  278. if (dd->dco_mask) {
  279. _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
  280. v &= ~(dd->dco_mask);
  281. v |= dco << __ffs(dd->dco_mask);
  282. }
  283. if (dd->sddiv_mask) {
  284. _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
  285. dd->last_rounded_n);
  286. v &= ~(dd->sddiv_mask);
  287. v |= sd_div << __ffs(dd->sddiv_mask);
  288. }
  289. /*
  290. * Errata i810 - DPLL controller can get stuck while transitioning
  291. * to a power saving state. Software must ensure the DPLL can not
  292. * transition to a low power state while changing M/N values.
  293. * Easiest way to accomplish this is to prevent DPLL autoidle
  294. * before doing the M/N re-program.
  295. */
  296. errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
  297. if (errata_i810) {
  298. ai = omap3_dpll_autoidle_read(clk);
  299. if (ai) {
  300. omap3_dpll_deny_idle(clk);
  301. /* OCP barrier */
  302. omap3_dpll_autoidle_read(clk);
  303. }
  304. }
  305. ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
  306. /* Set 4X multiplier and low-power mode */
  307. if (dd->m4xen_mask || dd->lpmode_mask) {
  308. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  309. if (dd->m4xen_mask) {
  310. if (dd->last_rounded_m4xen)
  311. v |= dd->m4xen_mask;
  312. else
  313. v &= ~dd->m4xen_mask;
  314. }
  315. if (dd->lpmode_mask) {
  316. if (dd->last_rounded_lpmode)
  317. v |= dd->lpmode_mask;
  318. else
  319. v &= ~dd->lpmode_mask;
  320. }
  321. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  322. }
  323. /* We let the clock framework set the other output dividers later */
  324. /* REVISIT: Set ramp-up delay? */
  325. _omap3_noncore_dpll_lock(clk);
  326. if (errata_i810 && ai)
  327. omap3_dpll_allow_idle(clk);
  328. return 0;
  329. }
  330. /* Public functions */
  331. /**
  332. * omap3_dpll_recalc - recalculate DPLL rate
  333. * @clk: DPLL struct clk
  334. *
  335. * Recalculate and propagate the DPLL rate.
  336. */
  337. unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
  338. {
  339. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  340. return omap2_get_dpll_rate(clk);
  341. }
  342. /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
  343. /**
  344. * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
  345. * @clk: pointer to a DPLL struct clk
  346. *
  347. * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
  348. * The choice of modes depends on the DPLL's programmed rate: if it is
  349. * the same as the DPLL's parent clock, it will enter bypass;
  350. * otherwise, it will enter lock. This code will wait for the DPLL to
  351. * indicate readiness before returning, unless the DPLL takes too long
  352. * to enter the target state. Intended to be used as the struct clk's
  353. * enable function. If DPLL3 was passed in, or the DPLL does not
  354. * support low-power stop, or if the DPLL took too long to enter
  355. * bypass or lock, return -EINVAL; otherwise, return 0.
  356. */
  357. int omap3_noncore_dpll_enable(struct clk_hw *hw)
  358. {
  359. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  360. int r;
  361. struct dpll_data *dd;
  362. struct clk_hw *parent;
  363. dd = clk->dpll_data;
  364. if (!dd)
  365. return -EINVAL;
  366. if (clk->clkdm) {
  367. r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
  368. if (r) {
  369. WARN(1,
  370. "%s: could not enable %s's clockdomain %s: %d\n",
  371. __func__, clk_hw_get_name(hw),
  372. clk->clkdm_name, r);
  373. return r;
  374. }
  375. }
  376. parent = clk_hw_get_parent(hw);
  377. if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
  378. WARN_ON(parent != dd->clk_bypass);
  379. r = _omap3_noncore_dpll_bypass(clk);
  380. } else {
  381. WARN_ON(parent != dd->clk_ref);
  382. r = _omap3_noncore_dpll_lock(clk);
  383. }
  384. return r;
  385. }
  386. /**
  387. * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
  388. * @clk: pointer to a DPLL struct clk
  389. *
  390. * Instructs a non-CORE DPLL to enter low-power stop. This function is
  391. * intended for use in struct clkops. No return value.
  392. */
  393. void omap3_noncore_dpll_disable(struct clk_hw *hw)
  394. {
  395. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  396. _omap3_noncore_dpll_stop(clk);
  397. if (clk->clkdm)
  398. ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
  399. }
  400. /* Non-CORE DPLL rate set code */
  401. /**
  402. * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
  403. * @hw: pointer to the clock to determine rate for
  404. * @req: target rate request
  405. *
  406. * Determines which DPLL mode to use for reaching a desired target rate.
  407. * Checks whether the DPLL shall be in bypass or locked mode, and if
  408. * locked, calculates the M,N values for the DPLL via round-rate.
  409. * Returns a 0 on success, negative error value in failure.
  410. */
  411. int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
  412. struct clk_rate_request *req)
  413. {
  414. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  415. struct dpll_data *dd;
  416. if (!req->rate)
  417. return -EINVAL;
  418. dd = clk->dpll_data;
  419. if (!dd)
  420. return -EINVAL;
  421. if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
  422. (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
  423. req->best_parent_hw = dd->clk_bypass;
  424. } else {
  425. req->rate = omap2_dpll_round_rate(hw, req->rate,
  426. &req->best_parent_rate);
  427. req->best_parent_hw = dd->clk_ref;
  428. }
  429. req->best_parent_rate = req->rate;
  430. return 0;
  431. }
  432. /**
  433. * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
  434. * @hw: pointer to the clock to set parent for
  435. * @index: parent index to select
  436. *
  437. * Sets parent for a DPLL clock. This sets the DPLL into bypass or
  438. * locked mode. Returns 0 with success, negative error value otherwise.
  439. */
  440. int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
  441. {
  442. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  443. int ret;
  444. if (!hw)
  445. return -EINVAL;
  446. if (index)
  447. ret = _omap3_noncore_dpll_bypass(clk);
  448. else
  449. ret = _omap3_noncore_dpll_lock(clk);
  450. return ret;
  451. }
  452. /**
  453. * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
  454. * @hw: pointer to the clock to set parent for
  455. * @rate: target rate for the clock
  456. * @parent_rate: rate of the parent clock
  457. *
  458. * Sets rate for a DPLL clock. First checks if the clock parent is
  459. * reference clock (in bypass mode, the rate of the clock can't be
  460. * changed) and proceeds with the rate change operation. Returns 0
  461. * with success, negative error value otherwise.
  462. */
  463. int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
  464. unsigned long parent_rate)
  465. {
  466. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  467. struct dpll_data *dd;
  468. u16 freqsel = 0;
  469. int ret;
  470. if (!hw || !rate)
  471. return -EINVAL;
  472. dd = clk->dpll_data;
  473. if (!dd)
  474. return -EINVAL;
  475. if (clk_hw_get_parent(hw) != dd->clk_ref)
  476. return -EINVAL;
  477. if (dd->last_rounded_rate == 0)
  478. return -EINVAL;
  479. /* Freqsel is available only on OMAP343X devices */
  480. if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
  481. freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
  482. WARN_ON(!freqsel);
  483. }
  484. pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
  485. clk_hw_get_name(hw), rate);
  486. ret = omap3_noncore_dpll_program(clk, freqsel);
  487. return ret;
  488. }
  489. /**
  490. * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
  491. * @hw: pointer to the clock to set rate and parent for
  492. * @rate: target rate for the DPLL
  493. * @parent_rate: clock rate of the DPLL parent
  494. * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
  495. *
  496. * Sets rate and parent for a DPLL clock. If new parent is the bypass
  497. * clock, only selects the parent. Otherwise proceeds with a rate
  498. * change, as this will effectively also change the parent as the
  499. * DPLL is put into locked mode. Returns 0 with success, negative error
  500. * value otherwise.
  501. */
  502. int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
  503. unsigned long rate,
  504. unsigned long parent_rate,
  505. u8 index)
  506. {
  507. int ret;
  508. if (!hw || !rate)
  509. return -EINVAL;
  510. /*
  511. * clk-ref at index[0], in which case we only need to set rate,
  512. * the parent will be changed automatically with the lock sequence.
  513. * With clk-bypass case we only need to change parent.
  514. */
  515. if (index)
  516. ret = omap3_noncore_dpll_set_parent(hw, index);
  517. else
  518. ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  519. return ret;
  520. }
  521. /* DPLL autoidle read/set code */
  522. /**
  523. * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
  524. * @clk: struct clk * of the DPLL to read
  525. *
  526. * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
  527. * -EINVAL if passed a null pointer or if the struct clk does not
  528. * appear to refer to a DPLL.
  529. */
  530. static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
  531. {
  532. const struct dpll_data *dd;
  533. u32 v;
  534. if (!clk || !clk->dpll_data)
  535. return -EINVAL;
  536. dd = clk->dpll_data;
  537. if (!dd->autoidle_mask)
  538. return -EINVAL;
  539. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  540. v &= dd->autoidle_mask;
  541. v >>= __ffs(dd->autoidle_mask);
  542. return v;
  543. }
  544. /**
  545. * omap3_dpll_allow_idle - enable DPLL autoidle bits
  546. * @clk: struct clk * of the DPLL to operate on
  547. *
  548. * Enable DPLL automatic idle control. This automatic idle mode
  549. * switching takes effect only when the DPLL is locked, at least on
  550. * OMAP3430. The DPLL will enter low-power stop when its downstream
  551. * clocks are gated. No return value.
  552. */
  553. static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
  554. {
  555. const struct dpll_data *dd;
  556. u32 v;
  557. if (!clk || !clk->dpll_data)
  558. return;
  559. dd = clk->dpll_data;
  560. if (!dd->autoidle_mask)
  561. return;
  562. /*
  563. * REVISIT: CORE DPLL can optionally enter low-power bypass
  564. * by writing 0x5 instead of 0x1. Add some mechanism to
  565. * optionally enter this mode.
  566. */
  567. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  568. v &= ~dd->autoidle_mask;
  569. v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
  570. ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
  571. }
  572. /**
  573. * omap3_dpll_deny_idle - prevent DPLL from automatically idling
  574. * @clk: struct clk * of the DPLL to operate on
  575. *
  576. * Disable DPLL automatic idle control. No return value.
  577. */
  578. static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
  579. {
  580. const struct dpll_data *dd;
  581. u32 v;
  582. if (!clk || !clk->dpll_data)
  583. return;
  584. dd = clk->dpll_data;
  585. if (!dd->autoidle_mask)
  586. return;
  587. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  588. v &= ~dd->autoidle_mask;
  589. v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
  590. ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
  591. }
  592. /* Clock control for DPLL outputs */
  593. /* Find the parent DPLL for the given clkoutx2 clock */
  594. static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
  595. {
  596. struct clk_hw_omap *pclk = NULL;
  597. /* Walk up the parents of clk, looking for a DPLL */
  598. do {
  599. do {
  600. hw = clk_hw_get_parent(hw);
  601. } while (hw && (!omap2_clk_is_hw_omap(hw)));
  602. if (!hw)
  603. break;
  604. pclk = to_clk_hw_omap(hw);
  605. } while (pclk && !pclk->dpll_data);
  606. /* clk does not have a DPLL as a parent? error in the clock data */
  607. if (!pclk) {
  608. WARN_ON(1);
  609. return NULL;
  610. }
  611. return pclk;
  612. }
  613. /**
  614. * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
  615. * @clk: DPLL output struct clk
  616. *
  617. * Using parent clock DPLL data, look up DPLL state. If locked, set our
  618. * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  619. */
  620. unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
  621. unsigned long parent_rate)
  622. {
  623. const struct dpll_data *dd;
  624. unsigned long rate;
  625. u32 v;
  626. struct clk_hw_omap *pclk = NULL;
  627. if (!parent_rate)
  628. return 0;
  629. pclk = omap3_find_clkoutx2_dpll(hw);
  630. if (!pclk)
  631. return 0;
  632. dd = pclk->dpll_data;
  633. WARN_ON(!dd->enable_mask);
  634. v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
  635. v >>= __ffs(dd->enable_mask);
  636. if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
  637. rate = parent_rate;
  638. else
  639. rate = parent_rate * 2;
  640. return rate;
  641. }
  642. /**
  643. * omap3_core_dpll_save_context - Save the m and n values of the divider
  644. * @hw: pointer struct clk_hw
  645. *
  646. * Before the dpll registers are lost save the last rounded rate m and n
  647. * and the enable mask.
  648. */
  649. int omap3_core_dpll_save_context(struct clk_hw *hw)
  650. {
  651. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  652. struct dpll_data *dd;
  653. u32 v;
  654. dd = clk->dpll_data;
  655. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  656. clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
  657. if (clk->context == DPLL_LOCKED) {
  658. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  659. dd->last_rounded_m = (v & dd->mult_mask) >>
  660. __ffs(dd->mult_mask);
  661. dd->last_rounded_n = ((v & dd->div1_mask) >>
  662. __ffs(dd->div1_mask)) + 1;
  663. }
  664. return 0;
  665. }
  666. /**
  667. * omap3_core_dpll_restore_context - restore the m and n values of the divider
  668. * @hw: pointer struct clk_hw
  669. *
  670. * Restore the last rounded rate m and n
  671. * and the enable mask.
  672. */
  673. void omap3_core_dpll_restore_context(struct clk_hw *hw)
  674. {
  675. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  676. const struct dpll_data *dd;
  677. u32 v;
  678. dd = clk->dpll_data;
  679. if (clk->context == DPLL_LOCKED) {
  680. _omap3_dpll_write_clken(clk, 0x4);
  681. _omap3_wait_dpll_status(clk, 0);
  682. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  683. v &= ~(dd->mult_mask | dd->div1_mask);
  684. v |= dd->last_rounded_m << __ffs(dd->mult_mask);
  685. v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
  686. ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
  687. _omap3_dpll_write_clken(clk, DPLL_LOCKED);
  688. _omap3_wait_dpll_status(clk, 1);
  689. } else {
  690. _omap3_dpll_write_clken(clk, clk->context);
  691. }
  692. }
  693. /**
  694. * omap3_non_core_dpll_save_context - Save the m and n values of the divider
  695. * @hw: pointer struct clk_hw
  696. *
  697. * Before the dpll registers are lost save the last rounded rate m and n
  698. * and the enable mask.
  699. */
  700. int omap3_noncore_dpll_save_context(struct clk_hw *hw)
  701. {
  702. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  703. struct dpll_data *dd;
  704. u32 v;
  705. dd = clk->dpll_data;
  706. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  707. clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
  708. if (clk->context == DPLL_LOCKED) {
  709. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  710. dd->last_rounded_m = (v & dd->mult_mask) >>
  711. __ffs(dd->mult_mask);
  712. dd->last_rounded_n = ((v & dd->div1_mask) >>
  713. __ffs(dd->div1_mask)) + 1;
  714. }
  715. return 0;
  716. }
  717. /**
  718. * omap3_core_dpll_restore_context - restore the m and n values of the divider
  719. * @hw: pointer struct clk_hw
  720. *
  721. * Restore the last rounded rate m and n
  722. * and the enable mask.
  723. */
  724. void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
  725. {
  726. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  727. const struct dpll_data *dd;
  728. u32 ctrl, mult_div1;
  729. dd = clk->dpll_data;
  730. ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  731. mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  732. if (clk->context == ((ctrl & dd->enable_mask) >>
  733. __ffs(dd->enable_mask)) &&
  734. dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
  735. __ffs(dd->mult_mask)) &&
  736. dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
  737. __ffs(dd->div1_mask)) + 1) {
  738. /* nothing to be done */
  739. return;
  740. }
  741. if (clk->context == DPLL_LOCKED)
  742. omap3_noncore_dpll_program(clk, 0);
  743. else
  744. _omap3_dpll_write_clken(clk, clk->context);
  745. }
  746. /* OMAP3/4 non-CORE DPLL clkops */
  747. const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
  748. .allow_idle = omap3_dpll_allow_idle,
  749. .deny_idle = omap3_dpll_deny_idle,
  750. };
  751. /**
  752. * omap3_dpll4_set_rate - set rate for omap3 per-dpll
  753. * @hw: clock to change
  754. * @rate: target rate for clock
  755. * @parent_rate: rate of the parent clock
  756. *
  757. * Check if the current SoC supports the per-dpll reprogram operation
  758. * or not, and then do the rate change if supported. Returns -EINVAL
  759. * if not supported, 0 for success, and potential error codes from the
  760. * clock rate change.
  761. */
  762. int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
  763. unsigned long parent_rate)
  764. {
  765. /*
  766. * According to the 12-5 CDP code from TI, "Limitation 2.5"
  767. * on 3430ES1 prevents us from changing DPLL multipliers or dividers
  768. * on DPLL4.
  769. */
  770. if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
  771. pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
  772. return -EINVAL;
  773. }
  774. return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  775. }
  776. /**
  777. * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
  778. * @hw: clock to change
  779. * @rate: target rate for clock
  780. * @parent_rate: rate of the parent clock
  781. * @index: parent index, 0 - reference clock, 1 - bypass clock
  782. *
  783. * Check if the current SoC support the per-dpll reprogram operation
  784. * or not, and then do the rate + parent change if supported. Returns
  785. * -EINVAL if not supported, 0 for success, and potential error codes
  786. * from the clock rate change.
  787. */
  788. int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
  789. unsigned long parent_rate, u8 index)
  790. {
  791. if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
  792. pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
  793. return -EINVAL;
  794. }
  795. return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
  796. index);
  797. }
  798. /* Apply DM3730 errata sprz319 advisory 2.1. */
  799. static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
  800. unsigned long parent_rate)
  801. {
  802. struct omap3_dpll5_settings {
  803. unsigned int rate, m, n;
  804. };
  805. static const struct omap3_dpll5_settings precomputed[] = {
  806. /*
  807. * From DM3730 errata advisory 2.1, table 35 and 36.
  808. * The N value is increased by 1 compared to the tables as the
  809. * errata lists register values while last_rounded_field is the
  810. * real divider value.
  811. */
  812. { 12000000, 80, 0 + 1 },
  813. { 13000000, 443, 5 + 1 },
  814. { 19200000, 50, 0 + 1 },
  815. { 26000000, 443, 11 + 1 },
  816. { 38400000, 25, 0 + 1 }
  817. };
  818. const struct omap3_dpll5_settings *d;
  819. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  820. struct dpll_data *dd;
  821. unsigned int i;
  822. for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
  823. if (parent_rate == precomputed[i].rate)
  824. break;
  825. }
  826. if (i == ARRAY_SIZE(precomputed))
  827. return false;
  828. d = &precomputed[i];
  829. /* Update the M, N and rounded rate values and program the DPLL. */
  830. dd = clk->dpll_data;
  831. dd->last_rounded_m = d->m;
  832. dd->last_rounded_n = d->n;
  833. dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
  834. omap3_noncore_dpll_program(clk, 0);
  835. return true;
  836. }
  837. /**
  838. * omap3_dpll5_set_rate - set rate for omap3 dpll5
  839. * @hw: clock to change
  840. * @rate: target rate for clock
  841. * @parent_rate: rate of the parent clock
  842. *
  843. * Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
  844. * the DPLL is used for USB host (detected through the requested rate).
  845. */
  846. int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
  847. unsigned long parent_rate)
  848. {
  849. if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
  850. if (omap3_dpll5_apply_errata(hw, parent_rate))
  851. return 0;
  852. }
  853. return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  854. }