divider.c 13 KB

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  1. /*
  2. * TI Divider Clock
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/clk/ti.h>
  23. #include "clock.h"
  24. #undef pr_fmt
  25. #define pr_fmt(fmt) "%s: " fmt, __func__
  26. static unsigned int _get_table_div(const struct clk_div_table *table,
  27. unsigned int val)
  28. {
  29. const struct clk_div_table *clkt;
  30. for (clkt = table; clkt->div; clkt++)
  31. if (clkt->val == val)
  32. return clkt->div;
  33. return 0;
  34. }
  35. static void _setup_mask(struct clk_omap_divider *divider)
  36. {
  37. u16 mask;
  38. u32 max_val;
  39. const struct clk_div_table *clkt;
  40. if (divider->table) {
  41. max_val = 0;
  42. for (clkt = divider->table; clkt->div; clkt++)
  43. if (clkt->val > max_val)
  44. max_val = clkt->val;
  45. } else {
  46. max_val = divider->max;
  47. if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
  48. !(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
  49. max_val--;
  50. }
  51. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  52. mask = fls(max_val) - 1;
  53. else
  54. mask = max_val;
  55. divider->mask = (1 << fls(mask)) - 1;
  56. }
  57. static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
  58. {
  59. if (divider->flags & CLK_DIVIDER_ONE_BASED)
  60. return val;
  61. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  62. return 1 << val;
  63. if (divider->table)
  64. return _get_table_div(divider->table, val);
  65. return val + 1;
  66. }
  67. static unsigned int _get_table_val(const struct clk_div_table *table,
  68. unsigned int div)
  69. {
  70. const struct clk_div_table *clkt;
  71. for (clkt = table; clkt->div; clkt++)
  72. if (clkt->div == div)
  73. return clkt->val;
  74. return 0;
  75. }
  76. static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
  77. {
  78. if (divider->flags & CLK_DIVIDER_ONE_BASED)
  79. return div;
  80. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  81. return __ffs(div);
  82. if (divider->table)
  83. return _get_table_val(divider->table, div);
  84. return div - 1;
  85. }
  86. static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
  87. unsigned long parent_rate)
  88. {
  89. struct clk_omap_divider *divider = to_clk_omap_divider(hw);
  90. unsigned int div, val;
  91. val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
  92. val &= divider->mask;
  93. div = _get_div(divider, val);
  94. if (!div) {
  95. WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
  96. "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  97. clk_hw_get_name(hw));
  98. return parent_rate;
  99. }
  100. return DIV_ROUND_UP(parent_rate, div);
  101. }
  102. /*
  103. * The reverse of DIV_ROUND_UP: The maximum number which
  104. * divided by m is r
  105. */
  106. #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
  107. static bool _is_valid_table_div(const struct clk_div_table *table,
  108. unsigned int div)
  109. {
  110. const struct clk_div_table *clkt;
  111. for (clkt = table; clkt->div; clkt++)
  112. if (clkt->div == div)
  113. return true;
  114. return false;
  115. }
  116. static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
  117. {
  118. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  119. return is_power_of_2(div);
  120. if (divider->table)
  121. return _is_valid_table_div(divider->table, div);
  122. return true;
  123. }
  124. static int _div_round_up(const struct clk_div_table *table,
  125. unsigned long parent_rate, unsigned long rate)
  126. {
  127. const struct clk_div_table *clkt;
  128. int up = INT_MAX;
  129. int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  130. for (clkt = table; clkt->div; clkt++) {
  131. if (clkt->div == div)
  132. return clkt->div;
  133. else if (clkt->div < div)
  134. continue;
  135. if ((clkt->div - div) < (up - div))
  136. up = clkt->div;
  137. }
  138. return up;
  139. }
  140. static int _div_round(const struct clk_div_table *table,
  141. unsigned long parent_rate, unsigned long rate)
  142. {
  143. if (!table)
  144. return DIV_ROUND_UP(parent_rate, rate);
  145. return _div_round_up(table, parent_rate, rate);
  146. }
  147. static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
  148. unsigned long *best_parent_rate)
  149. {
  150. struct clk_omap_divider *divider = to_clk_omap_divider(hw);
  151. int i, bestdiv = 0;
  152. unsigned long parent_rate, best = 0, now, maxdiv;
  153. unsigned long parent_rate_saved = *best_parent_rate;
  154. if (!rate)
  155. rate = 1;
  156. maxdiv = divider->max;
  157. if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
  158. parent_rate = *best_parent_rate;
  159. bestdiv = _div_round(divider->table, parent_rate, rate);
  160. bestdiv = bestdiv == 0 ? 1 : bestdiv;
  161. bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
  162. return bestdiv;
  163. }
  164. /*
  165. * The maximum divider we can use without overflowing
  166. * unsigned long in rate * i below
  167. */
  168. maxdiv = min(ULONG_MAX / rate, maxdiv);
  169. for (i = 1; i <= maxdiv; i++) {
  170. if (!_is_valid_div(divider, i))
  171. continue;
  172. if (rate * i == parent_rate_saved) {
  173. /*
  174. * It's the most ideal case if the requested rate can be
  175. * divided from parent clock without needing to change
  176. * parent rate, so return the divider immediately.
  177. */
  178. *best_parent_rate = parent_rate_saved;
  179. return i;
  180. }
  181. parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
  182. MULT_ROUND_UP(rate, i));
  183. now = DIV_ROUND_UP(parent_rate, i);
  184. if (now <= rate && now > best) {
  185. bestdiv = i;
  186. best = now;
  187. *best_parent_rate = parent_rate;
  188. }
  189. }
  190. if (!bestdiv) {
  191. bestdiv = divider->max;
  192. *best_parent_rate =
  193. clk_hw_round_rate(clk_hw_get_parent(hw), 1);
  194. }
  195. return bestdiv;
  196. }
  197. static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
  198. unsigned long *prate)
  199. {
  200. int div;
  201. div = ti_clk_divider_bestdiv(hw, rate, prate);
  202. return DIV_ROUND_UP(*prate, div);
  203. }
  204. static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
  205. unsigned long parent_rate)
  206. {
  207. struct clk_omap_divider *divider;
  208. unsigned int div, value;
  209. u32 val;
  210. if (!hw || !rate)
  211. return -EINVAL;
  212. divider = to_clk_omap_divider(hw);
  213. div = DIV_ROUND_UP(parent_rate, rate);
  214. if (div > divider->max)
  215. div = divider->max;
  216. if (div < divider->min)
  217. div = divider->min;
  218. value = _get_val(divider, div);
  219. val = ti_clk_ll_ops->clk_readl(&divider->reg);
  220. val &= ~(divider->mask << divider->shift);
  221. val |= value << divider->shift;
  222. ti_clk_ll_ops->clk_writel(val, &divider->reg);
  223. ti_clk_latch(&divider->reg, divider->latch);
  224. return 0;
  225. }
  226. /**
  227. * clk_divider_save_context - Save the divider value
  228. * @hw: pointer struct clk_hw
  229. *
  230. * Save the divider value
  231. */
  232. static int clk_divider_save_context(struct clk_hw *hw)
  233. {
  234. struct clk_omap_divider *divider = to_clk_omap_divider(hw);
  235. u32 val;
  236. val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
  237. divider->context = val & divider->mask;
  238. return 0;
  239. }
  240. /**
  241. * clk_divider_restore_context - restore the saved the divider value
  242. * @hw: pointer struct clk_hw
  243. *
  244. * Restore the saved the divider value
  245. */
  246. static void clk_divider_restore_context(struct clk_hw *hw)
  247. {
  248. struct clk_omap_divider *divider = to_clk_omap_divider(hw);
  249. u32 val;
  250. val = ti_clk_ll_ops->clk_readl(&divider->reg);
  251. val &= ~(divider->mask << divider->shift);
  252. val |= divider->context << divider->shift;
  253. ti_clk_ll_ops->clk_writel(val, &divider->reg);
  254. }
  255. const struct clk_ops ti_clk_divider_ops = {
  256. .recalc_rate = ti_clk_divider_recalc_rate,
  257. .round_rate = ti_clk_divider_round_rate,
  258. .set_rate = ti_clk_divider_set_rate,
  259. .save_context = clk_divider_save_context,
  260. .restore_context = clk_divider_restore_context,
  261. };
  262. static struct clk *_register_divider(struct device_node *node,
  263. u32 flags,
  264. struct clk_omap_divider *div)
  265. {
  266. struct clk *clk;
  267. struct clk_init_data init;
  268. const char *parent_name;
  269. parent_name = of_clk_get_parent_name(node, 0);
  270. init.name = node->name;
  271. init.ops = &ti_clk_divider_ops;
  272. init.flags = flags;
  273. init.parent_names = (parent_name ? &parent_name : NULL);
  274. init.num_parents = (parent_name ? 1 : 0);
  275. div->hw.init = &init;
  276. /* register the clock */
  277. clk = ti_clk_register(NULL, &div->hw, node->name);
  278. if (IS_ERR(clk))
  279. kfree(div);
  280. return clk;
  281. }
  282. int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
  283. u8 flags, struct clk_omap_divider *divider)
  284. {
  285. int valid_div = 0;
  286. int i;
  287. struct clk_div_table *tmp;
  288. u16 min_div = 0;
  289. if (!div_table) {
  290. divider->min = 1;
  291. divider->max = max_div;
  292. _setup_mask(divider);
  293. return 0;
  294. }
  295. i = 0;
  296. while (!num_dividers || i < num_dividers) {
  297. if (div_table[i] == -1)
  298. break;
  299. if (div_table[i])
  300. valid_div++;
  301. i++;
  302. }
  303. num_dividers = i;
  304. tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
  305. if (!tmp)
  306. return -ENOMEM;
  307. valid_div = 0;
  308. for (i = 0; i < num_dividers; i++)
  309. if (div_table[i] > 0) {
  310. tmp[valid_div].div = div_table[i];
  311. tmp[valid_div].val = i;
  312. valid_div++;
  313. if (div_table[i] > max_div)
  314. max_div = div_table[i];
  315. if (!min_div || div_table[i] < min_div)
  316. min_div = div_table[i];
  317. }
  318. divider->min = min_div;
  319. divider->max = max_div;
  320. divider->table = tmp;
  321. _setup_mask(divider);
  322. return 0;
  323. }
  324. static int __init ti_clk_get_div_table(struct device_node *node,
  325. struct clk_omap_divider *div)
  326. {
  327. struct clk_div_table *table;
  328. const __be32 *divspec;
  329. u32 val;
  330. u32 num_div;
  331. u32 valid_div;
  332. int i;
  333. divspec = of_get_property(node, "ti,dividers", &num_div);
  334. if (!divspec)
  335. return 0;
  336. num_div /= 4;
  337. valid_div = 0;
  338. /* Determine required size for divider table */
  339. for (i = 0; i < num_div; i++) {
  340. of_property_read_u32_index(node, "ti,dividers", i, &val);
  341. if (val)
  342. valid_div++;
  343. }
  344. if (!valid_div) {
  345. pr_err("no valid dividers for %pOFn table\n", node);
  346. return -EINVAL;
  347. }
  348. table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
  349. if (!table)
  350. return -ENOMEM;
  351. valid_div = 0;
  352. for (i = 0; i < num_div; i++) {
  353. of_property_read_u32_index(node, "ti,dividers", i, &val);
  354. if (val) {
  355. table[valid_div].div = val;
  356. table[valid_div].val = i;
  357. valid_div++;
  358. }
  359. }
  360. div->table = table;
  361. return 0;
  362. }
  363. static int _populate_divider_min_max(struct device_node *node,
  364. struct clk_omap_divider *divider)
  365. {
  366. u32 min_div = 0;
  367. u32 max_div = 0;
  368. u32 val;
  369. const struct clk_div_table *clkt;
  370. if (!divider->table) {
  371. /* Clk divider table not provided, determine min/max divs */
  372. if (of_property_read_u32(node, "ti,min-div", &min_div))
  373. min_div = 1;
  374. if (of_property_read_u32(node, "ti,max-div", &max_div)) {
  375. pr_err("no max-div for %pOFn!\n", node);
  376. return -EINVAL;
  377. }
  378. } else {
  379. for (clkt = divider->table; clkt->div; clkt++) {
  380. val = clkt->div;
  381. if (val > max_div)
  382. max_div = val;
  383. if (!min_div || val < min_div)
  384. min_div = val;
  385. }
  386. }
  387. divider->min = min_div;
  388. divider->max = max_div;
  389. _setup_mask(divider);
  390. return 0;
  391. }
  392. static int __init ti_clk_divider_populate(struct device_node *node,
  393. struct clk_omap_divider *div,
  394. u32 *flags)
  395. {
  396. u32 val;
  397. int ret;
  398. ret = ti_clk_get_reg_addr(node, 0, &div->reg);
  399. if (ret)
  400. return ret;
  401. if (!of_property_read_u32(node, "ti,bit-shift", &val))
  402. div->shift = val;
  403. else
  404. div->shift = 0;
  405. if (!of_property_read_u32(node, "ti,latch-bit", &val))
  406. div->latch = val;
  407. else
  408. div->latch = -EINVAL;
  409. *flags = 0;
  410. div->flags = 0;
  411. if (of_property_read_bool(node, "ti,index-starts-at-one"))
  412. div->flags |= CLK_DIVIDER_ONE_BASED;
  413. if (of_property_read_bool(node, "ti,index-power-of-two"))
  414. div->flags |= CLK_DIVIDER_POWER_OF_TWO;
  415. if (of_property_read_bool(node, "ti,set-rate-parent"))
  416. *flags |= CLK_SET_RATE_PARENT;
  417. ret = ti_clk_get_div_table(node, div);
  418. if (ret)
  419. return ret;
  420. return _populate_divider_min_max(node, div);
  421. }
  422. /**
  423. * of_ti_divider_clk_setup - Setup function for simple div rate clock
  424. * @node: device node for this clock
  425. *
  426. * Sets up a basic divider clock.
  427. */
  428. static void __init of_ti_divider_clk_setup(struct device_node *node)
  429. {
  430. struct clk *clk;
  431. u32 flags = 0;
  432. struct clk_omap_divider *div;
  433. div = kzalloc(sizeof(*div), GFP_KERNEL);
  434. if (!div)
  435. return;
  436. if (ti_clk_divider_populate(node, div, &flags))
  437. goto cleanup;
  438. clk = _register_divider(node, flags, div);
  439. if (!IS_ERR(clk)) {
  440. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  441. of_ti_clk_autoidle_setup(node);
  442. return;
  443. }
  444. cleanup:
  445. kfree(div->table);
  446. kfree(div);
  447. }
  448. CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
  449. static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
  450. {
  451. struct clk_omap_divider *div;
  452. u32 tmp;
  453. div = kzalloc(sizeof(*div), GFP_KERNEL);
  454. if (!div)
  455. return;
  456. if (ti_clk_divider_populate(node, div, &tmp))
  457. goto cleanup;
  458. if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
  459. return;
  460. cleanup:
  461. kfree(div->table);
  462. kfree(div);
  463. }
  464. CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
  465. of_ti_composite_divider_clk_setup);