clk-dra7-atl.c 7.4 KB

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  1. /*
  2. * DRA7 ATL (Audio Tracking Logic) clock driver
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/clk/ti.h>
  27. #include "clock.h"
  28. #define DRA7_ATL_INSTANCES 4
  29. #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
  30. #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
  31. #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
  32. #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
  33. #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
  34. #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
  35. #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
  36. #define DRA7_ATL_SWEN BIT(0)
  37. #define DRA7_ATL_DIVIDER_MASK (0x1f)
  38. #define DRA7_ATL_PCLKMUX BIT(0)
  39. struct dra7_atl_clock_info;
  40. struct dra7_atl_desc {
  41. struct clk *clk;
  42. struct clk_hw hw;
  43. struct dra7_atl_clock_info *cinfo;
  44. int id;
  45. bool probed; /* the driver for the IP has been loaded */
  46. bool valid; /* configured */
  47. bool enabled;
  48. u32 bws; /* Baseband Word Select Mux */
  49. u32 aws; /* Audio Word Select Mux */
  50. u32 divider; /* Cached divider value */
  51. };
  52. struct dra7_atl_clock_info {
  53. struct device *dev;
  54. void __iomem *iobase;
  55. struct dra7_atl_desc *cdesc;
  56. };
  57. #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
  58. static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
  59. u32 val)
  60. {
  61. __raw_writel(val, cinfo->iobase + reg);
  62. }
  63. static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
  64. {
  65. return __raw_readl(cinfo->iobase + reg);
  66. }
  67. static int atl_clk_enable(struct clk_hw *hw)
  68. {
  69. struct dra7_atl_desc *cdesc = to_atl_desc(hw);
  70. if (!cdesc->probed)
  71. goto out;
  72. if (unlikely(!cdesc->valid))
  73. dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
  74. cdesc->id);
  75. pm_runtime_get_sync(cdesc->cinfo->dev);
  76. atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
  77. cdesc->divider - 1);
  78. atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
  79. out:
  80. cdesc->enabled = true;
  81. return 0;
  82. }
  83. static void atl_clk_disable(struct clk_hw *hw)
  84. {
  85. struct dra7_atl_desc *cdesc = to_atl_desc(hw);
  86. if (!cdesc->probed)
  87. goto out;
  88. atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
  89. pm_runtime_put_sync(cdesc->cinfo->dev);
  90. out:
  91. cdesc->enabled = false;
  92. }
  93. static int atl_clk_is_enabled(struct clk_hw *hw)
  94. {
  95. struct dra7_atl_desc *cdesc = to_atl_desc(hw);
  96. return cdesc->enabled;
  97. }
  98. static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
  99. unsigned long parent_rate)
  100. {
  101. struct dra7_atl_desc *cdesc = to_atl_desc(hw);
  102. return parent_rate / cdesc->divider;
  103. }
  104. static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  105. unsigned long *parent_rate)
  106. {
  107. unsigned divider;
  108. divider = (*parent_rate + rate / 2) / rate;
  109. if (divider > DRA7_ATL_DIVIDER_MASK + 1)
  110. divider = DRA7_ATL_DIVIDER_MASK + 1;
  111. return *parent_rate / divider;
  112. }
  113. static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  114. unsigned long parent_rate)
  115. {
  116. struct dra7_atl_desc *cdesc;
  117. u32 divider;
  118. if (!hw || !rate)
  119. return -EINVAL;
  120. cdesc = to_atl_desc(hw);
  121. divider = ((parent_rate + rate / 2) / rate) - 1;
  122. if (divider > DRA7_ATL_DIVIDER_MASK)
  123. divider = DRA7_ATL_DIVIDER_MASK;
  124. cdesc->divider = divider + 1;
  125. return 0;
  126. }
  127. static const struct clk_ops atl_clk_ops = {
  128. .enable = atl_clk_enable,
  129. .disable = atl_clk_disable,
  130. .is_enabled = atl_clk_is_enabled,
  131. .recalc_rate = atl_clk_recalc_rate,
  132. .round_rate = atl_clk_round_rate,
  133. .set_rate = atl_clk_set_rate,
  134. };
  135. static void __init of_dra7_atl_clock_setup(struct device_node *node)
  136. {
  137. struct dra7_atl_desc *clk_hw = NULL;
  138. struct clk_init_data init = { NULL };
  139. const char **parent_names = NULL;
  140. struct clk *clk;
  141. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  142. if (!clk_hw) {
  143. pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
  144. return;
  145. }
  146. clk_hw->hw.init = &init;
  147. clk_hw->divider = 1;
  148. init.name = node->name;
  149. init.ops = &atl_clk_ops;
  150. init.flags = CLK_IGNORE_UNUSED;
  151. init.num_parents = of_clk_get_parent_count(node);
  152. if (init.num_parents != 1) {
  153. pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
  154. node);
  155. goto cleanup;
  156. }
  157. parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
  158. if (!parent_names)
  159. goto cleanup;
  160. parent_names[0] = of_clk_get_parent_name(node, 0);
  161. init.parent_names = parent_names;
  162. clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
  163. if (!IS_ERR(clk)) {
  164. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  165. kfree(parent_names);
  166. return;
  167. }
  168. cleanup:
  169. kfree(parent_names);
  170. kfree(clk_hw);
  171. }
  172. CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
  173. static int of_dra7_atl_clk_probe(struct platform_device *pdev)
  174. {
  175. struct device_node *node = pdev->dev.of_node;
  176. struct dra7_atl_clock_info *cinfo;
  177. int i;
  178. int ret = 0;
  179. if (!node)
  180. return -ENODEV;
  181. cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
  182. if (!cinfo)
  183. return -ENOMEM;
  184. cinfo->iobase = of_iomap(node, 0);
  185. cinfo->dev = &pdev->dev;
  186. pm_runtime_enable(cinfo->dev);
  187. pm_runtime_get_sync(cinfo->dev);
  188. atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
  189. for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
  190. struct device_node *cfg_node;
  191. char prop[5];
  192. struct dra7_atl_desc *cdesc;
  193. struct of_phandle_args clkspec;
  194. struct clk *clk;
  195. int rc;
  196. rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
  197. NULL, i, &clkspec);
  198. if (rc) {
  199. pr_err("%s: failed to lookup atl clock %d\n", __func__,
  200. i);
  201. return -EINVAL;
  202. }
  203. clk = of_clk_get_from_provider(&clkspec);
  204. if (IS_ERR(clk)) {
  205. pr_err("%s: failed to get atl clock %d from provider\n",
  206. __func__, i);
  207. return PTR_ERR(clk);
  208. }
  209. cdesc = to_atl_desc(__clk_get_hw(clk));
  210. cdesc->cinfo = cinfo;
  211. cdesc->id = i;
  212. /* Get configuration for the ATL instances */
  213. snprintf(prop, sizeof(prop), "atl%u", i);
  214. cfg_node = of_get_child_by_name(node, prop);
  215. if (cfg_node) {
  216. ret = of_property_read_u32(cfg_node, "bws",
  217. &cdesc->bws);
  218. ret |= of_property_read_u32(cfg_node, "aws",
  219. &cdesc->aws);
  220. if (!ret) {
  221. cdesc->valid = true;
  222. atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
  223. cdesc->bws);
  224. atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
  225. cdesc->aws);
  226. }
  227. of_node_put(cfg_node);
  228. }
  229. cdesc->probed = true;
  230. /*
  231. * Enable the clock if it has been asked prior to loading the
  232. * hw driver
  233. */
  234. if (cdesc->enabled)
  235. atl_clk_enable(__clk_get_hw(clk));
  236. }
  237. pm_runtime_put_sync(cinfo->dev);
  238. return ret;
  239. }
  240. static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
  241. { .compatible = "ti,dra7-atl", },
  242. {},
  243. };
  244. static struct platform_driver dra7_atl_clk_driver = {
  245. .driver = {
  246. .name = "dra7-atl",
  247. .suppress_bind_attrs = true,
  248. .of_match_table = of_dra7_atl_clk_match_tbl,
  249. },
  250. .probe = of_dra7_atl_clk_probe,
  251. };
  252. builtin_platform_driver(dra7_atl_clk_driver);