clk-7xx-compat.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DRA7 Clock init
  4. *
  5. * Copyright (C) 2013 Texas Instruments, Inc.
  6. *
  7. * Tero Kristo (t-kristo@ti.com)
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/list.h>
  11. #include <linux/clk.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/clk/ti.h>
  14. #include <dt-bindings/clock/dra7.h>
  15. #include "clock.h"
  16. #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
  17. #define DRA7_DPLL_USB_DEFFREQ 960000000
  18. static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
  19. { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
  20. { 0 },
  21. };
  22. static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
  23. "per_abe_x1_gfclk2_div",
  24. "video1_clk2_div",
  25. "video2_clk2_div",
  26. "hdmi_clk2_div",
  27. NULL,
  28. };
  29. static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
  30. "abe_24m_fclk",
  31. "abe_sys_clk_div",
  32. "func_24m_clk",
  33. "atl_clkin3_ck",
  34. "atl_clkin2_ck",
  35. "atl_clkin1_ck",
  36. "atl_clkin0_ck",
  37. "sys_clkin2",
  38. "ref_clkin0_ck",
  39. "ref_clkin1_ck",
  40. "ref_clkin2_ck",
  41. "ref_clkin3_ck",
  42. "mlb_clk",
  43. "mlbp_clk",
  44. NULL,
  45. };
  46. static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
  47. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  48. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  49. { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  50. { 0 },
  51. };
  52. static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
  53. "timer_sys_clk_div",
  54. "sys_32k_ck",
  55. "sys_clkin2",
  56. "ref_clkin0_ck",
  57. "ref_clkin1_ck",
  58. "ref_clkin2_ck",
  59. "ref_clkin3_ck",
  60. "abe_giclk_div",
  61. "video1_div_clk",
  62. "video2_div_clk",
  63. "hdmi_div_clk",
  64. "clkoutmux0_clk_mux",
  65. NULL,
  66. };
  67. static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
  68. { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  69. { 0 },
  70. };
  71. static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
  72. { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  73. { 0 },
  74. };
  75. static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
  76. { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  77. { 0 },
  78. };
  79. static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
  80. { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  81. { 0 },
  82. };
  83. static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
  84. "func_48m_fclk",
  85. "dpll_per_m2x2_ck",
  86. NULL,
  87. };
  88. static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
  89. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  90. { 0 },
  91. };
  92. static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
  93. { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
  94. { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
  95. { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
  96. { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
  97. { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
  98. { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
  99. { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
  100. { 0 },
  101. };
  102. static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
  103. { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
  104. { 0 },
  105. };
  106. static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
  107. { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
  108. { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
  109. { 0 },
  110. };
  111. static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
  112. { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
  113. { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
  114. { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
  115. { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
  116. { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
  117. { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
  118. { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
  119. { 0 },
  120. };
  121. static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
  122. { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
  123. { 0 },
  124. };
  125. static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
  126. { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
  127. { 0 },
  128. };
  129. static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
  130. "sys_32k_ck",
  131. "video1_clkin_ck",
  132. "video2_clkin_ck",
  133. "hdmi_clkin_ck",
  134. NULL,
  135. };
  136. static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
  137. "l3_iclk_div",
  138. "dpll_abe_m2_ck",
  139. "atl_cm:clk:0000:24",
  140. NULL,
  141. };
  142. static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
  143. { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
  144. { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
  145. { 0 },
  146. };
  147. static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
  148. { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
  149. { 0 },
  150. };
  151. static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
  152. { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
  153. { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
  154. { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
  155. { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
  156. { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
  157. { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
  158. { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
  159. { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
  160. { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
  161. { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
  162. { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
  163. { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
  164. { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
  165. { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
  166. { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
  167. { 0 },
  168. };
  169. static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
  170. { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
  171. { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
  172. { 0 },
  173. };
  174. static const char * const dra7_dss_dss_clk_parents[] __initconst = {
  175. "dpll_per_h12x2_ck",
  176. NULL,
  177. };
  178. static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
  179. "func_48m_fclk",
  180. NULL,
  181. };
  182. static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
  183. "hdmi_dpll_clk_mux",
  184. NULL,
  185. };
  186. static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
  187. "sys_32k_ck",
  188. NULL,
  189. };
  190. static const char * const dra7_dss_video1_clk_parents[] __initconst = {
  191. "video1_dpll_clk_mux",
  192. NULL,
  193. };
  194. static const char * const dra7_dss_video2_clk_parents[] __initconst = {
  195. "video2_dpll_clk_mux",
  196. NULL,
  197. };
  198. static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
  199. { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
  200. { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
  201. { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
  202. { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  203. { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
  204. { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
  205. { 0 },
  206. };
  207. static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
  208. { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
  209. { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
  210. { 0 },
  211. };
  212. static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
  213. "func_128m_clk",
  214. "dpll_per_m2x2_ck",
  215. NULL,
  216. };
  217. static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
  218. "l3init_cm:clk:0008:24",
  219. NULL,
  220. };
  221. static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
  222. .max_div = 4,
  223. .flags = CLK_DIVIDER_POWER_OF_TWO,
  224. };
  225. static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
  226. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  227. { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
  228. { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
  229. { 0 },
  230. };
  231. static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
  232. "l3init_cm:clk:0010:24",
  233. NULL,
  234. };
  235. static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
  236. .max_div = 4,
  237. .flags = CLK_DIVIDER_POWER_OF_TWO,
  238. };
  239. static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
  240. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  241. { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
  242. { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
  243. { 0 },
  244. };
  245. static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
  246. "l3init_960m_gfclk",
  247. NULL,
  248. };
  249. static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
  250. { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
  251. { 0 },
  252. };
  253. static const char * const dra7_sata_ref_clk_parents[] __initconst = {
  254. "sys_clkin1",
  255. NULL,
  256. };
  257. static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
  258. { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
  259. { 0 },
  260. };
  261. static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
  262. "apll_pcie_ck",
  263. NULL,
  264. };
  265. static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
  266. "optfclk_pciephy_div",
  267. NULL,
  268. };
  269. static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
  270. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  271. { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
  272. { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
  273. { 0 },
  274. };
  275. static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
  276. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  277. { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
  278. { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
  279. { 0 },
  280. };
  281. static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
  282. "dpll_gmac_h11x2_ck",
  283. "rmii_clk_ck",
  284. NULL,
  285. };
  286. static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
  287. "video1_clkin_ck",
  288. "video2_clkin_ck",
  289. "dpll_abe_m2_ck",
  290. "hdmi_clkin_ck",
  291. "l3_iclk_div",
  292. NULL,
  293. };
  294. static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
  295. { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
  296. { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
  297. { 0 },
  298. };
  299. static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
  300. { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
  301. { 0 },
  302. };
  303. static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
  304. { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
  305. { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
  306. { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
  307. { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
  308. { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
  309. { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
  310. { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
  311. { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
  312. { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
  313. { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
  314. { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
  315. { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
  316. { 0 },
  317. };
  318. static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
  319. "timer_sys_clk_div",
  320. "sys_32k_ck",
  321. "sys_clkin2",
  322. "ref_clkin0_ck",
  323. "ref_clkin1_ck",
  324. "ref_clkin2_ck",
  325. "ref_clkin3_ck",
  326. "abe_giclk_div",
  327. "video1_div_clk",
  328. "video2_div_clk",
  329. "hdmi_div_clk",
  330. NULL,
  331. };
  332. static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
  333. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  334. { 0 },
  335. };
  336. static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
  337. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  338. { 0 },
  339. };
  340. static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
  341. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  342. { 0 },
  343. };
  344. static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
  345. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  346. { 0 },
  347. };
  348. static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
  349. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  350. { 0 },
  351. };
  352. static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
  353. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  354. { 0 },
  355. };
  356. static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
  357. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  358. { 0 },
  359. };
  360. static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
  361. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  362. { 0 },
  363. };
  364. static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
  365. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  366. { 0 },
  367. };
  368. static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
  369. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  370. { 0 },
  371. };
  372. static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
  373. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  374. { 0 },
  375. };
  376. static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
  377. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  378. { 0 },
  379. };
  380. static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
  381. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  382. { 0 },
  383. };
  384. static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
  385. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  386. { 0 },
  387. };
  388. static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
  389. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  390. { 0 },
  391. };
  392. static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
  393. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  394. { 0 },
  395. };
  396. static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
  397. "l4per_cm:clk:0120:24",
  398. NULL,
  399. };
  400. static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
  401. .max_div = 4,
  402. .flags = CLK_DIVIDER_POWER_OF_TWO,
  403. };
  404. static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
  405. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  406. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  407. { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
  408. { 0 },
  409. };
  410. static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
  411. "l4per_cm:clk:0128:24",
  412. NULL,
  413. };
  414. static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
  415. .max_div = 4,
  416. .flags = CLK_DIVIDER_POWER_OF_TWO,
  417. };
  418. static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
  419. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  420. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  421. { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
  422. { 0 },
  423. };
  424. static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
  425. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  426. { 0 },
  427. };
  428. static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
  429. "func_128m_clk",
  430. "dpll_per_h13x2_ck",
  431. NULL,
  432. };
  433. static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
  434. "l4per_cm:clk:0138:24",
  435. NULL,
  436. };
  437. static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
  438. .max_div = 4,
  439. .flags = CLK_DIVIDER_POWER_OF_TWO,
  440. };
  441. static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
  442. { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
  443. { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
  444. { 0 },
  445. };
  446. static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
  447. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  448. { 0 },
  449. };
  450. static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
  451. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  452. { 0 },
  453. };
  454. static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
  455. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  456. { 0 },
  457. };
  458. static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
  459. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  460. { 0 },
  461. };
  462. static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
  463. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  464. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  465. { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  466. { 0 },
  467. };
  468. static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
  469. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  470. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  471. { 0 },
  472. };
  473. static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
  474. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  475. { 0 },
  476. };
  477. static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
  478. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  479. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  480. { 0 },
  481. };
  482. static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
  483. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  484. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  485. { 0 },
  486. };
  487. static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
  488. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  489. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  490. { 0 },
  491. };
  492. static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
  493. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  494. { 0 },
  495. };
  496. static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
  497. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  498. { 0 },
  499. };
  500. static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
  501. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  502. { 0 },
  503. };
  504. static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
  505. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  506. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  507. { 0 },
  508. };
  509. static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
  510. { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  511. { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  512. { 0 },
  513. };
  514. static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
  515. { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
  516. { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
  517. { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
  518. { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
  519. { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
  520. { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
  521. { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
  522. { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
  523. { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
  524. { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  525. { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  526. { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  527. { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  528. { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  529. { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
  530. { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
  531. { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
  532. { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
  533. { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
  534. { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
  535. { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
  536. { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
  537. { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
  538. { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
  539. { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
  540. { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
  541. { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
  542. { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
  543. { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
  544. { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
  545. { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  546. { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
  547. { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
  548. { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
  549. { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
  550. { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
  551. { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
  552. { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
  553. { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
  554. { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
  555. { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
  556. { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
  557. { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
  558. { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
  559. { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
  560. { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
  561. { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
  562. { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
  563. { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
  564. { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
  565. { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
  566. { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
  567. { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
  568. { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
  569. { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
  570. { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
  571. { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
  572. { 0 },
  573. };
  574. static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
  575. { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
  576. { 0 },
  577. };
  578. static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
  579. { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
  580. { 0 },
  581. };
  582. static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
  583. { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
  584. { 0 },
  585. };
  586. static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
  587. "sys_clkin1",
  588. "sys_clkin2",
  589. NULL,
  590. };
  591. static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
  592. { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
  593. { 0 },
  594. };
  595. static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
  596. { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
  597. { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
  598. { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
  599. { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
  600. { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
  601. { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
  602. { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
  603. { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
  604. { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
  605. { 0 },
  606. };
  607. const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
  608. { 0x4a005320, dra7_mpu_clkctrl_regs },
  609. { 0x4a005540, dra7_ipu_clkctrl_regs },
  610. { 0x4a005740, dra7_rtc_clkctrl_regs },
  611. { 0x4a008620, dra7_coreaon_clkctrl_regs },
  612. { 0x4a008720, dra7_l3main1_clkctrl_regs },
  613. { 0x4a008a20, dra7_dma_clkctrl_regs },
  614. { 0x4a008b20, dra7_emif_clkctrl_regs },
  615. { 0x4a008c00, dra7_atl_clkctrl_regs },
  616. { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
  617. { 0x4a008e20, dra7_l3instr_clkctrl_regs },
  618. { 0x4a009120, dra7_dss_clkctrl_regs },
  619. { 0x4a009320, dra7_l3init_clkctrl_regs },
  620. { 0x4a009700, dra7_l4per_clkctrl_regs },
  621. { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
  622. { 0 },
  623. };
  624. struct ti_dt_clk dra7xx_compat_clks[] = {
  625. DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
  626. DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
  627. DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
  628. DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
  629. DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
  630. DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
  631. DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
  632. DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
  633. DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
  634. DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
  635. DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
  636. DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
  637. DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
  638. DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
  639. DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
  640. DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
  641. DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
  642. DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
  643. DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
  644. DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
  645. DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
  646. DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
  647. DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
  648. DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
  649. DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
  650. DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
  651. DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
  652. DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
  653. DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
  654. DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
  655. DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
  656. DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
  657. DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
  658. DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
  659. DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
  660. DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
  661. DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
  662. DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
  663. DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
  664. DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
  665. DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
  666. DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
  667. DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
  668. DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
  669. DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
  670. DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
  671. DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
  672. DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
  673. DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
  674. DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
  675. DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
  676. DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
  677. DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
  678. DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
  679. DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
  680. DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
  681. DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
  682. DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
  683. DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
  684. DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
  685. DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
  686. DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
  687. DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
  688. DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
  689. DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
  690. DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
  691. DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
  692. DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
  693. DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
  694. DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
  695. DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
  696. DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
  697. DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
  698. DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
  699. DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
  700. DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
  701. DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
  702. DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
  703. DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
  704. DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
  705. DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
  706. DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
  707. DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
  708. DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
  709. DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
  710. DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
  711. DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
  712. DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
  713. { .node_name = NULL },
  714. };