clk-43xx-compat.c 9.6 KB

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  1. /*
  2. * AM43XX Clock init
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/clk/ti.h>
  21. #include <dt-bindings/clock/am4.h>
  22. #include "clock.h"
  23. static const char * const am4_synctimer_32kclk_parents[] __initconst = {
  24. "mux_synctimer32k_ck",
  25. NULL,
  26. };
  27. static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
  28. { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
  29. { 0 },
  30. };
  31. static const char * const am4_gpio0_dbclk_parents[] __initconst = {
  32. "gpio0_dbclk_mux_ck",
  33. NULL,
  34. };
  35. static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
  36. { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
  37. { 0 },
  38. };
  39. static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
  40. { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
  41. { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
  42. { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
  43. { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
  44. { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
  45. { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
  46. { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
  47. { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
  48. { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
  49. { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
  50. { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
  51. { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
  52. { 0 },
  53. };
  54. static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
  55. { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
  56. { 0 },
  57. };
  58. static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
  59. { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
  60. { 0 },
  61. };
  62. static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
  63. { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
  64. { 0 },
  65. };
  66. static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
  67. "dpll_per_clkdcoldo",
  68. NULL,
  69. };
  70. static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
  71. { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
  72. { 0 },
  73. };
  74. static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
  75. { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
  76. { 0 },
  77. };
  78. static const char * const am4_gpio1_dbclk_parents[] __initconst = {
  79. "clkdiv32k_ick",
  80. NULL,
  81. };
  82. static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
  83. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  84. { 0 },
  85. };
  86. static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
  87. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  88. { 0 },
  89. };
  90. static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
  91. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  92. { 0 },
  93. };
  94. static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
  95. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  96. { 0 },
  97. };
  98. static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
  99. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  100. { 0 },
  101. };
  102. static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
  103. { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  104. { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
  105. { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  106. { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  107. { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  108. { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  109. { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
  110. { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
  111. { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  112. { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  113. { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  114. { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  115. { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
  116. { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
  117. { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
  118. { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
  119. { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
  120. { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
  121. { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
  122. { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
  123. { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
  124. { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  125. { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
  126. { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
  127. { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  128. { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  129. { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  130. { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  131. { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  132. { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  133. { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  134. { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  135. { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  136. { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  137. { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  138. { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  139. { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
  140. { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  141. { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  142. { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  143. { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  144. { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  145. { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
  146. { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  147. { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  148. { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  149. { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  150. { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  151. { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  152. { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
  153. { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
  154. { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
  155. { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
  156. { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
  157. { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
  158. { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
  159. { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
  160. { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
  161. { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
  162. { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  163. { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  164. { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  165. { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  166. { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  167. { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  168. { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  169. { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
  170. { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
  171. { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
  172. { 0 },
  173. };
  174. const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
  175. { 0x44df2820, am4_l4_wkup_clkctrl_regs },
  176. { 0x44df8320, am4_mpu_clkctrl_regs },
  177. { 0x44df8420, am4_gfx_l3_clkctrl_regs },
  178. { 0x44df8520, am4_l4_rtc_clkctrl_regs },
  179. { 0x44df8820, am4_l4_per_clkctrl_regs },
  180. { 0 },
  181. };
  182. const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
  183. { 0x44df2820, am4_l4_wkup_clkctrl_regs },
  184. { 0x44df8320, am4_mpu_clkctrl_regs },
  185. { 0x44df8420, am4_gfx_l3_clkctrl_regs },
  186. { 0x44df8820, am4_l4_per_clkctrl_regs },
  187. { 0 },
  188. };
  189. struct ti_dt_clk am43xx_compat_clks[] = {
  190. DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
  191. DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
  192. DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
  193. DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
  194. DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
  195. DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
  196. DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
  197. DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
  198. DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
  199. DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
  200. DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
  201. { .node_name = NULL },
  202. };