vpsys-gate.c 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2022 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/clock/light-fm-ap-clock.h>
  6. #include <dt-bindings/clock/light-vpsys.h>
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/types.h>
  17. #include "../clk.h"
  18. static struct clk *gates[LIGHT_VPSYS_CLK_END];
  19. static struct clk_onecell_data clk_gate_data;
  20. static u32 share_cnt_g2d_clk_en;
  21. static u32 share_cnt_fce_clk_en;
  22. static int light_vpsys_clk_probe(struct platform_device *pdev)
  23. {
  24. struct device *dev = &pdev->dev;
  25. struct device_node *np = dev->of_node;
  26. void __iomem *gate_base;
  27. int ret;
  28. gate_base = devm_platform_ioremap_resource(pdev, 0);
  29. if (WARN_ON(IS_ERR(gate_base)))
  30. return PTR_ERR(gate_base);
  31. /* we assume that the gate clock is a root clock */
  32. gates[LIGHT_VPSYS_G2D_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_pclk", NULL,
  33. gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
  34. gates[LIGHT_VPSYS_G2D_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_aclk", NULL,
  35. gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
  36. gates[LIGHT_VPSYS_G2D_CCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_cclk", NULL,
  37. gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
  38. gates[LIGHT_VPSYS_FCE_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_pclk", NULL,
  39. gate_base + 0x20, 2, &share_cnt_fce_clk_en);
  40. gates[LIGHT_VPSYS_FCE_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_aclk", NULL,
  41. gate_base + 0x20, 2, &share_cnt_fce_clk_en);
  42. gates[LIGHT_VPSYS_VDEC_ACLK] = thead_clk_light_gate("clkgen_vdec_aclk", NULL, gate_base + 0x20, 4);
  43. gates[LIGHT_VPSYS_VDEC_CCLK] = thead_clk_light_gate("clkgen_vdec_cclk", NULL, gate_base + 0x20, 5);
  44. gates[LIGHT_VPSYS_VDEC_PCLK] = thead_clk_light_gate("clkgen_vdec_pclk", NULL, gate_base + 0x20, 6);
  45. gates[LIGHT_VPSYS_VENC_CCLK] = thead_clk_light_gate("clkgen_venc_cclk", NULL, gate_base + 0x20, 8);
  46. gates[LIGHT_VPSYS_VENC_PCLK] = thead_clk_light_gate("clkgen_venc_pclk", NULL, gate_base + 0x20, 9);
  47. gates[LIGHT_VPSYS_VENC_ACLK] = thead_clk_light_gate("clkgen_venc_aclk", NULL, gate_base + 0x20, 7);
  48. clk_gate_data.clks = gates;
  49. clk_gate_data.clk_num = ARRAY_SIZE(gates);
  50. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
  51. if (ret < 0) {
  52. dev_err(dev, "failed to register gate clks for light vpsys\n");
  53. goto unregister_clks;
  54. }
  55. dev_info(dev, "succeed to register vpsys gate clock provider\n");
  56. return 0;
  57. unregister_clks:
  58. thead_unregister_clocks(gates, ARRAY_SIZE(gates));
  59. return ret;
  60. }
  61. static const struct of_device_id vpsys_clk_gate_of_match[] = {
  62. { .compatible = "thead,vpsys-gate-controller" },
  63. { /* sentinel */ },
  64. };
  65. MODULE_DEVICE_TABLE(of, vpsys_clk_gate_of_match);
  66. static struct platform_driver light_vpsys_clk_driver = {
  67. .probe = light_vpsys_clk_probe,
  68. .driver = {
  69. .name = "vpsys-clk-gate-provider",
  70. .of_match_table = of_match_ptr(vpsys_clk_gate_of_match),
  71. },
  72. };
  73. module_platform_driver(light_vpsys_clk_driver);
  74. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  75. MODULE_DESCRIPTION("Thead Light Fullmask vpsys clock gate provider");
  76. MODULE_LICENSE("GPL v2");