vosys-gate.c 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2022 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/clock/light-fm-ap-clock.h>
  6. #include <dt-bindings/clock/light-vosys.h>
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/types.h>
  17. #include "../clk.h"
  18. static struct clk *gates[LIGHT_CLKGEN_VOSYS_CLK_END];
  19. static struct clk_onecell_data clk_gate_data;
  20. static int light_vosys_clk_probe(struct platform_device *pdev)
  21. {
  22. struct device *dev = &pdev->dev;
  23. struct device_node *np = dev->of_node;
  24. void __iomem *gate_base;
  25. int ret;
  26. gate_base = devm_platform_ioremap_resource(pdev, 0);
  27. if (WARN_ON(IS_ERR(gate_base)))
  28. return PTR_ERR(gate_base);
  29. /* we assume that the gate clock is a root clock */
  30. gates[LIGHT_CLKGEN_AXI4_VO_PCLK] = thead_clk_light_gate("clkgen_axi4_vo_pclk", NULL,
  31. gate_base + 0x50, 22);
  32. gates[LIGHT_CLKGEN_IOPMP_VOSYS_DPU_PCLK] = thead_clk_light_gate("clkgen_iopmp_dpu_pclk", NULL,
  33. gate_base + 0x50, 23);
  34. gates[LIGHT_CLKGEN_IOPMP_VOSYS_DPU1_PCLK] = thead_clk_light_gate("clkgen_iopmp_dpu1_pclk", NULL,
  35. gate_base + 0x50, 24);
  36. gates[LIGHT_CLKGEN_IOPMP_VOSYS_GPU_PCLK] = thead_clk_light_gate("clkgen_iopmp_gpu_pclk", NULL,
  37. gate_base + 0x50, 25);
  38. gates[LIGHT_CLKGEN_HDMI_PCLK] = thead_clk_light_gate("clkgen_hdmi_pclk", NULL, gate_base + 0x50, 11);
  39. gates[LIGHT_CLKGEN_MIPIDSI0_PCLK] = thead_clk_light_gate("clkgen_mipidsi0_pclk", NULL,
  40. gate_base + 0x50, 13);
  41. gates[LIGHT_CLKGEN_MIPIDSI1_PCLK] = thead_clk_light_gate("clkgen_mipidsi1_pclk", NULL,
  42. gate_base + 0x50, 14);
  43. gates[LIGHT_CLKGEN_AXI4_VO_ACLK] = thead_clk_light_gate("clkgen_axi4_vo_aclk", NULL,
  44. gate_base + 0x50, 0);
  45. gates[LIGHT_CLKGEN_IOPMP_GPU_ACLK] = thead_clk_light_gate("clkgen_iopmp_gpu_aclk", NULL,
  46. gate_base + 0x50, 29);
  47. gates[LIGHT_CLKGEN_IOPMP_DPU_ACLK] = thead_clk_light_gate("clkgen_iopmp_dpu_aclk", NULL,
  48. gate_base + 0x50, 28);
  49. gates[LIGHT_CLKGEN_IOPMP_DPU1_ACLK] = thead_clk_light_gate("clkgen_iopmp_dpu1_aclk", NULL,
  50. gate_base + 0x50, 27);
  51. gates[LIGHT_CLKGEN_X2H_DPU_ACLK] = thead_clk_light_gate("clkgen_x2h_dpu_aclk", NULL, gate_base + 0x50, 21);
  52. gates[LIGHT_CLKGEN_X2H_DPU1_ACLK] = thead_clk_light_gate("clkgen_x2h_dpu1_aclk", NULL, gate_base + 0x50, 20);
  53. gates[LIGHT_CLKGEN_MIPIDSI0_PIXCLK] = thead_clk_light_gate("clkgen_mipidsi0_pixclk", NULL, gate_base + 0x50, 30);
  54. gates[LIGHT_CLKGEN_HDMI_PIXCLK] = thead_clk_light_gate("clkgen_hdmi_pixclk", NULL, gate_base + 0x54, 0);
  55. gates[LIGHT_CLKGEN_MIPIDSI1_PIXCLK] = thead_clk_light_gate("clkgen_mipidsi1_pixclk", NULL, gate_base + 0x50, 31);
  56. gates[LIGHT_CLKGEN_HDMI_SFR_CLK] = thead_clk_light_gate("clkgen_hdmi_sfr_clk", NULL, gate_base + 0x50, 10);
  57. gates[LIGHT_CLKGEN_HDMI_CEC_CLK] = thead_clk_light_gate("clkgen_hdmi_cec_cclk", NULL, gate_base + 0x50, 12);
  58. gates[LIGHT_CLKGEN_HDMI_I2S_CLK] = thead_clk_light_gate("clkgen_hdmi_i2s_clk", NULL, gate_base + 0x50, 19);
  59. gates[LIGHT_CLKGEN_MIPIDSI0_CFG_CLK] = thead_clk_light_gate("clkgen_mipidsi0_cfg_clk", NULL, gate_base + 0x50, 15);
  60. gates[LIGHT_CLKGEN_MIPIDSI1_CFG_CLK] = thead_clk_light_gate("clkgen_mipidsi1_cfg_clk", NULL, gate_base + 0x50, 16);
  61. gates[LIGHT_CLKGEN_MIPIDSI0_REFCLK] = thead_clk_light_gate("clkgen_mipidsi0_refclk", NULL, gate_base + 0x50, 17);
  62. gates[LIGHT_CLKGEN_MIPIDSI1_REFCLK] = thead_clk_light_gate("clkgen_mipidsi1_refclk", NULL, gate_base + 0x50, 18);
  63. gates[LIGHT_CLKGEN_GPU_CORE_CLK] = thead_clk_light_gate("clkgen_gpu_core_clk", NULL, gate_base + 0x50, 3);
  64. gates[LIGHT_CLKGEN_GPU_CFG_ACLK] = thead_clk_light_gate("clkgen_gpu_cfg_aclk", NULL, gate_base + 0x50, 4);
  65. gates[LIGHT_CLKGEN_DPU_HCLK] = thead_clk_light_gate("clkgen_dpu_hclk", NULL, gate_base + 0x50, 7);
  66. gates[LIGHT_CLKGEN_DPU_ACLK] = thead_clk_light_gate("clkgen_dpu_aclk", NULL, gate_base + 0x50, 8);
  67. gates[LIGHT_CLKGEN_DPU_CCLK] = thead_clk_light_gate("clkgen_dpu_cclk", NULL, gate_base + 0x50, 9);
  68. gates[LIGHT_CLKGEN_DPU_PIXCLK0] = thead_clk_light_gate("clkgen_dpu_pixclk0", NULL, gate_base + 0x50, 5);
  69. gates[LIGHT_CLKGEN_DPU_PIXCLK1] = thead_clk_light_gate("clkgen_dpu_pixclk1", NULL, gate_base + 0x50, 6);
  70. clk_gate_data.clks = gates;
  71. clk_gate_data.clk_num = ARRAY_SIZE(gates);
  72. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
  73. if (ret < 0) {
  74. dev_err(dev, "failed to register gate clks for light vosys\n");
  75. goto unregister_clks;
  76. }
  77. dev_info(dev, "succeed to register vosys gate clock provider\n");
  78. return 0;
  79. unregister_clks:
  80. thead_unregister_clocks(gates, ARRAY_SIZE(gates));
  81. return ret;
  82. }
  83. static const struct of_device_id vosys_clk_gate_of_match[] = {
  84. { .compatible = "thead,vosys-gate-controller" },
  85. { /* sentinel */ },
  86. };
  87. MODULE_DEVICE_TABLE(of, vosys_clk_gate_of_match);
  88. static struct platform_driver light_vosys_clk_driver = {
  89. .probe = light_vosys_clk_probe,
  90. .driver = {
  91. .name = "vosys-clk-gate-provider",
  92. .of_match_table = of_match_ptr(vosys_clk_gate_of_match),
  93. },
  94. };
  95. module_platform_driver(light_vosys_clk_driver);
  96. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  97. MODULE_DESCRIPTION("Thead Light Fullmask vosys clock gate provider");
  98. MODULE_LICENSE("GPL v2");