visys-gate.c 6.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2022 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/clock/light-fm-ap-clock.h>
  6. #include <dt-bindings/clock/light-visys.h>
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/types.h>
  17. #include "clk-gate.h"
  18. #include "../clk.h"
  19. static struct clk *gates[LIGHT_CLKGEN_VISYS_CLK_END];
  20. static struct clk_onecell_data clk_gate_data;
  21. static u32 share_cnt_isp0_hclk_en;
  22. static u32 share_cnt_isp0_aclk_en;
  23. static int light_visys_clk_probe(struct platform_device *pdev)
  24. {
  25. struct regmap *visys_regmap;
  26. struct device *dev = &pdev->dev;
  27. struct device_node *np = dev->of_node;
  28. int ret;
  29. visys_regmap = syscon_regmap_lookup_by_phandle(np, "visys-regmap");
  30. if (IS_ERR(visys_regmap)) {
  31. dev_err(&pdev->dev, "cannot find regmap for vi system register\n");
  32. return PTR_ERR(visys_regmap);
  33. }
  34. /* we assume that the gate clock is a root clock */
  35. gates[LIGHT_CLKGEN_DW200_ACLK] = thead_gate_clk_register("clkgen_dw200_aclk", NULL,
  36. visys_regmap, 0xa0, 27, GATE_NOT_SHARED, NULL, dev);
  37. gates[LIGHT_CLKGEN_AXI4_VISYS1_ACLK] = thead_gate_clk_register("clkgen_axi4_visys1_aclk", NULL,
  38. visys_regmap, 0xa0, 26, GATE_NOT_SHARED, NULL, dev);
  39. gates[LIGHT_CLKGEN_AXI4_VISYS2_ACLK] = thead_gate_clk_register("clkgen_axi4_visys2_aclk", NULL,
  40. visys_regmap, 0xa0, 25, GATE_NOT_SHARED, NULL, dev);
  41. gates[LIGHT_CLKGEN_AXI4_VISYS3_ACLK] = thead_gate_clk_register("clkgen_axi4_visys3_aclk", NULL,
  42. visys_regmap, 0xa0, 24, GATE_NOT_SHARED, NULL, dev);
  43. gates[LIGHT_CLKGEN_ISP_RY_ACLK] = thead_gate_clk_register("clkgen_isp_ry_aclk", NULL,
  44. visys_regmap, 0xa0, 22, GATE_NOT_SHARED, NULL, dev);
  45. gates[LIGHT_CLKGEN_ISP_VENC_SHAKE_ACLK] = thead_gate_clk_register("clkgen_isp_venc_shake_aclk", NULL,
  46. visys_regmap, 0xa0, 30, GATE_NOT_SHARED, NULL, dev);
  47. gates[LIGHT_CLKGEN_VIPRE_ACLK] = thead_gate_clk_register("clkgen_vipre_aclk", NULL,
  48. visys_regmap, 0xa0, 31, GATE_NOT_SHARED, NULL, dev);
  49. gates[LIGHT_CLKGEN_DW200_HCLK] = thead_gate_clk_register("clkgen_dw200_hclk", NULL,
  50. visys_regmap, 0xa0, 13, GATE_NOT_SHARED, NULL, dev);
  51. gates[LIGHT_CLKGEN_ISP_RY_HCLK] = thead_gate_clk_register("clkgen_isp_ry_hclk", NULL,
  52. visys_regmap, 0xa0, 12, GATE_NOT_SHARED, NULL, dev);
  53. gates[LIGHT_CLKGEN_MIPI_CSI0_PCLK] = thead_gate_clk_register("clkgen_mipi_csi0_pclk", NULL,
  54. visys_regmap, 0xa0, 18, GATE_NOT_SHARED, NULL, dev);
  55. gates[LIGHT_CLKGEN_MIPI_CSI1_PCLK] = thead_gate_clk_register("clkgen_mipi_csi1_pclk", NULL,
  56. visys_regmap, 0xa0, 17, GATE_NOT_SHARED, NULL, dev);
  57. gates[LIGHT_CLKGEN_MIPI_CSI2_PCLK] = thead_gate_clk_register("clkgen_mipi_csi2_pclk", NULL,
  58. visys_regmap, 0xa0, 16, GATE_NOT_SHARED, NULL, dev);
  59. gates[LIGHT_CLKGEN_VIPRE_PCLK] = thead_gate_clk_register("clkgen_vipre_pclk", NULL,
  60. visys_regmap, 0xa0, 15, GATE_NOT_SHARED, NULL, dev);
  61. gates[LIGHT_CLKGEN_ISP_VENC_SHAKE_PCLK] = thead_gate_clk_register("clkgen_isp_venc_shake_pclk", NULL,
  62. visys_regmap, 0xa0, 29, GATE_NOT_SHARED, NULL, dev);
  63. gates[LIGHT_CLKGEN_MIPI_CSI0_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi0_pixclk", NULL,
  64. visys_regmap, 0xa0, 11, GATE_NOT_SHARED, NULL, dev);
  65. gates[LIGHT_CLKGEN_MIPI_CSI1_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi1_pixclk", NULL,
  66. visys_regmap, 0xa0, 10, GATE_NOT_SHARED, NULL, dev);
  67. gates[LIGHT_CLKGEN_MIPI_CSI2_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi2_pixclk", NULL,
  68. visys_regmap, 0xa0, 9, GATE_NOT_SHARED, NULL, dev);
  69. gates[LIGHT_CLKGEN_VIPRE_PIXELCLK] = thead_gate_clk_register("clkgen_vipre_pixelclk", NULL,
  70. visys_regmap, 0xa4, 23, GATE_NOT_SHARED, NULL, dev);
  71. gates[LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi0_cfg_clk", NULL,
  72. visys_regmap, 0xa0, 8, GATE_NOT_SHARED, NULL, dev);
  73. gates[LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi1_cfg_clk", NULL,
  74. visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
  75. gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
  76. visys_regmap, 0xa0, 6, GATE_NOT_SHARED, NULL, dev);
  77. gates[LIGHT_CLKGEN_DW200_CLK_VSE] = thead_gate_clk_register("clkgen_dw200_clk_vse", NULL,
  78. visys_regmap, 0xa0, 5, GATE_NOT_SHARED, NULL, dev);
  79. gates[LIGHT_CLKGEN_DW200_CLK_DWE] = thead_gate_clk_register("clkgen_dw200_clk_dwe", NULL,
  80. visys_regmap, 0xa0, 4, GATE_NOT_SHARED, NULL, dev);
  81. gates[LIGHT_CLKGEN_ISP0_CLK] = thead_gate_clk_register("clkgen_isp_clk_0", NULL,
  82. visys_regmap, 0xa4, 31, GATE_NOT_SHARED, NULL, dev);
  83. gates[LIGHT_CLKGEN_ISP1_CLK] = thead_gate_clk_register("clkgen_isp_clk_1", NULL,
  84. visys_regmap, 0xa4, 30, GATE_NOT_SHARED, NULL, dev);
  85. gates[LIGHT_CLKGEN_ISP_RY_CCLK] = thead_gate_clk_register("clkgen_isp_ry_cclk", NULL,
  86. visys_regmap, 0xa0, 21, GATE_NOT_SHARED, NULL, dev);
  87. gates[LIGHT_CLKGEN_ISP1_PIXELCLK] = thead_gate_clk_register("clkgen_isp1_pixelclk", NULL,
  88. visys_regmap, 0xa4, 28, GATE_NOT_SHARED, NULL, dev);
  89. gates[LIGHT_CLKGEN_ISP0_PIXELCLK] = thead_gate_clk_register("clkgen_isp0_pixelclk", NULL,
  90. visys_regmap, 0xa4, 29, GATE_NOT_SHARED, NULL, dev);
  91. gates[LIGHT_CLKGEN_ISP1_HCLK] = thead_gate_clk_register("clkgen_isp1_hclk", NULL,
  92. visys_regmap, 0xa0, 1, GATE_SHARED, &share_cnt_isp0_hclk_en, dev);
  93. gates[LIGHT_CLKGEN_ISP0_HCLK] = thead_gate_clk_register("clkgen_isp0_hclk", NULL,
  94. visys_regmap, 0xa0, 1, GATE_SHARED, &share_cnt_isp0_hclk_en, dev);
  95. gates[LIGHT_CLKGEN_ISP1_ACLK] = thead_gate_clk_register("clkgen_isp1_aclk", NULL,
  96. visys_regmap, 0xa0, 3, GATE_SHARED, &share_cnt_isp0_aclk_en, dev);
  97. gates[LIGHT_CLKGEN_ISP0_ACLK] = thead_gate_clk_register("clkgen_isp0_aclk", NULL,
  98. visys_regmap, 0xa0, 3, GATE_SHARED, &share_cnt_isp0_aclk_en, dev);
  99. clk_gate_data.clks = gates;
  100. clk_gate_data.clk_num = ARRAY_SIZE(gates);
  101. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
  102. if (ret < 0) {
  103. dev_err(dev, "failed to register gate clks for light visys\n");
  104. goto unregister_clks;
  105. }
  106. dev_info(dev, "succeed to register visys gate clock provider\n");
  107. return 0;
  108. unregister_clks:
  109. thead_unregister_clocks(gates, ARRAY_SIZE(gates));
  110. return ret;
  111. }
  112. static const struct of_device_id visys_clk_gate_of_match[] = {
  113. { .compatible = "thead,visys-gate-controller" },
  114. { /* sentinel */ },
  115. };
  116. MODULE_DEVICE_TABLE(of, visys_clk_gate_of_match);
  117. static struct platform_driver light_visys_clk_driver = {
  118. .probe = light_visys_clk_probe,
  119. .driver = {
  120. .name = "visys-clk-gate-provider",
  121. .of_match_table = of_match_ptr(visys_clk_gate_of_match),
  122. },
  123. };
  124. module_platform_driver(light_visys_clk_driver);
  125. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  126. MODULE_DESCRIPTION("Thead Light Fullmask visys clock gate provider");
  127. MODULE_LICENSE("GPL v2");