clk.h 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #ifndef __MACH_THEAD_CLK_H
  6. #define __MACH_THEAD_CLK_H
  7. #include <linux/spinlock.h>
  8. #include <linux/clk-provider.h>
  9. extern spinlock_t thead_light_clk_lock;
  10. #define LIGHT_PLL_RATE(_vco, _rate, _r, _b, _f, _p, _k) \
  11. { \
  12. .vco_rate = (_vco), \
  13. .rate = (_rate), \
  14. .refdiv = (_r), \
  15. .fbdiv = (_b), \
  16. .frac = (_f), \
  17. .postdiv1 = (_p), \
  18. .postdiv2 = (_k), \
  19. }
  20. enum light_pll_outtype {
  21. LIGHT_PLL_VCO,
  22. LIGHT_PLL_DIV,
  23. };
  24. enum light_div_type {
  25. MUX_TYPE_DIV,
  26. MUX_TYPE_CDE,
  27. };
  28. enum light_pll_clktype {
  29. LIGHT_AUDIO_PLL,
  30. LIGHT_SYS_PLL,
  31. LIGHT_CPU_PLL0,
  32. LIGHT_CPU_PLL1,
  33. LIGHT_GMAC_PLL,
  34. LIGHT_VIDEO_PLL,
  35. LIGHT_DDR_PLL,
  36. LIGHT_DPU0_PLL,
  37. LIGHT_DPU1_PLL,
  38. };
  39. struct light_pll_rate_table {
  40. unsigned long vco_rate;
  41. unsigned long rate;
  42. unsigned int refdiv;
  43. unsigned int fbdiv;
  44. unsigned int frac;
  45. unsigned int postdiv1;
  46. unsigned int postdiv2;
  47. };
  48. struct light_pll_clk {
  49. enum light_pll_outtype out_type;
  50. enum light_pll_clktype clk_type;
  51. const struct light_pll_rate_table *rate_table;
  52. int rate_count;
  53. int flags;
  54. };
  55. static inline struct clk *thead_light_clk_fixed_factor(const char *name,
  56. const char *parent, unsigned int mult, unsigned int div)
  57. {
  58. return clk_register_fixed_factor(NULL, name, parent,
  59. CLK_SET_RATE_PARENT, mult, div);
  60. }
  61. struct clk *thead_light_pll(const char *name, const char *parent_name,
  62. void __iomem *base,
  63. const struct light_pll_clk *pll_clk);
  64. static inline struct clk *thead_clk_light_gate(const char *name, const char *parent,
  65. void __iomem *reg, u8 shift)
  66. {
  67. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  68. shift, 0, &thead_light_clk_lock);
  69. }
  70. struct clk *thead_clk_light_register_gate_shared(const char *name, const char *parent,
  71. unsigned long flags, void __iomem *reg,
  72. u8 shift, spinlock_t *lock,
  73. unsigned int *share_count);
  74. struct clk *thead_clk_light_divider(const char *name, const char *parent,
  75. void __iomem *reg, u8 shift, u8 width,
  76. u8 sync, enum light_div_type div_type,
  77. u16 min, u16 max);
  78. void thead_unregister_clocks(struct clk *clks[], unsigned int count);
  79. static inline struct clk *thead_clk_fixed(const char *name, unsigned long rate)
  80. {
  81. return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  82. }
  83. static inline struct clk *thead_clk_light_gate_shared(const char *name, const char *parent,
  84. void __iomem *reg, u8 shift,
  85. unsigned int *share_count)
  86. {
  87. return thead_clk_light_register_gate_shared(name, parent, CLK_SET_RATE_PARENT, reg,
  88. shift, &thead_light_clk_lock, share_count);
  89. }
  90. static inline struct clk *thead_light_clk_mux_flags(const char *name,
  91. void __iomem *reg, u8 shift, u8 width,
  92. const char * const *parents, int num_parents,
  93. unsigned long flags)
  94. {
  95. return clk_register_mux(NULL, name, parents, num_parents,
  96. flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
  97. &thead_light_clk_lock);
  98. }
  99. #endif