clk.c 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/of.h>
  11. #include <linux/slab.h>
  12. #include <linux/spinlock.h>
  13. #include "clk.h"
  14. #define LIGHT_PLL_CFG0 0x0
  15. #define LIGHT_PLL_CFG1 0x04
  16. #define LIGHT_PLL_CFG2 0x8
  17. #define LIGHT_POSTDIV2_SHIFT 24
  18. #define LIGHT_POSTDIV2_MASK GENMASK(26, 24)
  19. #define LIGHT_POSTDIV1_SHIFT 20
  20. #define LIGHT_POSTDIV1_MASK GENMASK(22, 20)
  21. #define LIGHT_FBDIV_SHIFT 8
  22. #define LIGHT_FBDIV_MASK GENMASK(19, 8)
  23. #define LIGHT_REFDIV_SHIFT 0
  24. #define LIGHT_REFDIV_MASK GENMASK(5, 0)
  25. #define LIGHT_BYPASS_MASK BIT(30)
  26. #define LIGHT_RST_MASK BIT(29)
  27. #define LIGHT_DSMPD_MASK BIT(24)
  28. #define LIGHT_DACPD_MASK BIT(25)
  29. #define LIGHT_FRAC_MASK GENMASK(23, 0)
  30. #define LIGHT_FRAC_SHIFT 0
  31. #define LIGHT_FRAC_DIV BIT(24)
  32. #define LOCK_TIMEOUT_US 10000
  33. #define div_mask(d) ((1 << (d->width)) - 1)
  34. DEFINE_SPINLOCK(thead_light_clk_lock);
  35. enum light_pll_mode {
  36. PLL_MODE_FRAC,
  37. PLL_MODE_INT,
  38. };
  39. struct clk_lightpll {
  40. struct clk_hw hw;
  41. void __iomem *base;
  42. enum light_pll_clktype clk_type;
  43. enum light_pll_outtype out_type;
  44. enum light_pll_mode pll_mode;
  45. const struct light_pll_rate_table *rate_table;
  46. int rate_count;
  47. u32 cfg0_reg_off;
  48. u32 pll_sts_off;
  49. int pll_lock_bit;
  50. /* Light MPW Aon/ddr pll define bypass:rst bits as: 31:30
  51. * but AP pll define bypass:rst bits as: 30:29
  52. *
  53. * Light Fullmask align these register field define, all pll
  54. * define bypss:rst bits as: 30:29
  55. */
  56. int pll_rst_bit;
  57. int pll_bypass_bit;
  58. };
  59. struct clk_lightdiv {
  60. struct clk_divider divider;
  61. enum light_div_type div_type;
  62. u16 min_div;
  63. u16 max_div;
  64. u8 sync_en;
  65. const struct clk_ops *ops;
  66. };
  67. struct clk_lightgate {
  68. struct clk_gate gate;
  69. unsigned int *share_count;
  70. const struct clk_ops *ops;
  71. };
  72. #define to_clk_lightpll(_hw) container_of(_hw, struct clk_lightpll, hw)
  73. void thead_unregister_clocks(struct clk *clks[], unsigned int count)
  74. {
  75. unsigned int i;
  76. for (i = 0; i < count; i++)
  77. clk_unregister(clks[i]);
  78. }
  79. static void clk_light_pll_cfg_init(struct clk_lightpll *pll)
  80. {
  81. switch (pll->clk_type) {
  82. case LIGHT_AUDIO_PLL:
  83. pll->cfg0_reg_off = 0x0;
  84. pll->pll_sts_off = 0x90;
  85. pll->pll_lock_bit = BIT(0);
  86. pll->pll_bypass_bit = BIT(31);
  87. pll->pll_rst_bit = BIT(30);
  88. pll->pll_mode = PLL_MODE_FRAC;
  89. break;
  90. case LIGHT_SYS_PLL:
  91. pll->cfg0_reg_off = 0x10;
  92. pll->pll_sts_off = 0x90;
  93. pll->pll_lock_bit = BIT(1);
  94. pll->pll_bypass_bit = BIT(31);
  95. pll->pll_rst_bit = BIT(30);
  96. pll->pll_mode = PLL_MODE_FRAC;
  97. break;
  98. case LIGHT_CPU_PLL0:
  99. pll->cfg0_reg_off = 0x0;
  100. pll->pll_sts_off = 0x80;
  101. pll->pll_lock_bit = BIT(1);
  102. pll->pll_bypass_bit = BIT(30);
  103. pll->pll_rst_bit = BIT(29);
  104. pll->pll_mode = PLL_MODE_INT;
  105. break;
  106. case LIGHT_CPU_PLL1:
  107. pll->cfg0_reg_off = 0x10;
  108. pll->pll_sts_off = 0x80;
  109. pll->pll_lock_bit = BIT(4);
  110. pll->pll_bypass_bit = BIT(30);
  111. pll->pll_rst_bit = BIT(29);
  112. pll->pll_mode = PLL_MODE_INT;
  113. break;
  114. case LIGHT_GMAC_PLL:
  115. pll->cfg0_reg_off = 0x20;
  116. pll->pll_sts_off = 0x80;
  117. pll->pll_lock_bit = BIT(3);
  118. pll->pll_bypass_bit = BIT(30);
  119. pll->pll_rst_bit = BIT(29);
  120. pll->pll_mode = PLL_MODE_INT;
  121. break;
  122. case LIGHT_VIDEO_PLL:
  123. pll->cfg0_reg_off = 0x30;
  124. pll->pll_sts_off = 0x80;
  125. pll->pll_lock_bit = BIT(7);
  126. pll->pll_bypass_bit = BIT(30);
  127. pll->pll_rst_bit = BIT(29);
  128. pll->pll_mode = PLL_MODE_INT;
  129. break;
  130. case LIGHT_DDR_PLL:
  131. pll->cfg0_reg_off = 0x8;
  132. pll->pll_sts_off = 0x18;
  133. pll->pll_lock_bit = BIT(0);
  134. pll->pll_bypass_bit = BIT(31);
  135. pll->pll_rst_bit = BIT(30);
  136. pll->pll_mode = PLL_MODE_INT;
  137. break;
  138. case LIGHT_DPU0_PLL:
  139. pll->cfg0_reg_off = 0x40;
  140. pll->pll_sts_off = 0x80;
  141. pll->pll_lock_bit = BIT(8);
  142. pll->pll_bypass_bit = BIT(30);
  143. pll->pll_rst_bit = BIT(29);
  144. pll->pll_mode = PLL_MODE_INT;
  145. break;
  146. case LIGHT_DPU1_PLL:
  147. pll->cfg0_reg_off = 0x50;
  148. pll->pll_sts_off = 0x80;
  149. pll->pll_lock_bit = BIT(9);
  150. pll->pll_bypass_bit = BIT(30);
  151. pll->pll_rst_bit = BIT(29);
  152. pll->pll_mode = PLL_MODE_INT;
  153. break;
  154. default:
  155. pr_err("%s: Unknown pll type\n", __func__);
  156. };
  157. }
  158. static int clk_light_pll_wait_lock(struct clk_lightpll *pll)
  159. {
  160. u32 val;
  161. return readl_poll_timeout(pll->base + pll->pll_sts_off, val,
  162. val & pll->pll_lock_bit, 0,
  163. LOCK_TIMEOUT_US);
  164. }
  165. static int clk_light_pll_prepare(struct clk_hw *hw)
  166. {
  167. struct clk_lightpll *pll = to_clk_lightpll(hw);
  168. void __iomem *cfg1_off;
  169. u32 val;
  170. int ret;
  171. cfg1_off = pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1;
  172. val = readl_relaxed(cfg1_off);
  173. if (!(val & pll->pll_rst_bit))
  174. return 0;
  175. /* Enable RST */
  176. val |= pll->pll_rst_bit;
  177. writel_relaxed(val, cfg1_off);
  178. udelay(3);
  179. /* Disable RST */
  180. val &= ~pll->pll_rst_bit;
  181. writel_relaxed(val, cfg1_off);
  182. ret = clk_light_pll_wait_lock(pll);
  183. if (ret)
  184. return ret;
  185. return 0;
  186. }
  187. static int clk_light_pll_is_prepared(struct clk_hw *hw)
  188. {
  189. struct clk_lightpll *pll = to_clk_lightpll(hw);
  190. u32 val;
  191. val = readl_relaxed(pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  192. return (val & pll->pll_rst_bit) ? 0 : 1;
  193. }
  194. static void clk_light_pll_unprepare(struct clk_hw *hw)
  195. {
  196. struct clk_lightpll *pll = to_clk_lightpll(hw);
  197. u32 val;
  198. val = readl_relaxed(pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  199. val |= pll->pll_rst_bit;
  200. writel_relaxed(val, pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  201. }
  202. static unsigned long clk_light_pll_recalc_rate(struct clk_hw *hw,
  203. unsigned long parent_rate)
  204. {
  205. #ifndef CONFIG_LIGHT_CLK_EMU
  206. struct clk_lightpll *pll = to_clk_lightpll(hw);
  207. u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
  208. u32 pll_cfg0, pll_cfg1;
  209. u64 fvco = 0;
  210. pll_cfg0 = readl_relaxed(pll->base + pll->cfg0_reg_off);
  211. pll_cfg1 = readl_relaxed(pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  212. refdiv = (pll_cfg0 & LIGHT_REFDIV_MASK) >> LIGHT_REFDIV_SHIFT;
  213. fbdiv = (pll_cfg0 & LIGHT_FBDIV_MASK) >> LIGHT_FBDIV_SHIFT;
  214. postdiv1 = (pll_cfg0 & LIGHT_POSTDIV1_MASK) >> LIGHT_POSTDIV1_SHIFT;
  215. postdiv2 = (pll_cfg0 & LIGHT_POSTDIV2_MASK) >> LIGHT_POSTDIV2_SHIFT;
  216. frac = (pll_cfg1 & LIGHT_FRAC_MASK) >> LIGHT_FRAC_SHIFT;
  217. /* rate calculation:
  218. * INT mode: FOUTVCO = FREE * FBDIV / REFDIV
  219. * FRAC mode:FOUTVCO = (FREE * FBDIV + FREE * FRAC/BIT(24)) / REFDIV
  220. */
  221. if (pll->pll_mode == PLL_MODE_FRAC)
  222. fvco = (parent_rate * frac) / LIGHT_FRAC_DIV;
  223. fvco += (parent_rate * fbdiv);
  224. do_div(fvco, refdiv);
  225. if (pll->out_type == LIGHT_PLL_DIV)
  226. do_div(fvco, postdiv1 * postdiv2);
  227. return fvco;
  228. #else
  229. struct clk_lightpll *pll = to_clk_lightpll(hw);
  230. const struct light_pll_rate_table *rate_table = pll->rate_table;
  231. /* return minimum supported value */
  232. if (pll->out_type == LIGHT_PLL_DIV)
  233. return rate_table[0].rate;
  234. return rate_table[0].vco_rate;
  235. #endif
  236. }
  237. static const struct light_pll_rate_table *light_get_pll_div_settings(
  238. struct clk_lightpll *pll, unsigned long rate)
  239. {
  240. const struct light_pll_rate_table *rate_table = pll->rate_table;
  241. int i;
  242. for (i = 0; i < pll->rate_count; i++)
  243. if (rate == rate_table[i].rate)
  244. return &rate_table[i];
  245. return NULL;
  246. }
  247. static const struct light_pll_rate_table *light_get_pll_vco_settings(
  248. struct clk_lightpll *pll, unsigned long rate)
  249. {
  250. const struct light_pll_rate_table *rate_table = pll->rate_table;
  251. int i;
  252. for (i = 0; i < pll->rate_count; i++)
  253. if (rate == rate_table[i].vco_rate)
  254. return &rate_table[i];
  255. return NULL;
  256. }
  257. static inline bool clk_light_pll_change(struct clk_lightpll *pll,
  258. const struct light_pll_rate_table *rate)
  259. {
  260. u32 refdiv_old, fbdiv_old, postdiv1_old, postdiv2_old, frac_old;
  261. u32 cfg0, cfg1;
  262. bool pll_changed;
  263. cfg0 = readl_relaxed(pll->base + pll->cfg0_reg_off);
  264. cfg1 = readl_relaxed(pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  265. refdiv_old = (cfg0 & LIGHT_REFDIV_MASK) >> LIGHT_REFDIV_SHIFT;
  266. fbdiv_old = (cfg0 & LIGHT_FBDIV_MASK) >> LIGHT_FBDIV_SHIFT;
  267. postdiv1_old = (cfg0 & LIGHT_POSTDIV1_MASK) >> LIGHT_POSTDIV1_SHIFT;
  268. postdiv2_old = (cfg0 & LIGHT_POSTDIV2_MASK) >> LIGHT_POSTDIV2_SHIFT;
  269. frac_old = (cfg1 & LIGHT_FRAC_MASK) >> LIGHT_FRAC_SHIFT;
  270. pll_changed = rate->refdiv != refdiv_old || rate->fbdiv != fbdiv_old ||
  271. rate->postdiv1 != postdiv1_old || rate->postdiv2 != postdiv2_old;
  272. if (pll->pll_mode == PLL_MODE_FRAC)
  273. pll_changed |= (rate->frac != frac_old);
  274. return pll_changed;
  275. }
  276. static int clk_light_pll_set_rate(struct clk_hw *hw, unsigned long drate,
  277. unsigned long prate)
  278. {
  279. struct clk_lightpll *pll = to_clk_lightpll(hw);
  280. const struct light_pll_rate_table *rate;
  281. void __iomem *cfg1_off;
  282. u32 tmp, div_val;
  283. int ret;
  284. if (pll->out_type == LIGHT_PLL_VCO) {
  285. rate = light_get_pll_vco_settings(pll, drate);
  286. if (!rate) {
  287. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  288. drate, clk_hw_get_name(hw));
  289. return -EINVAL;
  290. }
  291. } else {
  292. rate = light_get_pll_div_settings(pll, drate);
  293. if (!rate) {
  294. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  295. drate, clk_hw_get_name(hw));
  296. return -EINVAL;
  297. }
  298. }
  299. if (!clk_light_pll_change(pll, rate))
  300. return 0;
  301. /* Enable RST */
  302. cfg1_off = pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1;
  303. tmp = readl_relaxed(cfg1_off);
  304. tmp |= pll->pll_rst_bit;
  305. writel_relaxed(tmp, cfg1_off);
  306. div_val = (rate->refdiv << LIGHT_REFDIV_SHIFT) |
  307. (rate->fbdiv << LIGHT_FBDIV_SHIFT) |
  308. (rate->postdiv1 << LIGHT_POSTDIV1_SHIFT) |
  309. (rate->postdiv2 << LIGHT_POSTDIV2_SHIFT);
  310. writel_relaxed(div_val, pll->base + pll->cfg0_reg_off);
  311. if (pll->pll_mode == PLL_MODE_FRAC) {
  312. tmp &= ~(LIGHT_FRAC_MASK << LIGHT_FRAC_SHIFT);
  313. tmp |= rate->frac;
  314. writel_relaxed(tmp, cfg1_off);
  315. }
  316. udelay(3);
  317. /* Disable RST */
  318. tmp &= ~pll->pll_rst_bit;
  319. writel_relaxed(tmp, cfg1_off);
  320. /* Wait Lock, ~20us cost */
  321. ret = clk_light_pll_wait_lock(pll);
  322. if (ret)
  323. return ret;
  324. /* HW requires 30us for pll stable */
  325. udelay(30);
  326. return 0;
  327. }
  328. static long clk_light_pllvco_round_rate(struct clk_hw *hw, unsigned long rate,
  329. unsigned long *prate)
  330. {
  331. struct clk_lightpll *pll = to_clk_lightpll(hw);
  332. const struct light_pll_rate_table *rate_table = pll->rate_table;
  333. unsigned long best = 0, now = 0;
  334. unsigned int i, best_i = 0;
  335. for (i = 0; i < pll->rate_count; i++) {
  336. now = rate_table[i].vco_rate;
  337. if (rate == now) {
  338. return rate_table[i].vco_rate;
  339. } else if (abs(now - rate) < abs(best - rate)) {
  340. best = now;
  341. best_i = i;
  342. }
  343. }
  344. /* return minimum supported value */
  345. return rate_table[best_i].vco_rate;
  346. }
  347. static long clk_light_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
  348. unsigned long *prate)
  349. {
  350. struct clk_lightpll *pll = to_clk_lightpll(hw);
  351. const struct light_pll_rate_table *rate_table = pll->rate_table;
  352. unsigned long best = 0, now = 0;
  353. unsigned int i, best_i = 0;
  354. for (i = 0; i < pll->rate_count; i++) {
  355. now = rate_table[i].rate;
  356. if (rate == now) {
  357. return rate_table[i].rate;
  358. } else if (abs(now - rate) < abs(best - rate)) {
  359. best = now;
  360. best_i = i;
  361. }
  362. }
  363. /* return minimum supported value */
  364. return rate_table[best_i].rate;
  365. }
  366. static const struct clk_ops clk_light_pll_def_ops = {
  367. .recalc_rate = clk_light_pll_recalc_rate,
  368. };
  369. static const struct clk_ops clk_light_pllvco_ops = {
  370. .prepare = clk_light_pll_prepare,
  371. .unprepare = clk_light_pll_unprepare,
  372. .is_prepared = clk_light_pll_is_prepared,
  373. .recalc_rate = clk_light_pll_recalc_rate,
  374. .round_rate = clk_light_pllvco_round_rate,
  375. .set_rate = clk_light_pll_set_rate,
  376. };
  377. static const struct clk_ops clk_light_plldiv_ops = {
  378. .prepare = clk_light_pll_prepare,
  379. .unprepare = clk_light_pll_unprepare,
  380. .is_prepared = clk_light_pll_is_prepared,
  381. .recalc_rate = clk_light_pll_recalc_rate,
  382. .round_rate = clk_light_plldiv_round_rate,
  383. .set_rate = clk_light_pll_set_rate,
  384. };
  385. struct clk *thead_light_pll(const char *name, const char *parent_name,
  386. void __iomem *base,
  387. const struct light_pll_clk *pll_clk)
  388. {
  389. struct clk_lightpll *pll;
  390. struct clk *clk;
  391. struct clk_init_data init;
  392. u32 val;
  393. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  394. if (!pll)
  395. return ERR_PTR(-ENOMEM);
  396. init.name = name;
  397. init.flags = pll_clk->flags;
  398. init.parent_names = &parent_name;
  399. init.num_parents = 1;
  400. switch (pll_clk->out_type) {
  401. case LIGHT_PLL_VCO:
  402. if (pll_clk->rate_table)
  403. init.ops = &clk_light_pllvco_ops;
  404. break;
  405. case LIGHT_PLL_DIV:
  406. if (pll_clk->rate_table)
  407. init.ops = &clk_light_plldiv_ops;
  408. break;
  409. default:
  410. pr_err("%s: Unknown pll out type for pll clk %s\n",
  411. __func__, name);
  412. };
  413. if (!pll_clk->rate_table)
  414. init.ops = &clk_light_pll_def_ops;
  415. pll->base = base;
  416. pll->hw.init = &init;
  417. pll->out_type = pll_clk->out_type;
  418. pll->clk_type = pll_clk->clk_type;
  419. pll->rate_table = pll_clk->rate_table;
  420. pll->rate_count = pll_clk->rate_count;
  421. clk_light_pll_cfg_init(pll);
  422. val = readl_relaxed(pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  423. val &= ~pll->pll_bypass_bit;
  424. val |= LIGHT_DACPD_MASK;
  425. val |= LIGHT_DSMPD_MASK;
  426. if (pll->pll_mode == PLL_MODE_FRAC) {
  427. val &= ~LIGHT_DSMPD_MASK;
  428. val &= ~LIGHT_DACPD_MASK;
  429. }
  430. writel_relaxed(val, pll->base + pll->cfg0_reg_off + LIGHT_PLL_CFG1);
  431. clk = clk_register(NULL, &pll->hw);
  432. if (IS_ERR(clk)) {
  433. pr_err("%s: failed to register pll %s %lu\n",
  434. __func__, name, PTR_ERR(clk));
  435. kfree(pll);
  436. }
  437. return clk;
  438. }
  439. static inline struct clk_lightdiv *to_clk_lightdiv(struct clk_hw *hw)
  440. {
  441. struct clk_divider *divider = to_clk_divider(hw);
  442. return container_of(divider, struct clk_lightdiv, divider);
  443. }
  444. static unsigned long clk_lightdiv_recalc_rate(struct clk_hw *hw,
  445. unsigned long parent_rate)
  446. {
  447. struct clk_lightdiv *light_div = to_clk_lightdiv(hw);
  448. return light_div->ops->recalc_rate(&light_div->divider.hw, parent_rate);
  449. }
  450. static long clk_lightdiv_round_rate(struct clk_hw *hw, unsigned long rate,
  451. unsigned long *prate)
  452. {
  453. struct clk_lightdiv *light_div = to_clk_lightdiv(hw);
  454. return light_div->ops->round_rate(&light_div->divider.hw, rate, prate);
  455. }
  456. static int clk_lightdiv_set_rate(struct clk_hw *hw, unsigned long rate,
  457. unsigned long parent_rate)
  458. {
  459. struct clk_lightdiv *light_div = to_clk_lightdiv(hw);
  460. struct clk_divider *div = to_clk_divider(hw);
  461. unsigned int divider, value;
  462. unsigned long flags = 0;
  463. u32 val;
  464. divider = parent_rate / rate;
  465. /* DIV is zero based divider, but CDE is not */
  466. if (light_div->div_type == MUX_TYPE_DIV)
  467. value = divider;
  468. else
  469. value = divider - 1;
  470. /* handle the div valid range */
  471. if (value > light_div->max_div)
  472. value = light_div->max_div;
  473. if (value < light_div->min_div)
  474. value = light_div->min_div;
  475. spin_lock_irqsave(div->lock, flags);
  476. val = readl(div->reg);
  477. val &= ~BIT(light_div->sync_en);
  478. writel(val, div->reg);
  479. udelay(1);
  480. val &= ~(div_mask(div) << div->shift);
  481. val |= value << div->shift;
  482. writel(val, div->reg);
  483. udelay(1);
  484. val |= BIT(light_div->sync_en);
  485. writel(val, div->reg);
  486. spin_unlock_irqrestore(div->lock, flags);
  487. return 0;
  488. }
  489. static const struct clk_ops clk_lightdiv_ops = {
  490. .recalc_rate = clk_lightdiv_recalc_rate,
  491. .round_rate = clk_lightdiv_round_rate,
  492. .set_rate = clk_lightdiv_set_rate,
  493. };
  494. struct clk *thead_clk_light_divider(const char *name, const char *parent,
  495. void __iomem *reg, u8 shift, u8 width,
  496. u8 sync, enum light_div_type div_type,
  497. u16 min, u16 max)
  498. {
  499. struct clk_lightdiv *light_div;
  500. struct clk_hw *hw;
  501. struct clk_init_data init;
  502. int ret;
  503. light_div = kzalloc(sizeof(*light_div), GFP_KERNEL);
  504. if (!light_div)
  505. return ERR_PTR(-ENOMEM);
  506. init.name = name;
  507. init.ops = &clk_lightdiv_ops;
  508. init.flags = CLK_SET_RATE_PARENT;
  509. init.parent_names = parent ? &parent : NULL;
  510. init.num_parents = parent ? 1 : 0;
  511. light_div->divider.reg = reg;
  512. light_div->divider.shift = shift;
  513. light_div->divider.width = width;
  514. light_div->divider.lock = &thead_light_clk_lock;
  515. light_div->divider.hw.init = &init;
  516. light_div->ops = &clk_divider_ops;
  517. light_div->sync_en = sync;
  518. light_div->div_type = div_type;
  519. if (light_div->div_type == MUX_TYPE_DIV)
  520. light_div->divider.flags = CLK_DIVIDER_ONE_BASED;
  521. light_div->min_div = min > ((1 << width) - 1) ?
  522. ((1 << width) - 1) : min;
  523. light_div->max_div = max > ((1 << width) - 1) ?
  524. ((1 << width) - 1) : max;
  525. hw = &light_div->divider.hw;
  526. ret = clk_hw_register(NULL, hw);
  527. if (ret) {
  528. kfree(light_div);
  529. return ERR_PTR(ret);
  530. }
  531. return hw->clk;
  532. }
  533. static inline struct clk_lightgate *to_clk_lightgate(struct clk_hw *hw)
  534. {
  535. struct clk_gate *gate = to_clk_gate(hw);
  536. return container_of(gate, struct clk_lightgate, gate);
  537. }
  538. static int clk_light_gate_share_is_enabled(struct clk_hw *hw)
  539. {
  540. struct clk_lightgate *light_gate = to_clk_lightgate(hw);
  541. return light_gate->ops->is_enabled(hw);
  542. }
  543. static int clk_light_gate_share_enable(struct clk_hw *hw)
  544. {
  545. struct clk_lightgate *light_gate = to_clk_lightgate(hw);
  546. if (light_gate->share_count && (*light_gate->share_count)++ > 0) {
  547. pr_debug("[%s,%d]share_count = %d\n", __func__, __LINE__, (*light_gate->share_count));
  548. return 0;
  549. }
  550. pr_debug("[%s,%d]share_count = %d\n", __func__, __LINE__, (*light_gate->share_count));
  551. return light_gate->ops->enable(hw);
  552. }
  553. static void clk_light_gate_share_disable(struct clk_hw *hw)
  554. {
  555. struct clk_lightgate *light_gate = to_clk_lightgate(hw);
  556. if (light_gate->share_count) {
  557. if (WARN_ON(*light_gate->share_count == 0))
  558. return;
  559. else if (--(*light_gate->share_count) > 0) {
  560. pr_debug("[%s,%d]share_count = %d\n", __func__, __LINE__, (*light_gate->share_count));
  561. return;
  562. }
  563. }
  564. pr_debug("[%s,%d]share_count = %d\n", __func__, __LINE__, (*light_gate->share_count));
  565. light_gate->ops->disable(hw);
  566. }
  567. static void clk_light_gate_share_disable_unused(struct clk_hw *hw)
  568. {
  569. struct clk_lightgate *light_gate = to_clk_lightgate(hw);
  570. if (!light_gate->share_count || *light_gate->share_count == 0)
  571. return light_gate->ops->disable(hw);
  572. }
  573. static const struct clk_ops clk_lightgate_share_ops = {
  574. .enable = clk_light_gate_share_enable,
  575. .disable = clk_light_gate_share_disable,
  576. .disable_unused = clk_light_gate_share_disable_unused,
  577. .is_enabled = clk_light_gate_share_is_enabled,
  578. };
  579. struct clk *thead_clk_light_register_gate_shared(const char *name, const char *parent,
  580. unsigned long flags, void __iomem *reg,
  581. u8 shift, spinlock_t *lock,
  582. unsigned int *share_count)
  583. {
  584. struct clk_lightgate *light_gate;
  585. struct clk_hw *hw;
  586. struct clk_init_data init;
  587. int ret;
  588. light_gate = kzalloc(sizeof(*light_gate), GFP_KERNEL);
  589. if (!light_gate)
  590. return ERR_PTR(-ENOMEM);
  591. light_gate->gate.reg = reg;
  592. light_gate->gate.bit_idx = shift;
  593. light_gate->gate.flags = 0;
  594. light_gate->gate.lock = lock;
  595. light_gate->gate.hw.init = &init;
  596. light_gate->ops = &clk_gate_ops;
  597. light_gate->share_count = share_count;
  598. init.name = name;
  599. init.ops = &clk_lightgate_share_ops;
  600. init.flags = flags;
  601. init.parent_names = parent ? &parent : NULL;
  602. init.num_parents = parent ? 1 : 0;
  603. hw = &light_gate->gate.hw;
  604. ret = clk_hw_register(NULL, hw);
  605. if (ret) {
  606. kfree(light_gate);
  607. return ERR_PTR(ret);
  608. }
  609. return hw->clk;
  610. }