clk-light-fm.c 47 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/clock/light-fm-ap-clock.h>
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/types.h>
  17. #include "clk.h"
  18. static struct clk *clks[CLK_END];
  19. static struct clk_onecell_data clk_data;
  20. /* Light Fullmask */
  21. static u32 share_cnt_x2h_cpusys_clk_en;
  22. static u32 share_cnt_dmac_cpusys_clk_en;
  23. static u32 share_cnt_timer0_clk_en;
  24. static u32 share_cnt_timer1_clk_en;
  25. static u32 share_cnt_axi4_cpusys2_clk_en;
  26. static u32 share_cnt_bmu_c910_clk_en;
  27. static u32 share_cnt_aon2cpu_a2x_clk_en;
  28. static u32 share_cnt_chip_dbg_clk_en;
  29. static u32 share_cnt_x2x_cpusys_clk_en;
  30. static u32 share_cnt_cfg2tee_x2h_clk_en;
  31. static u32 share_cnt_cpu2aon_x2h_clk_en;
  32. static u32 share_cnt_cpu2vp_x2p_clk_en;
  33. static u32 share_cnt_npu_core_clk_en;
  34. static u32 share_cnt_cpu2peri_x2h_clk_en;
  35. static u32 share_cnt_cpu2vi_x2h_clk_en;
  36. static u32 share_cnt_vpsys_axi_aclk_en;
  37. static u32 share_cnt_gmac1_clk_en;
  38. static u32 share_cnt_gmac0_clk_en;
  39. static u32 share_cnt_perisys_apb3_hclk_en;
  40. static u32 share_cnt_qspi0_clk_en;
  41. static u32 share_cnt_gmac_axi_clk_en;
  42. static u32 share_cnt_gpio0_clk_en;
  43. static u32 share_cnt_gpio1_clk_en;
  44. static u32 share_cnt_pwm_clk_en;
  45. static u32 share_cnt_spi_clk_en;
  46. static u32 share_cnt_uart0_clk_en;
  47. static u32 share_cnt_uart2_clk_en;
  48. static u32 share_cnt_i2c2_clk_en;
  49. static u32 share_cnt_peri_i2s_clk_en;
  50. static u32 share_cnt_qspi1_clk_en;
  51. static u32 share_cnt_uart1_clk_en;
  52. static u32 share_cnt_uart3_clk_en;
  53. static u32 share_cnt_uart4_clk_en;
  54. static u32 share_cnt_uart5_clk_en;
  55. static u32 share_cnt_i2c0_clk_en;
  56. static u32 share_cnt_i2c1_clk_en;
  57. static u32 share_cnt_i2c4_clk_en;
  58. static u32 share_cnt_i2c5_clk_en;
  59. static u32 share_cnt_gpio2_clk_en;
  60. static u32 share_cnt_gpio3_clk_en;
  61. static u32 share_cnt_vosys_axi_aclk_en;
  62. /* Light Fullmask PLL Bypass */
  63. static const char * const cpu_pll0_bypass_sels[] = {"cpu_pll0_foutpostdiv", "osc_24m", };
  64. static const char * const cpu_pll1_bypass_sels[] = {"cpu_pll1_foutpostdiv", "osc_24m", };
  65. static const char * const gmac_pll_bypass_sels[] = {"gmac_pll_foutpostdiv", "osc_24m", };
  66. static const char * const video_pll_bypass_sels[] = {"video_pll_foutpostdiv", "osc_24m", };
  67. static const char * const tee_pll_bypass_sels[] = {"tee_pll_foutpostdiv", "osc_24m"};
  68. static const char * const dpu0_pll_bypass_sels[] = {"dpu0_pll_foutpostdiv", "osc_24m"};
  69. static const char * const dpu1_pll_bypass_sels[] = {"dpu1_pll_foutpostdiv", "osc_24m"};
  70. /* light fullmask mux */
  71. static const char * const ahb2_cpusys_hclk_sels[] = {"ahb2_cpusys_hclk_out_div", "osc_24m"};
  72. static const char * const c910_cclk_i0_sels[] = {"cpu_pll0_foutpostdiv", "osc_24m"};
  73. static const char * const c910_cclk_sels[] = {"c910_cclk_i0", "cpu_pll1_foutpostdiv"};
  74. static const char * const cfg_axi_aclk_sels[] = {"cfg_axi_aclk_out_div", "osc_24m"};
  75. static const char * const teesys_hclk_sels[] = {"teesys_i1_hclk", "teesys_i0_hclk"};
  76. static const char * const perisys_ahb_hclk_sels[] = {"perisys_ahb_hclk_out_div", "osc_24m"};
  77. static const char * const clk_out_1_sels[] = {"osc_24m", "clk_out_1_out_div"};
  78. static const char * const clk_out_2_sels[] = {"osc_24m", "clk_out_2_out_div"};
  79. static const char * const clk_out_3_sels[] = {"osc_24m", "clk_out_3_out_div"};
  80. static const char * const clk_out_4_sels[] = {"osc_24m", "clk_out_4_out_div"};
  81. static const char * const peri_i2s_src_clk_sels[] = {"clkgen_peri_i2s_src_clk_0", "clkgen_peri_i2s_src_clk_1"};
  82. static const char * const npu_cclk_sels[] = {"gmac_pll_foutpostdiv", "npu_cclk_out_div"};
  83. static const char * const cfg_apb_pclk_sels[] = {"cfg_apb_pclk_out_div", "osc_24m"};
  84. static const char * const uart_sclk_sels[] = {"clk_100m", "osc_24m"};
  85. static const struct light_pll_rate_table light_cpupll_tbl[] = {
  86. LIGHT_PLL_RATE(2616000000U, 2616000000U, 1, 109, 0, 1, 1),
  87. LIGHT_PLL_RATE(2592000000U, 2592000000U, 1, 108, 0, 1, 1),
  88. LIGHT_PLL_RATE(2568000000U, 2568000000U, 1, 107, 0, 1, 1),
  89. LIGHT_PLL_RATE(2544000000U, 2544000000U, 1, 106, 0, 1, 1),
  90. LIGHT_PLL_RATE(2520000000U, 2520000000U, 1, 105, 0, 1, 1),
  91. LIGHT_PLL_RATE(2496000000U, 2496000000U, 1, 104, 0, 1, 1),
  92. LIGHT_PLL_RATE(2472000000U, 2472000000U, 1, 103, 0, 1, 1),
  93. LIGHT_PLL_RATE(2448000000U, 2448000000U, 1, 102, 0, 1, 1),
  94. LIGHT_PLL_RATE(2424000000U, 2424000000U, 1, 101, 0, 1, 1),
  95. LIGHT_PLL_RATE(2400000000U, 2400000000U, 1, 100, 0, 1, 1),
  96. LIGHT_PLL_RATE(2376000000U, 2376000000U, 1, 99, 0, 1, 1),
  97. LIGHT_PLL_RATE(2352000000U, 2352000000U, 1, 98, 0, 1, 1),
  98. LIGHT_PLL_RATE(2328000000U, 2328000000U, 1, 97, 0, 1, 1),
  99. LIGHT_PLL_RATE(2304000000U, 2304000000U, 1, 96, 0, 1, 1),
  100. LIGHT_PLL_RATE(2280000000U, 2280000000U, 1, 95, 0, 1, 1),
  101. LIGHT_PLL_RATE(2256000000U, 2256000000U, 1, 94, 0, 1, 1),
  102. LIGHT_PLL_RATE(2232000000U, 2232000000U, 1, 93, 0, 1, 1),
  103. LIGHT_PLL_RATE(2208000000U, 2208000000U, 1, 92, 0, 1, 1),
  104. LIGHT_PLL_RATE(2184000000U, 2184000000U, 1, 91, 0, 1, 1),
  105. LIGHT_PLL_RATE(2160000000U, 2160000000U, 1, 90, 0, 1, 1),
  106. LIGHT_PLL_RATE(2136000000U, 2136000000U, 1, 89, 0, 1, 1),
  107. LIGHT_PLL_RATE(2112000000U, 2112000000U, 1, 88, 0, 1, 1),
  108. LIGHT_PLL_RATE(2088000000U, 2088000000U, 1, 87, 0, 1, 1),
  109. LIGHT_PLL_RATE(2064000000U, 2064000000U, 1, 86, 0, 1, 1),
  110. LIGHT_PLL_RATE(2040000000U, 2040000000U, 1, 85, 0, 1, 1),
  111. LIGHT_PLL_RATE(2016000000U, 2016000000U, 1, 84, 0, 1, 1),
  112. LIGHT_PLL_RATE(1992000000U, 1992000000U, 1, 83, 0, 1, 1),
  113. LIGHT_PLL_RATE(1968000000U, 1968000000U, 1, 82, 0, 1, 1),
  114. LIGHT_PLL_RATE(1944000000U, 1944000000U, 1, 81, 0, 1, 1),
  115. LIGHT_PLL_RATE(1920000000U, 1920000000U, 1, 80, 0, 1, 1),
  116. LIGHT_PLL_RATE(1896000000U, 1896000000U, 1, 79, 0, 1, 1),
  117. LIGHT_PLL_RATE(1872000000U, 1872000000U, 1, 78, 0, 1, 1),
  118. LIGHT_PLL_RATE(1848000000U, 1848000000U, 1, 77, 0, 1, 1),
  119. LIGHT_PLL_RATE(1824000000U, 1824000000U, 1, 76, 0, 1, 1),
  120. LIGHT_PLL_RATE(1800000000U, 1800000000U, 1, 75, 0, 1, 1),
  121. LIGHT_PLL_RATE(1776000000U, 1776000000U, 1, 74, 0, 1, 1),
  122. LIGHT_PLL_RATE(1752000000U, 1752000000U, 1, 73, 0, 1, 1),
  123. LIGHT_PLL_RATE(1728000000U, 1728000000U, 1, 72, 0, 1, 1),
  124. LIGHT_PLL_RATE(1704000000U, 1704000000U, 1, 71, 0, 1, 1),
  125. LIGHT_PLL_RATE(1680000000U, 1680000000U, 1, 70, 0, 1, 1),
  126. LIGHT_PLL_RATE(1656000000U, 1656000000U, 1, 69, 0, 1, 1),
  127. LIGHT_PLL_RATE(1632000000U, 1632000000U, 1, 68, 0, 1, 1),
  128. LIGHT_PLL_RATE(1608000000U, 1608000000U, 1, 67, 0, 1, 1),
  129. LIGHT_PLL_RATE(1584000000U, 1584000000U, 1, 66, 0, 1, 1),
  130. LIGHT_PLL_RATE(1560000000U, 1560000000U, 1, 65, 0, 1, 1),
  131. LIGHT_PLL_RATE(1536000000U, 1536000000U, 1, 64, 0, 1, 1),
  132. LIGHT_PLL_RATE(1512000000U, 1512000000U, 1, 63, 0, 1, 1),
  133. LIGHT_PLL_RATE(3000000000U, 1500000000U, 1, 125, 0, 2, 1),
  134. LIGHT_PLL_RATE(2976000000U, 1488000000U, 1, 124, 0, 2, 1),
  135. LIGHT_PLL_RATE(2952000000U, 1476000000U, 1, 123, 0, 2, 1),
  136. LIGHT_PLL_RATE(2928000000U, 1464000000U, 1, 122, 0, 2, 1),
  137. LIGHT_PLL_RATE(2904000000U, 1452000000U, 1, 121, 0, 2, 1),
  138. LIGHT_PLL_RATE(2880000000U, 1440000000U, 1, 120, 0, 2, 1),
  139. LIGHT_PLL_RATE(2856000000U, 1428000000U, 1, 119, 0, 2, 1),
  140. LIGHT_PLL_RATE(2832000000U, 1416000000U, 1, 118, 0, 2, 1),
  141. LIGHT_PLL_RATE(2808000000U, 1404000000U, 1, 117, 0, 2, 1),
  142. LIGHT_PLL_RATE(2784000000U, 1392000000U, 1, 116, 0, 2, 1),
  143. LIGHT_PLL_RATE(2760000000U, 1380000000U, 1, 115, 0, 2, 1),
  144. LIGHT_PLL_RATE(2736000000U, 1368000000U, 1, 114, 0, 2, 1),
  145. LIGHT_PLL_RATE(2712000000U, 1356000000U, 1, 113, 0, 2, 1),
  146. LIGHT_PLL_RATE(2688000000U, 1344000000U, 1, 112, 0, 2, 1),
  147. LIGHT_PLL_RATE(2664000000U, 1332000000U, 1, 111, 0, 2, 1),
  148. LIGHT_PLL_RATE(2640000000U, 1320000000U, 1, 110, 0, 2, 1),
  149. LIGHT_PLL_RATE(2616000000U, 1308000000U, 1, 109, 0, 2, 1),
  150. LIGHT_PLL_RATE(2592000000U, 1296000000U, 1, 108, 0, 2, 1),
  151. LIGHT_PLL_RATE(2568000000U, 1284000000U, 1, 107, 0, 2, 1),
  152. LIGHT_PLL_RATE(2544000000U, 1272000000U, 1, 106, 0, 2, 1),
  153. LIGHT_PLL_RATE(2520000000U, 1260000000U, 1, 105, 0, 2, 1),
  154. LIGHT_PLL_RATE(2496000000U, 1248000000U, 1, 104, 0, 2, 1),
  155. LIGHT_PLL_RATE(2472000000U, 1236000000U, 1, 103, 0, 2, 1),
  156. LIGHT_PLL_RATE(2448000000U, 1224000000U, 1, 102, 0, 2, 1),
  157. LIGHT_PLL_RATE(2424000000U, 1212000000U, 1, 101, 0, 2, 1),
  158. LIGHT_PLL_RATE(2400000000U, 1200000000U, 1, 100, 0, 2, 1),
  159. LIGHT_PLL_RATE(2376000000U, 1188000000U, 1, 99, 0, 2, 1),
  160. LIGHT_PLL_RATE(2352000000U, 1176000000U, 1, 98, 0, 2, 1),
  161. LIGHT_PLL_RATE(2328000000U, 1164000000U, 1, 97, 0, 2, 1),
  162. LIGHT_PLL_RATE(2304000000U, 1152000000U, 1, 96, 0, 2, 1),
  163. LIGHT_PLL_RATE(2280000000U, 1140000000U, 1, 95, 0, 2, 1),
  164. LIGHT_PLL_RATE(2256000000U, 1128000000U, 1, 94, 0, 2, 1),
  165. LIGHT_PLL_RATE(2232000000U, 1116000000U, 1, 93, 0, 2, 1),
  166. LIGHT_PLL_RATE(2208000000U, 1104000000U, 1, 92, 0, 2, 1),
  167. LIGHT_PLL_RATE(2184000000U, 1092000000U, 1, 91, 0, 2, 1),
  168. LIGHT_PLL_RATE(2160000000U, 1080000000U, 1, 90, 0, 2, 1),
  169. LIGHT_PLL_RATE(2136000000U, 1068000000U, 1, 89, 0, 2, 1),
  170. LIGHT_PLL_RATE(2112000000U, 1056000000U, 1, 88, 0, 2, 1),
  171. LIGHT_PLL_RATE(2088000000U, 1044000000U, 1, 87, 0, 2, 1),
  172. LIGHT_PLL_RATE(2064000000U, 1032000000U, 1, 86, 0, 2, 1),
  173. LIGHT_PLL_RATE(2040000000U, 1020000000U, 1, 85, 0, 2, 1),
  174. LIGHT_PLL_RATE(2016000000U, 1008000000U, 1, 84, 0, 2, 1),
  175. LIGHT_PLL_RATE(3000000000U, 1000000000U, 1, 125, 0, 3, 1),
  176. LIGHT_PLL_RATE(2976000000U, 992000000U, 1, 124, 0, 3, 1),
  177. LIGHT_PLL_RATE(2952000000U, 984000000U, 1, 123, 0, 3, 1),
  178. LIGHT_PLL_RATE(2928000000U, 976000000U, 1, 122, 0, 3, 1),
  179. LIGHT_PLL_RATE(2904000000U, 968000000U, 1, 121, 0, 3, 1),
  180. LIGHT_PLL_RATE(2880000000U, 960000000U, 1, 120, 0, 3, 1),
  181. LIGHT_PLL_RATE(2856000000U, 952000000U, 1, 119, 0, 3, 1),
  182. LIGHT_PLL_RATE(2832000000U, 944000000U, 1, 118, 0, 3, 1),
  183. LIGHT_PLL_RATE(2808000000U, 936000000U, 1, 117, 0, 3, 1),
  184. LIGHT_PLL_RATE(2784000000U, 928000000U, 1, 116, 0, 3, 1),
  185. LIGHT_PLL_RATE(2760000000U, 920000000U, 1, 115, 0, 3, 1),
  186. LIGHT_PLL_RATE(2736000000U, 912000000U, 1, 114, 0, 3, 1),
  187. LIGHT_PLL_RATE(2712000000U, 904000000U, 1, 113, 0, 3, 1),
  188. LIGHT_PLL_RATE(1800000000U, 900000000U, 1, 75, 0, 2, 1),
  189. LIGHT_PLL_RATE(2688000000U, 896000000U, 1, 112, 0, 3, 1),
  190. LIGHT_PLL_RATE(2664000000U, 888000000U, 1, 111, 0, 3, 1),
  191. LIGHT_PLL_RATE(2640000000U, 880000000U, 1, 110, 0, 3, 1),
  192. LIGHT_PLL_RATE(2616000000U, 872000000U, 1, 109, 0, 3, 1),
  193. LIGHT_PLL_RATE(2592000000U, 864000000U, 1, 108, 0, 3, 1),
  194. LIGHT_PLL_RATE(2568000000U, 856000000U, 1, 107, 0, 3, 1),
  195. LIGHT_PLL_RATE(2544000000U, 848000000U, 1, 106, 0, 3, 1),
  196. LIGHT_PLL_RATE(2520000000U, 840000000U, 1, 105, 0, 3, 1),
  197. LIGHT_PLL_RATE(2496000000U, 832000000U, 1, 104, 0, 3, 1),
  198. LIGHT_PLL_RATE(2472000000U, 824000000U, 1, 103, 0, 3, 1),
  199. LIGHT_PLL_RATE(2448000000U, 816000000U, 1, 102, 0, 3, 1),
  200. LIGHT_PLL_RATE(2424000000U, 808000000U, 1, 101, 0, 3, 1),
  201. LIGHT_PLL_RATE(2400000000U, 800000000U, 1, 100, 0, 3, 1),
  202. LIGHT_PLL_RATE(2376000000U, 792000000U, 1, 99, 0, 3, 1),
  203. LIGHT_PLL_RATE(2352000000U, 784000000U, 1, 98, 0, 3, 1),
  204. LIGHT_PLL_RATE(2328000000U, 776000000U, 1, 97, 0, 3, 1),
  205. LIGHT_PLL_RATE(2304000000U, 768000000U, 1, 96, 0, 3, 1),
  206. LIGHT_PLL_RATE(2280000000U, 760000000U, 1, 95, 0, 3, 1),
  207. LIGHT_PLL_RATE(2256000000U, 752000000U, 1, 94, 0, 3, 1),
  208. LIGHT_PLL_RATE(2232000000U, 744000000U, 1, 93, 0, 3, 1),
  209. LIGHT_PLL_RATE(2208000000U, 736000000U, 1, 92, 0, 3, 1),
  210. LIGHT_PLL_RATE(2184000000U, 728000000U, 1, 91, 0, 3, 1),
  211. LIGHT_PLL_RATE(2160000000U, 720000000U, 1, 90, 0, 3, 1),
  212. LIGHT_PLL_RATE(2136000000U, 712000000U, 1, 89, 0, 3, 1),
  213. LIGHT_PLL_RATE(2808000000U, 702000000U, 1, 117, 0, 4, 1),
  214. LIGHT_PLL_RATE(2760000000U, 690000000U, 1, 115, 0, 4, 1),
  215. LIGHT_PLL_RATE(2712000000U, 678000000U, 1, 113, 0, 4, 1),
  216. LIGHT_PLL_RATE(2664000000U, 666000000U, 1, 111, 0, 4, 1),
  217. LIGHT_PLL_RATE(2616000000U, 654000000U, 1, 109, 0, 4, 1),
  218. LIGHT_PLL_RATE(2568000000U, 642000000U, 1, 107, 0, 4, 1),
  219. LIGHT_PLL_RATE(2520000000U, 630000000U, 1, 105, 0, 4, 1),
  220. LIGHT_PLL_RATE(2472000000U, 618000000U, 1, 103, 0, 4, 1),
  221. LIGHT_PLL_RATE(2424000000U, 606000000U, 1, 101, 0, 4, 1),
  222. LIGHT_PLL_RATE(3000000000U, 600000000U, 1, 125, 0, 5, 1),
  223. LIGHT_PLL_RATE(2952000000U, 590400000U, 1, 123, 0, 5, 1),
  224. LIGHT_PLL_RATE(2904000000U, 580800000U, 1, 121, 0, 5, 1),
  225. LIGHT_PLL_RATE(2856000000U, 571200000U, 1, 119, 0, 5, 1),
  226. LIGHT_PLL_RATE(2808000000U, 561600000U, 1, 117, 0, 5, 1),
  227. LIGHT_PLL_RATE(2760000000U, 552000000U, 1, 115, 0, 5, 1),
  228. LIGHT_PLL_RATE(2712000000U, 542400000U, 1, 113, 0, 5, 1),
  229. LIGHT_PLL_RATE(2664000000U, 532800000U, 1, 111, 0, 5, 1),
  230. LIGHT_PLL_RATE(2616000000U, 523200000U, 1, 109, 0, 5, 1),
  231. LIGHT_PLL_RATE(2568000000U, 513600000U, 1, 107, 0, 5, 1),
  232. LIGHT_PLL_RATE(2520000000U, 504000000U, 1, 105, 0, 5, 1),
  233. LIGHT_PLL_RATE(3000000000U, 500000000U, 1, 125, 0, 6, 1),
  234. LIGHT_PLL_RATE(2952000000U, 492000000U, 1, 123, 0, 6, 1),
  235. LIGHT_PLL_RATE(2904000000U, 484000000U, 1, 121, 0, 6, 1),
  236. LIGHT_PLL_RATE(2856000000U, 476000000U, 1, 119, 0, 6, 1),
  237. LIGHT_PLL_RATE(2808000000U, 468000000U, 1, 117, 0, 6, 1),
  238. LIGHT_PLL_RATE(2760000000U, 460000000U, 1, 115, 0, 6, 1),
  239. LIGHT_PLL_RATE(2712000000U, 452000000U, 1, 113, 0, 6, 1),
  240. LIGHT_PLL_RATE(2664000000U, 444000000U, 1, 111, 0, 6, 1),
  241. LIGHT_PLL_RATE(2616000000U, 436000000U, 1, 109, 0, 6, 1),
  242. LIGHT_PLL_RATE(2568000000U, 428000000U, 1, 107, 0, 6, 1),
  243. LIGHT_PLL_RATE(2520000000U, 420000000U, 1, 105, 0, 6, 1),
  244. LIGHT_PLL_RATE(2472000000U, 412000000U, 1, 103, 0, 6, 1),
  245. LIGHT_PLL_RATE(2400000000U, 400000000U, 1, 100, 0, 3, 2),
  246. LIGHT_PLL_RATE(2352000000U, 392000000U, 1, 98, 0, 3, 2),
  247. LIGHT_PLL_RATE(2304000000U, 384000000U, 1, 96, 0, 3, 2),
  248. LIGHT_PLL_RATE(2256000000U, 376000000U, 1, 94, 0, 3, 2),
  249. LIGHT_PLL_RATE(2208000000U, 368000000U, 1, 92, 0, 3, 2),
  250. LIGHT_PLL_RATE(2160000000U, 360000000U, 1, 90, 0, 3, 2),
  251. LIGHT_PLL_RATE(2112000000U, 352000000U, 1, 88, 0, 3, 2),
  252. LIGHT_PLL_RATE(2064000000U, 344000000U, 1, 86, 0, 3, 2),
  253. LIGHT_PLL_RATE(2016000000U, 336000000U, 1, 84, 0, 3, 2),
  254. LIGHT_PLL_RATE(1968000000U, 328000000U, 1, 82, 0, 3, 2),
  255. LIGHT_PLL_RATE(1920000000U, 320000000U, 1, 80, 0, 3, 2),
  256. LIGHT_PLL_RATE(1872000000U, 312000000U, 1, 78, 0, 3, 2),
  257. LIGHT_PLL_RATE(1824000000U, 304000000U, 1, 76, 0, 3, 2),
  258. LIGHT_PLL_RATE(3000000000U, 300000000U, 1, 125, 0, 5, 2),
  259. LIGHT_PLL_RATE(2880000000U, 288000000U, 1, 120, 0, 5, 2),
  260. LIGHT_PLL_RATE(2760000000U, 276000000U, 1, 115, 0, 5, 2),
  261. LIGHT_PLL_RATE(2640000000U, 264000000U, 1, 110, 0, 5, 2),
  262. LIGHT_PLL_RATE(2520000000U, 252000000U, 1, 105, 0, 5, 2),
  263. LIGHT_PLL_RATE(2400000000U, 240000000U, 1, 100, 0, 5, 2),
  264. LIGHT_PLL_RATE(2280000000U, 228000000U, 1, 95, 0, 5, 2),
  265. LIGHT_PLL_RATE(2160000000U, 216000000U, 1, 90, 0, 5, 2),
  266. LIGHT_PLL_RATE(2040000000U, 204000000U, 1, 85, 0, 5, 2),
  267. LIGHT_PLL_RATE(3000000000U, 200000000U, 1, 125, 0, 5, 3),
  268. LIGHT_PLL_RATE(2880000000U, 192000000U, 1, 120, 0, 5, 3),
  269. LIGHT_PLL_RATE(2760000000U, 184000000U, 1, 115, 0, 5, 3),
  270. LIGHT_PLL_RATE(2640000000U, 176000000U, 1, 110, 0, 5, 3),
  271. LIGHT_PLL_RATE(2520000000U, 168000000U, 1, 105, 0, 5, 3),
  272. LIGHT_PLL_RATE(2400000000U, 160000000U, 1, 100, 0, 5, 3),
  273. LIGHT_PLL_RATE(2280000000U, 152000000U, 1, 95, 0, 5, 3),
  274. LIGHT_PLL_RATE(2160000000U, 144000000U, 1, 90, 0, 5, 3),
  275. LIGHT_PLL_RATE(2040000000U, 136000000U, 1, 85, 0, 5, 3),
  276. LIGHT_PLL_RATE(1920000000U, 128000000U, 1, 80, 0, 5, 3),
  277. LIGHT_PLL_RATE(3000000000U, 125000000U, 1, 125, 0, 6, 4),
  278. LIGHT_PLL_RATE(2760000000U, 115000000U, 1, 115, 0, 6, 4),
  279. LIGHT_PLL_RATE(2520000000U, 105000000U, 1, 105, 0, 6, 4),
  280. LIGHT_PLL_RATE(2280000000U, 95000000U, 1, 95, 0, 6, 4),
  281. LIGHT_PLL_RATE(2040000000U, 85000000U, 1, 85, 0, 6, 4),
  282. LIGHT_PLL_RATE(1800000000U, 75000000U, 1, 75, 0, 6, 4),
  283. LIGHT_PLL_RATE(1560000000U, 65000000U, 1, 65, 0, 6, 4),
  284. LIGHT_PLL_RATE(1320000000U, 55000000U, 1, 55, 0, 6, 4),
  285. };
  286. static const struct light_pll_rate_table light_dpupll_tbl[] = {
  287. LIGHT_PLL_RATE(2376000000U, 1188000000U, 1, 99, 0, 2, 1),
  288. LIGHT_PLL_RATE(1980000000U, 990000000U, 2, 165, 0, 2, 1),
  289. LIGHT_PLL_RATE(2970000000U, 742500000U, 4, 495, 0, 4, 1),
  290. LIGHT_PLL_RATE(2304000000U, 1152000000U, 1, 96, 0, 2, 1),
  291. LIGHT_PLL_RATE(1512000000U, 504000000U, 1, 63, 0, 3, 1),
  292. LIGHT_PLL_RATE(1512000000U, 503500000U, 1, 63, 0, 3, 1),
  293. LIGHT_PLL_RATE(2898000000U, 483000000U, 4, 483, 0, 6, 1),
  294. LIGHT_PLL_RATE(2592000000U, 648000000U, 1, 108, 0, 4, 1),
  295. LIGHT_PLL_RATE(2772000000U, 924000000U, 2, 231, 0, 3, 1),
  296. LIGHT_PLL_RATE(2856000000U, 476000000U, 1, 119, 0, 6, 1),
  297. LIGHT_PLL_RATE(2130000000U, 355000000U, 4, 355, 0, 6, 1),
  298. LIGHT_PLL_RATE(3192000000U, 456000000U, 1, 133, 0, 7, 1),
  299. LIGHT_PLL_RATE(2730000000U, 390000000U, 4, 455, 0, 7, 1),
  300. LIGHT_PLL_RATE(1680000000U, 240000000U, 1, 70, 0, 7, 1),
  301. LIGHT_PLL_RATE(2832000000U, 708000000U, 1, 118, 0, 4, 1),
  302. LIGHT_PLL_RATE(1026000000U, 342000000U, 4, 171, 0, 3, 1),
  303. LIGHT_PLL_RATE(1260000000U, 630000000U, 4, 210, 0, 2, 1),
  304. };
  305. static struct light_pll_clk light_cpu_pll0div = {
  306. .out_type = LIGHT_PLL_DIV,
  307. .clk_type = LIGHT_CPU_PLL0,
  308. .rate_table = light_cpupll_tbl,
  309. .rate_count = ARRAY_SIZE(light_cpupll_tbl),
  310. };
  311. static struct light_pll_clk light_cpu_pll1div = {
  312. .out_type = LIGHT_PLL_DIV,
  313. .clk_type = LIGHT_CPU_PLL1,
  314. .rate_table = light_cpupll_tbl,
  315. .rate_count = ARRAY_SIZE(light_cpupll_tbl),
  316. };
  317. static struct light_pll_clk light_dpu0_plldiv = {
  318. .out_type = LIGHT_PLL_DIV,
  319. .clk_type = LIGHT_DPU0_PLL,
  320. .rate_table = light_dpupll_tbl,
  321. .rate_count = ARRAY_SIZE(light_dpupll_tbl),
  322. };
  323. static struct light_pll_clk light_dpu1_plldiv = {
  324. .out_type = LIGHT_PLL_DIV,
  325. .clk_type = LIGHT_DPU1_PLL,
  326. .rate_table = light_dpupll_tbl,
  327. .rate_count = ARRAY_SIZE(light_dpupll_tbl),
  328. };
  329. static int light_clocks_probe(struct platform_device *pdev)
  330. {
  331. struct device *dev = &pdev->dev;
  332. struct device_node *np = dev->of_node;
  333. void __iomem *ap_base;
  334. int ret;
  335. const bool *teesys = of_device_get_match_data(dev);
  336. /* Clock source */
  337. clks[CLK_DUMMY] = thead_clk_fixed("dummy", 0);
  338. clks[OSC_32K] = of_clk_get_by_name(np, "osc_32k");
  339. clks[OSC_24M] = of_clk_get_by_name(np, "osc_24m");
  340. clks[RC_24M] = of_clk_get_by_name(np, "rc_24m");
  341. np = dev->of_node;
  342. ap_base = devm_platform_ioremap_resource(pdev, 0);
  343. if (WARN_ON(IS_ERR(ap_base))) {
  344. ret = PTR_ERR(ap_base);
  345. goto unregister_clks;
  346. }
  347. /* Light Fullmask AP PLL clocks */
  348. clks[CPU_PLL0_FOUTPOSTDIV] = thead_light_pll("cpu_pll0_foutpostdiv", "osc_24m", ap_base, &light_cpu_pll0div);
  349. clks[CPU_PLL1_FOUTPOSTDIV] = thead_light_pll("cpu_pll1_foutpostdiv", "osc_24m", ap_base, &light_cpu_pll1div);
  350. clks[DPU0_PLL_FOUTPOSTDIV] = thead_light_pll("dpu0_pll_foutpostdiv", "osc_24m", ap_base, &light_dpu0_plldiv);
  351. clks[DPU1_PLL_FOUTPOSTDIV] = thead_light_pll("dpu1_pll_foutpostdiv", "osc_24m", ap_base, &light_dpu1_plldiv);
  352. /* Light Fullmask AP Fixed PLL */
  353. clks[GMAC_PLL_FOUTPOSTDIV] = thead_clk_fixed("gmac_pll_foutpostdiv", 1000000000);
  354. clks[VIDEO_PLL_FOUTPOSTDIV] = thead_clk_fixed("video_pll_foutpostdiv", 792000000);
  355. clks[VIDEO_PLL_FOUTVCO] = thead_clk_fixed("video_pll_foutvco", 2376000000);
  356. clks[TEE_PLL_FOUTPOSTDIV] = thead_clk_fixed("tee_pll_foutpostdiv", 792000000);
  357. clks[CLKGEN_PERI_I2S_SRC_CLK_0] = thead_clk_fixed("clkgen_peri_i2s_src_clk_0", 294912000); //from audio_pll_foutpostdiv
  358. clks[CLKGEN_PERI_I2S_SRC_CLK_1] = thead_clk_fixed("clkgen_peri_i2s_src_clk_1", 135475200); //from sys_pll_foutpostdiv
  359. clks[CLKGEN_C910_BUS_CLK_NO_ICG] = thead_clk_fixed("clkgen_c910_bus_clk_no_icg", 750000000);
  360. clks[AONSYS_BUS_CLK] = thead_clk_fixed("aonsys_hclk", 101606400); //from sys_pll, maybe change ?
  361. /* Light Fullmask AP MUX */
  362. clks[CPU_PLL0_BYPASS] = thead_light_clk_mux_flags("cpu_pll0_bypass", ap_base + 0x4, 30, 1, cpu_pll0_bypass_sels, ARRAY_SIZE(cpu_pll0_bypass_sels), CLK_SET_RATE_PARENT);
  363. clks[CPU_PLL1_BYPASS] = thead_light_clk_mux_flags("cpu_pll1_bypass", ap_base + 0x14, 30, 1, cpu_pll1_bypass_sels, ARRAY_SIZE(cpu_pll1_bypass_sels), CLK_SET_RATE_PARENT);
  364. clks[GMAC_PLL_BYPASS] = thead_light_clk_mux_flags("gmac_pll_bypass", ap_base + 0x24, 30, 1, gmac_pll_bypass_sels, ARRAY_SIZE(gmac_pll_bypass_sels), CLK_SET_RATE_PARENT);
  365. clks[VIDEO_PLL_BYPASS] = thead_light_clk_mux_flags("video_pll_bypass", ap_base + 0x34, 30, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
  366. clks[TEE_PLL_BYPASS] = thead_light_clk_mux_flags("tee_pll_bypass", ap_base + 0x64, 30, 1, tee_pll_bypass_sels, ARRAY_SIZE(tee_pll_bypass_sels), CLK_SET_RATE_PARENT);
  367. clks[DPU0_PLL_BYPASS] = thead_light_clk_mux_flags("dpu0_pll_bypass", ap_base + 0x44, 30, 1, dpu0_pll_bypass_sels, ARRAY_SIZE(dpu0_pll_bypass_sels), CLK_SET_RATE_PARENT);
  368. clks[DPU1_PLL_BYPASS] = thead_light_clk_mux_flags("dpu1_pll_bypass", ap_base + 0x54, 30, 1, dpu1_pll_bypass_sels, ARRAY_SIZE(dpu1_pll_bypass_sels), CLK_SET_RATE_PARENT);
  369. clks[AHB2_CPUSYS_HCLK] = thead_light_clk_mux_flags("ahb2_cpusys_hclk", ap_base + 0x120, 5, 1, ahb2_cpusys_hclk_sels, ARRAY_SIZE(ahb2_cpusys_hclk_sels), CLK_SET_RATE_PARENT);
  370. clks[C910_CCLK_I0] = thead_light_clk_mux_flags("c910_cclk_i0", ap_base + 0x100, 1, 1, c910_cclk_i0_sels, ARRAY_SIZE(c910_cclk_i0_sels), CLK_SET_RATE_PARENT);
  371. clks[C910_CCLK] = thead_light_clk_mux_flags("c910_cclk", ap_base + 0x100, 0, 1, c910_cclk_sels, ARRAY_SIZE(c910_cclk_sels), CLK_SET_RATE_PARENT);
  372. clks[CFG_AXI_ACLK] = thead_light_clk_mux_flags("cfg_axi_aclk", ap_base + 0x138, 5, 1, cfg_axi_aclk_sels, ARRAY_SIZE(cfg_axi_aclk_sels), CLK_SET_RATE_PARENT);
  373. if (teesys)
  374. clks[TEESYS_HCLK] = thead_light_clk_mux_flags("teesys_hclk", ap_base + 0x1cc, 13, 1, teesys_hclk_sels, ARRAY_SIZE(teesys_hclk_sels), CLK_SET_RATE_PARENT); //just for teesys!!!
  375. clks[PERISYS_AHB_HCLK] = thead_light_clk_mux_flags("perisys_ahb_hclk", ap_base + 0x140, 5, 1, perisys_ahb_hclk_sels, ARRAY_SIZE(perisys_ahb_hclk_sels), CLK_SET_RATE_PARENT);
  376. clks[CLK_OUT_1] = thead_light_clk_mux_flags("clk_out_1", ap_base + 0x1b4, 4, 1, clk_out_1_sels, ARRAY_SIZE(clk_out_1_sels), CLK_SET_RATE_PARENT);
  377. clks[CLK_OUT_2] = thead_light_clk_mux_flags("clk_out_2", ap_base + 0x1b8, 4, 1, clk_out_2_sels, ARRAY_SIZE(clk_out_2_sels), CLK_SET_RATE_PARENT);
  378. clks[CLK_OUT_3] = thead_light_clk_mux_flags("clk_out_3", ap_base + 0x1bc, 4, 1, clk_out_3_sels, ARRAY_SIZE(clk_out_3_sels), CLK_SET_RATE_PARENT);
  379. clks[CLK_OUT_4] = thead_light_clk_mux_flags("clk_out_4", ap_base + 0x1c0, 4, 1, clk_out_4_sels, ARRAY_SIZE(clk_out_4_sels), CLK_SET_RATE_PARENT);
  380. clks[PERI_I2S_SRC_CLK] = thead_light_clk_mux_flags("peri_i2s_src_clk", ap_base + 0x1f0, 0, 1, peri_i2s_src_clk_sels, ARRAY_SIZE(peri_i2s_src_clk_sels), CLK_SET_RATE_PARENT);
  381. clks[NPU_CCLK] = thead_light_clk_mux_flags("npu_cclk", ap_base + 0x1c8, 6, 1, npu_cclk_sels, ARRAY_SIZE(npu_cclk_sels), CLK_SET_RATE_PARENT);
  382. clks[CFG_APB_PCLK] = thead_light_clk_mux_flags("cfg_apb_pclk", ap_base + 0x1c4, 7, 1, cfg_apb_pclk_sels, ARRAY_SIZE(cfg_apb_pclk_sels), CLK_SET_RATE_PARENT);
  383. clks[UART_SCLK] = thead_light_clk_mux_flags("uart_sclk", ap_base + 0x210, 0, 1, uart_sclk_sels, ARRAY_SIZE(uart_sclk_sels), CLK_SET_RATE_PARENT);
  384. /* Light Fullmask AP Divider */
  385. clks[AHB2_CPUSYS_HCLK_OUT_DIV] = thead_clk_light_divider("ahb2_cpusys_hclk_out_div", "gmac_pll_fout1ph0", ap_base + 0x120, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
  386. clks[APB3_CPUSYS_PCLK] = thead_clk_light_divider("apb3_cpusys_pclk", "ahb2_cpusys_hclk", ap_base + 0x130, 0, 3, 3, MUX_TYPE_CDE, 1, 7);
  387. clks[AXI4_CPUSYS2_ACLK] = thead_clk_light_divider("axi4_cpusys2_aclk", "gmac_pll_foutpostdiv", ap_base + 0x134, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
  388. clks[CFG_AXI_ACLK_OUT_DIV] = thead_clk_light_divider("cfg_axi_aclk_out_div", "video_pll_foutpostdiv", ap_base + 0x138, 0, 4, 4, MUX_TYPE_DIV, 2, 15);
  389. if (teesys) {
  390. clks[TEESYS_I0_HCLK] = thead_clk_light_divider("teesys_i0_hclk", "tee_pll_foutpostdiv", ap_base + 0x1cc, 0, 4, 4, MUX_TYPE_DIV, 2, 15); //just for teesys!!!
  391. clks[TEESYS_I1_HCLK] = thead_clk_light_divider("teesys_i1_hclk", "video_pll_foutpostdiv", ap_base + 0x1cc, 8, 4, 12, MUX_TYPE_DIV, 2, 15); //just for teesys!!!
  392. }
  393. clks[PERISYS_AHB_HCLK_OUT_DIV] = thead_clk_light_divider("perisys_ahb_hclk_out_div", "gmac_pll_fout1ph0", ap_base + 0x140, 0, 4, 4, MUX_TYPE_DIV, 2, 7);
  394. clks[PERISYS_APB_PCLK] = thead_clk_light_divider("perisys_apb_pclk", "perisys_ahb_hclk", ap_base + 0x150, 0, 3, 3, MUX_TYPE_CDE, 3, 7);
  395. clks[PERI2SYS_APB_PCLK] = thead_clk_light_divider("peri2sys_apb_pclk", "gmac_pll_fout4", ap_base + 0x150, 4, 3, 8, MUX_TYPE_DIV, 2, 7);
  396. clks[CLK_OUT_1_OUT_DIV] = thead_clk_light_divider("clk_out_1_out_div", "osc_24m", ap_base + 0x1b4, 0, 3, 3, MUX_TYPE_DIV, 2, 4);
  397. clks[CLK_OUT_2_OUT_DIV] = thead_clk_light_divider("clk_out_2_out_div", "osc_24m", ap_base + 0x1b8, 0, 3, 3, MUX_TYPE_DIV, 2, 4);
  398. clks[CLK_OUT_3_OUT_DIV] = thead_clk_light_divider("clk_out_3_out_div", "osc_24m", ap_base + 0x1bc, 0, 3, 3, MUX_TYPE_DIV, 2, 4);
  399. clks[CLK_OUT_4_OUT_DIV] = thead_clk_light_divider("clk_out_4_out_div", "osc_24m", ap_base + 0x1c0, 0, 3, 3, MUX_TYPE_DIV, 2, 4);
  400. clks[VOSYS_ACLK_M] = thead_clk_light_divider("vosys_aclk_m", "video_pll_foutvco", ap_base + 0x1dc, 0, 4, 4, MUX_TYPE_DIV, 3, 15);
  401. clks[NPU_CCLK_OUT_DIV] = thead_clk_light_divider("npu_cclk_out_div", "video_pll_foutvco", ap_base + 0x1c8, 0, 3, 3, MUX_TYPE_DIV, 3, 7);
  402. clks[CFG_APB_PCLK_OUT_DIV] = thead_clk_light_divider("cfg_apb_pclk_out_div", "gmac_pll_foutpostdiv", ap_base + 0x1c4, 0, 4, 4, MUX_TYPE_DIV, 4, 15);
  403. clks[VISYS_ACLK_M] = thead_clk_light_divider("visys_aclk_m", "video_pll_foutvco", ap_base + 0x1d0, 16, 4, 20, MUX_TYPE_DIV, 3, 15);
  404. clks[VISYS_AHB_HCLK] = thead_clk_light_divider("visys_ahb_hclk", "video_pll_foutvco", ap_base + 0x1d0, 0, 4, 4, MUX_TYPE_DIV, 6, 15);
  405. clks[VPSYS_APB_PCLK] = thead_clk_light_divider("vpsys_apb_pclk", "gmac_pll_fout1ph0", ap_base + 0x1e0, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
  406. clks[VPSYS_AXI_ACLK] = thead_clk_light_divider("vpsys_axi_aclk", "video_pll_foutvco", ap_base + 0x1e0, 8, 4, 12, MUX_TYPE_DIV, 3, 15);
  407. clks[VENC_CCLK] = thead_clk_light_divider("venc_cclk", "gmac_pll_foutpostdiv", ap_base + 0x1e4, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
  408. clks[DPU0_PLL_DIV_CLK] = thead_clk_light_divider("dpu0_pll_div_clk", "dpu0_pll_foutpostdiv", ap_base + 0x1e8, 0, 8, 8, MUX_TYPE_DIV, 2, 214);
  409. clks[DPU1_PLL_DIV_CLK] = thead_clk_light_divider("dpu1_pll_div_clk", "dpu1_pll_foutpostdiv", ap_base + 0x1ec, 0, 8, 8, MUX_TYPE_DIV, 2, 214);
  410. /* Light Fullmask PLL FOUT */
  411. clks[GMAC_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("gmac_pll_fout1ph0", "gmac_pll_bypass", 1, 2);
  412. clks[GMAC_PLL_FOUT4] = thead_light_clk_fixed_factor("gmac_pll_fout4", "gmac_pll_bypass", 1, 8);
  413. clks[VIDEO_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("video_pll_fout1ph0", "video_pll_bybass", 1, 2);
  414. clks[VIDEO_PLL_FOUT4] = thead_light_clk_fixed_factor("video_pll_fout4", "video_pll_bypass", 1, 8);
  415. clks[TEE_PLL_FOUT4] = thead_light_clk_fixed_factor("tee_pll_fout4", "tee_pll_bypass", 1, 8);
  416. clks[CPU_PLL0_FOUT4] = thead_light_clk_fixed_factor("cpu_pll0_fout4", "cpu_pll0_bypass", 1, 8);
  417. clks[CPU_PLL1_FOUT4] = thead_light_clk_fixed_factor("cpu_pll1_fout4", "cpu_pll1_bypass", 1, 8);
  418. clks[DPU0_PLL_FOUT4] = thead_light_clk_fixed_factor("dpu0_pll_fout4", "dpu0_pll_bypass", 1, 8);
  419. clks[DPU1_PLL_FOUT4] = thead_light_clk_fixed_factor("dpu1_pll_fout4", "dpu1_pll_bypass", 1, 8);
  420. /* Light Fullmask Fixed Factor */
  421. clks[C910_OSC_CLK] = thead_light_clk_fixed_factor("c910_osc_clk", "osc_24m", 1, 1);
  422. clks[QSPI_SSI_CLK] = thead_light_clk_fixed_factor("qspi_ssi_clk", "video_pll_foutpostdiv", 1, 1); /* Note: no mux to select, use default value */
  423. clks[QSPI0_SSI_CLK] = thead_light_clk_fixed_factor("qspi0_ssi_clk", "qspi_ssi_clk", 1, 1);
  424. clks[QSPI1_SSI_CLK] = thead_light_clk_fixed_factor("qspi1_ssi_clk", "video_pll_fout1ph0", 1, 1);
  425. clks[SPI_SSI_CLK] = thead_light_clk_fixed_factor("spi_ssi_clk", "video_pll_fout1ph0", 1, 1);
  426. clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 1); /* Note: no mux to select, use default value */
  427. clks[PWM_CCLK] = thead_light_clk_fixed_factor("pwm_cclk", "osc_24m", 1, 1);
  428. clks[CHIP_DBG_CCLK] = thead_light_clk_fixed_factor("chip_dbg_cclk", "osc_24m", 1, 1);
  429. clks[GMAC_CCLK] = thead_light_clk_fixed_factor("gmac_cclk", "gmac_pll_fout1ph0", 1, 1);
  430. clks[GPIO0_DBCLK] = thead_light_clk_fixed_factor("gpio0_dbclk", "pad_rtc_clk", 1, 1);
  431. clks[GPIO1_DBCLK] = thead_light_clk_fixed_factor("gpio1_dbclk", "pad_rtc_clk", 1, 1);
  432. clks[GPIO2_DBCLK] = thead_light_clk_fixed_factor("gpio2_dbclk", "pad_rtc_clk", 1, 1);
  433. clks[GPIO3_DBCLK] = thead_light_clk_fixed_factor("gpio3_dbclk", "pad_rtc_clk", 1, 1);
  434. clks[CLK_100M] = thead_light_clk_fixed_factor("clk_100m", "gmac_pll_foutpostdiv", 1, 10);
  435. clks[I2C_IC_CLK] = thead_light_clk_fixed_factor("i2c_ic_clk", "clk_100m", 1, 2);
  436. clks[TIMER_CCLK] = thead_light_clk_fixed_factor("timer_cclk", "osc_24m", 1, 1);
  437. clks[AXI4_CPUSYS1_ACLK] = thead_light_clk_fixed_factor("axi4_cpusys1_aclk", "clkgen_c910_bus_clk_no_icg", 1, 1);
  438. clks[CPU_BUS_DFTCLK] = thead_light_clk_fixed_factor("cpu_bus_dftclk", "cpu_pll0_foutpostdiv", 1, 2);
  439. clks[CPU_PLL0_TEST_CLK] = thead_light_clk_fixed_factor("cpu_pll0_test_clk", "cpu_pll0_fout4", 1, 8);
  440. clks[CPU_PLL1_TEST_CLK] = thead_light_clk_fixed_factor("cpu_pll1_test_clk", "cpu_pll1_fout4", 1, 8);
  441. clks[DPU0_PLL_TEST_CLK] = thead_light_clk_fixed_factor("dpu0_pll_test_clk", "dpu0_pll_fout4", 1, 8);
  442. clks[DPU1_PLL_TEST_CLK] = thead_light_clk_fixed_factor("dpu1_pll_test_clk", "dpu1_pll_fout4", 1, 8);
  443. clks[GMAC_PLL_TEST_CLK] = thead_light_clk_fixed_factor("gmac_pll_test_clk", "gmac_pll_fout4", 1, 8);
  444. clks[VIDEO_PLL_TEST_CLK] = thead_light_clk_fixed_factor("video_pll_test_clk", "video_pll_fout4", 1, 8);
  445. clks[TEE_PLL_TEST_CLK] = thead_light_clk_fixed_factor("tee_pll_test_clk", "tee_pll_fout4", 1, 8);
  446. clks[AONSYS_BUS_CLK] = thead_light_clk_fixed_factor("aonsys_bus_clk", "aonsys_hclk", 1, 1);
  447. /* Light Fullmask Clock Gate */
  448. clks[CLKGEN_AHB2_CPUSYS_HCLK] = thead_clk_light_gate("clkgen_ahb2_cpusys_hclk", "ahb2_cpusys_hclk", ap_base + 0x120, 6);
  449. clks[CLKGEN_APB3_CPUSYS_HCLK] = thead_clk_light_gate("clkgen_apb3_cpusys_hclk", "ahb2_cpusys_hclk", ap_base + 0x130, 4);
  450. clks[CLKGEN_C910_BROM_HCLK] = thead_clk_light_gate("clkgen_c910_brom_hclk", "ahb2_cpusys_hclk", ap_base + 0x100, 4);
  451. clks[CLKGEN_SPINLOCK_HCLK] = thead_clk_light_gate("clkgen_spinlock_hclk", "ahb2_cpusys_hclk", ap_base + 0x208, 10);
  452. clks[CLKGEN_MBOX0_PCLK] = thead_clk_light_gate("clkgen_mbox0_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 7);
  453. clks[CLKGEN_MBOX1_PCLK] = thead_clk_light_gate("clkgen_mbox1_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 6);
  454. clks[CLKGEN_MBOX2_PCLK] = thead_clk_light_gate("clkgen_mbox2_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 5);
  455. clks[CLKGEN_MBOX3_PCLK] = thead_clk_light_gate("clkgen_mbox3_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 4);
  456. clks[CLKGEN_WDT0_PCLK] = thead_clk_light_gate("clkgen_wdt0_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 3);
  457. clks[CLKGEN_WDT1_PCLK] = thead_clk_light_gate("clkgen_wdt1_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 2);
  458. if (teesys)
  459. clks[CLKGEN_MISCSYS_TEE_CCLK] = thead_clk_light_gate("clkgen_miscsys_tee_cclk", "teesys_hclk", ap_base + 0x1cc, 25); //just for teesys!!!
  460. clks[CLKGEN_SRAM_AXI_ACLK_2] = thead_clk_light_gate("clkgen_sram_axi_aclk_2", "axi4_cpusys1_aclk", ap_base + 0x20c, 2);
  461. clks[CLKGEN_PERISYS_AHB_HCLK] = thead_clk_light_gate("clkgen_perisys_ahb_hclk", "perisys_ahb_hclk", ap_base + 0x140, 6);
  462. clks[CLKGEN_PERISYS_APB1_HCLK] = thead_clk_light_gate("clkgen_perisys_apb1_hclk", "perisys_ahb_hclk", ap_base + 0x150, 9);
  463. clks[CLKGEN_PERISYS_APB2_HCLK] = thead_clk_light_gate("clkgen_perisys_apb2_hclk", "perisys_ahb_hclk", ap_base + 0x150, 10);
  464. clks[CLKGEN_PERISYS_APB4_HCLK] = thead_clk_light_gate("clkgen_perisys_apb4_hclk", "perisys_ahb_hclk", ap_base + 0x150, 12);
  465. clks[CLKGEN_PADCTRL0_APSYS_PCLK] = thead_clk_light_gate("clkgen_padctrl0_apsys_pclk", "perisys_ahb_hclk", ap_base + 0x204, 22);
  466. clks[CLKGEN_DSMART_PCLK] = thead_clk_light_gate("clkgen_dsmart_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 23);
  467. clks[CLKGEN_PADCTRL1_APSYS_PCLK] = thead_clk_light_gate("clkgen_padctrl1_apsys_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 24);
  468. clks[CLKGEN_CLK_OUT_1_CLK] = thead_clk_light_gate("clkgen_clk_out_1_clk", "clk_out_1", ap_base + 0x1b4, 5);
  469. clks[CLKGEN_CLK_OUT_2_CLK] = thead_clk_light_gate("clkgen_clk_out_2_clk", "clk_out_2", ap_base + 0x1b8, 5);
  470. clks[CLKGEN_CLK_OUT_3_CLK] = thead_clk_light_gate("clkgen_clk_out_3_clk", "clk_out_3", ap_base + 0x1bc, 5);
  471. clks[CLKGEN_CLK_OUT_4_CLK] = thead_clk_light_gate("clkgen_clk_out_4_clk", "clk_out_4", ap_base + 0x1c0, 5);
  472. clks[CLKGEN_NPUSYS_AXI_ACLK] = thead_clk_light_gate("clkgen_npusys_axi_aclk", "npu_cclk", ap_base + 0x1c8, 5);
  473. clks[CLKGEN_SRAM_AXI_ACLK_0] = thead_clk_light_gate("clkgen_sram_axi_aclk_0", "npu_cclk", ap_base + 0x20c, 4);
  474. clks[CLKGEN_APB_CPU2CFG_HCLK] = thead_clk_light_gate("clkgen_apb_cpu2cfg_hclk", "cfg_apb_pclk", ap_base + 0x1c4, 5);
  475. clks[CLKGEN_SRAM_AXI_ACLK_1] = thead_clk_light_gate("clkgen_sram_axi_aclk_1", "visys_aclk_m", ap_base + 0x20c, 3);
  476. clks[CLKGEN_SRAM_AXI_ACLK_3] = thead_clk_light_gate("clkgen_sram_axi_aclk_3", "vpsys_axi_aclk", ap_base + 0x20c, 1);
  477. clks[CLKGEN_VPSYS_VENC_CCLK] = thead_clk_light_gate("clkgen_vpsys_venc_cclk", "venc_cclk", ap_base + 0x1e4, 5);
  478. clks[CLKGEN_EMMC_SDIO_REF_CLK] = thead_clk_light_gate("clkgen_emmc_sdio_ref_clk", "emmc_sdio_ref_clk", ap_base + 0x204, 30);
  479. clks[CLKGEN_X2H_CPUSYS_MHCLK] = thead_clk_light_gate_shared("clkgen_x2h_cpusys_mhclk", "ahb2_cpusys_hclk", ap_base + 0x120, 7, &share_cnt_x2h_cpusys_clk_en);
  480. clks[CLKGEN_X2H_CPUSYS_ACLK] = thead_clk_light_gate_shared("clkgen_x2h_cpusys_aclk", "cfg_axi_aclk", ap_base + 0x120, 7, &share_cnt_x2h_cpusys_clk_en);
  481. clks[CLKGEN_DMAC_CPUSYS_HCLK] = thead_clk_light_gate_shared("clkgen_dmac_cpusys_hclk", "ahb2_cpusys_hclk", ap_base + 0x208, 8, &share_cnt_dmac_cpusys_clk_en);
  482. clks[CLKGEN_IOPMP_DMAC_CPUSYS_PCLK] = thead_clk_light_gate_shared("clkgen_iopmp_dmac_cpusys_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 8, &share_cnt_dmac_cpusys_clk_en);
  483. clks[CLKGEN_DMAC_CPUSYS_ACLK] = thead_clk_light_gate_shared("clkgen_dmac_cpusys_aclk", "axi4_cpusys2_aclk", ap_base + 0x208, 8, &share_cnt_dmac_cpusys_clk_en);
  484. clks[CLKGEN_TIMER0_PCLK] = thead_clk_light_gate_shared("clkgen_timer0_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 1, &share_cnt_timer0_clk_en);
  485. clks[CLKGEN_TIMER0_CCLK] = thead_clk_light_gate_shared("clkgen_timer0_cclk", "timer_cclk", ap_base + 0x208, 1, &share_cnt_timer0_clk_en);
  486. clks[CLKGEN_TIMER1_PCLK] = thead_clk_light_gate_shared("clkgen_timer1_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 0, &share_cnt_timer1_clk_en);
  487. clks[CLKGEN_TIMER1_CCLK] = thead_clk_light_gate_shared("clkgen_timer1_cclk", "timer_cclk", ap_base + 0x208, 0, &share_cnt_timer1_clk_en);
  488. clks[CLKGEN_AXI4_CPUSYS2_PCLK] = thead_clk_light_gate_shared("clkgen_axi4_cpusys2_pclk", "apb3_cpusys_pclk", ap_base + 0x134, 5, &share_cnt_axi4_cpusys2_clk_en);
  489. clks[CLKGEN_AXI4_CPUSYS2_ACLK] = thead_clk_light_gate_shared("clkgen_axi4_cpusys2_aclk", "axi4_cpusys2_aclk", ap_base + 0x134, 5, &share_cnt_axi4_cpusys2_clk_en);
  490. clks[CLKGEN_BMU_C910_PCLK] = thead_clk_light_gate_shared("clkgen_bmu_c910_pclk", "apb3_cpusys_pclk", ap_base + 0x100, 5, &share_cnt_bmu_c910_clk_en);
  491. clks[CLKGEN_BMU_C910_ACLK] = thead_clk_light_gate_shared("clkgen_bmu_c910_aclk", "axi4_cpusys1_aclk", ap_base + 0x100, 5, &share_cnt_bmu_c910_clk_en);
  492. clks[CLKGEN_IOPMP_AON_PCLK] = thead_clk_light_gate_shared("clkgen_iopmp_aon_pclk", "apb3_cpusys_pclk", ap_base + 0x134, 8, &share_cnt_aon2cpu_a2x_clk_en);
  493. clks[CLKGEN_AON2CPU_A2X_ACLK] = thead_clk_light_gate_shared("clkgen_aon2cpu_a2x_aclk", "axi4_cpusys2_aclk", ap_base + 0x134, 8, &share_cnt_aon2cpu_a2x_clk_en);
  494. clks[CLKGEN_AON2CPU_A2X_HCLK] = thead_clk_light_gate_shared("clkgen_aon2cpu_a2x_hclk", "aonsys_bus_clk", ap_base + 0x134, 8, &share_cnt_aon2cpu_a2x_clk_en);
  495. clks[CLKGEN_IOPMP_CHIP_DBG_PCLK] = thead_clk_light_gate_shared("clkgen_iopmp_chip_dbg_pclk", "apb3_cpusys_pclk", ap_base + 0x208, 9, &share_cnt_chip_dbg_clk_en);
  496. clks[CLKGEN_CHIP_DBG_ACLK] = thead_clk_light_gate_shared("clkgen_chip_dbg_aclk", "axi4_cpusys2_aclk", ap_base + 0x208, 9, &share_cnt_chip_dbg_clk_en);
  497. clks[CLKGEN_CHIP_DBG_CCLK] = thead_clk_light_gate_shared("clkgen_chip_dbg_cclk", "chip_dbg_cclk", ap_base + 0x208, 9, &share_cnt_chip_dbg_clk_en);
  498. clks[CLKGEN_X2X_CPUSYS_ACLK_M] = thead_clk_light_gate_shared("clkgen_x2x_cpusys_aclk_m", "axi4_cpusys2_aclk", ap_base + 0x134, 7, &share_cnt_x2x_cpusys_clk_en);
  499. clks[CLKGEN_X2X_CPUSYS_ACLK_S] = thead_clk_light_gate_shared("clkgen_x2x_cpusys_aclk_s", "axi4_cpusys1_aclk", ap_base + 0x134, 7, &share_cnt_x2x_cpusys_clk_en);
  500. clks[CLKGEN_CPU2PERI_X2H_ACLK] = thead_clk_light_gate_shared("clkgen_cpu2peri_x2h_aclk", "axi4_cpusys1_aclk", ap_base + 0x140, 9, &share_cnt_cpu2peri_x2h_clk_en);
  501. clks[CLKGEN_CPU2PERI_X2H_MHCLK] = thead_clk_light_gate_shared("clkgen_cpu2peri_x2h_mhclk", "perisys_ahb_hclk", ap_base + 0x140, 9, &share_cnt_cpu2peri_x2h_clk_en);
  502. clks[CLKGEN_CPU2VI_X2H_ACLK] = thead_clk_light_gate_shared("clkgen_cpu2vi_x2h_aclk", "axi4_cpusys1_aclk", ap_base + 0x1d0, 21, &share_cnt_cpu2vi_x2h_clk_en);
  503. clks[CLKGEN_CPU2VI_X2H_MHCLK] = thead_clk_light_gate_shared("clkgen_cpu2vi_x2h_mhclk", "visys_ahb_hclk", ap_base + 0x1d0, 21, &share_cnt_cpu2vi_x2h_clk_en);
  504. clks[CLKGEN_CFG2TEE_X2H_ACLK] = thead_clk_light_gate_shared("clkgen_cfg2tee_x2h_aclk", "cfg_axi_aclk", ap_base + 0x1cc, 24, &share_cnt_cfg2tee_x2h_clk_en); // just for teesys!!!
  505. clks[CLKGEN_CFG2TEE_X2H_MHCLK] = thead_clk_light_gate_shared("clkgen_cfg2tee_x2h_mhclk", "teesys_hclk", ap_base + 0x1cc, 24, &share_cnt_cfg2tee_x2h_clk_en); // just for teesys!!!
  506. clks[CLKGEN_CPU2AON_X2H_ACLK] = thead_clk_light_gate_shared("clkgen_cpu2aon_x2h_aclk", "cfg_axi_aclk", ap_base + 0x138, 8, &share_cnt_cpu2aon_x2h_clk_en);
  507. clks[CLKGEN_CPU2AON_X2H_MHCLK] = thead_clk_light_gate_shared("clkgen_cpu2aon_x2h_mhclk", "aonsys_bus_clk", ap_base + 0x138, 8, &share_cnt_cpu2aon_x2h_clk_en);
  508. clks[CLKGEN_CPU2VP_X2P_ACLK] = thead_clk_light_gate_shared("clkgen_cpu2vp_x2p_aclk", "cfg_axi_aclk", ap_base + 0x1e0, 13, &share_cnt_cpu2vp_x2p_clk_en);
  509. clks[CLKGEN_CPU2VP_X2P_PCLK] = thead_clk_light_gate_shared("clkgen_cpu2vp_x2p_pclk", "vpsys_apb_pclk", ap_base + 0x1e0, 13, &share_cnt_cpu2vp_x2p_clk_en);
  510. clks[CLKGEN_TOP_AXI4S_ACLK] = thead_clk_light_gate_shared("clkgen_top_axi4s_aclk", "cfg_axi_aclk", ap_base + 0x1c8, 4, &share_cnt_npu_core_clk_en);
  511. clks[CLKGEN_TOP_APB_SX_PCLK] = thead_clk_light_gate_shared("clkgen_top_apb_sx_pclk", "cfg_apb_pclk", ap_base + 0x1c8, 4, &share_cnt_npu_core_clk_en);
  512. clks[CLKGEN_MISC2VP_X2X_ACLK_M] = thead_clk_light_gate_shared("clkgen_misc2vp_x2x_aclk_m", "perisys_ahb_hclk", ap_base + 0x1e0, 15, &share_cnt_vpsys_axi_aclk_en);
  513. clks[CLKGEN_VPSYS_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_aclk", "vpsys_axi_aclk", ap_base + 0x1e0, 15, &share_cnt_vpsys_axi_aclk_en);
  514. clks[CLKGEN_GMAC1_HCLK] = thead_clk_light_gate_shared("clkgen_gmac1_hclk", "perisys_ahb_hclk", ap_base + 0x204, 26, &share_cnt_gmac1_clk_en);
  515. clks[CLKGEN_GMAC1_PCLK] = thead_clk_light_gate_shared("clkgen_gmac1_pclk", "perisys_ahb_hclk", ap_base + 0x204, 26, &share_cnt_gmac1_clk_en);
  516. clks[CLKGEN_GMAC1_CCLK] = thead_clk_light_gate_shared("clkgen_gmac1_cclk", "gmac_cclk", ap_base + 0x204, 26, &share_cnt_gmac1_clk_en);
  517. clks[CLKGEN_GMAC0_HCLK] = thead_clk_light_gate_shared("clkgen_gmac0_hclk", "perisys_ahb_hclk", ap_base + 0x204, 19, &share_cnt_gmac0_clk_en);
  518. clks[CLKGEN_GMAC0_PCLK] = thead_clk_light_gate_shared("clkgen_gmac0_pclk", "perisys_ahb_hclk", ap_base + 0x204, 19, &share_cnt_gmac0_clk_en);
  519. clks[CLKGEN_GMAC0_CCLK] = thead_clk_light_gate_shared("clkgen_gmac0_cclk", "gmac_cclk", ap_base + 0x204, 19, &share_cnt_gmac0_clk_en);
  520. clks[CLKGEN_PERI2PERI1_APB_HCLK] = thead_clk_light_gate_shared("clkgen_peri2peri1_apb_hclk", "perisys_ahb_hclk", ap_base + 0x150, 11, &share_cnt_perisys_apb3_hclk_en);
  521. clks[CLKGEN_PERI2PERI1_APB_PCLK] = thead_clk_light_gate_shared("clkgen_peri2peri1_apb_pclk", "peri2sys_apb_pclk", ap_base + 0x150, 11, &share_cnt_perisys_apb3_hclk_en);
  522. clks[CLKGEN_QSPI0_PCLK] = thead_clk_light_gate_shared("clkgen_qspi0_pclk", "perisys_ahb_hclk", ap_base + 0x204, 17, &share_cnt_qspi0_clk_en);
  523. clks[CLKGEN_QSPI0_SSI_CLK] = thead_clk_light_gate_shared("clkgen_qspi0_ssi_clk", "qspi0_ssi_clk", ap_base + 0x204, 17, &share_cnt_qspi0_clk_en);
  524. clks[CLKGEN_GMAC_AXI_ACLK] = thead_clk_light_gate_shared("clkgen_gmac_axi_aclk", "perisys_ahb_hclk", ap_base + 0x204, 21, &share_cnt_gmac_axi_clk_en);
  525. clks[CLKGEN_GMAC_AXI_PCLK] = thead_clk_light_gate_shared("clkgen_gmac_axi_pclk", "perisys_ahb_hclk", ap_base + 0x204, 21, &share_cnt_gmac_axi_clk_en);
  526. clks[CLKGEN_GPIO0_PCLK] = thead_clk_light_gate_shared("clkgen_gpio0_pclk", "perisys_ahb_hclk", ap_base + 0x204, 8, &share_cnt_gpio0_clk_en);
  527. clks[CLKGEN_GPIO0_DBCLK] = thead_clk_light_gate_shared("clkgen_gpio0_dbclk", "gpio0_dbclk", ap_base + 0x204, 8, &share_cnt_gpio0_clk_en);
  528. clks[CLKGEN_GPIO1_PCLK] = thead_clk_light_gate_shared("clkgen_gpio1_pclk", "perisys_ahb_hclk", ap_base + 0x204, 7, &share_cnt_gpio0_clk_en);
  529. clks[CLKGEN_GPIO1_DBCLK] = thead_clk_light_gate_shared("clkgen_gpio1_dbclk", "gpio1_dbclk", ap_base + 0x204, 7, &share_cnt_gpio1_clk_en);
  530. clks[CLKGEN_PWM_PCLK] = thead_clk_light_gate_shared("clkgen_pwm_pclk", "perisys_apb_pclk", ap_base + 0x204, 18, &share_cnt_pwm_clk_en);
  531. clks[CLKGEN_PWM_CCLK] = thead_clk_light_gate_shared("clkgen_pwm_cclk", "pwm_cclk", ap_base + 0x204, 18, &share_cnt_pwm_clk_en);
  532. clks[CLKGEN_SPI_PCLK] = thead_clk_light_gate_shared("clkgen_spi_pclk", "perisys_apb_pclk", ap_base + 0x204, 15, &share_cnt_spi_clk_en);
  533. clks[CLKGEN_SPI_SSI_CLK] = thead_clk_light_gate_shared("clkgen_spi_ssi_clk", "spi_ssi_clk", ap_base + 0x204, 15, &share_cnt_spi_clk_en);
  534. clks[CLKGEN_UART0_PCLK] = thead_clk_light_gate_shared("clkgen_uart0_pclk", "perisys_apb_pclk", ap_base + 0x204, 14, &share_cnt_uart0_clk_en);
  535. clks[CLKGEN_UART0_SCLK] = thead_clk_light_gate_shared("clkgen_uart0_sclk", "uart_sclk", ap_base + 0x204, 14, &share_cnt_uart0_clk_en);
  536. clks[CLKGEN_UART2_PCLK] = thead_clk_light_gate_shared("clkgen_uart2_pclk", "perisys_apb_pclk", ap_base + 0x204, 12, &share_cnt_uart2_clk_en);
  537. clks[CLKGEN_UART2_SCLK] = thead_clk_light_gate_shared("clkgen_uart2_sclk", "uart_sclk", ap_base + 0x204, 12, &share_cnt_uart2_clk_en);
  538. clks[CLKGEN_I2C2_PCLK] = thead_clk_light_gate_shared("clkgen_i2c2_pclk", "perisys_apb_pclk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
  539. clks[CLKGEN_I2C2_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c2_ic_clk", "i2c_ic_clk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
  540. clks[CLKGEN_I2C3_PCLK] = thead_clk_light_gate_shared("clkgen_i2c3_pclk", "perisys_apb_pclk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
  541. clks[CLKGEN_I2C3_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c3_ic_clk", "i2c_ic_clk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
  542. clks[CLKGEN_I2S_PCLK] = thead_clk_light_gate_shared("clkgen_i2s_pclk", "perisys_apb_pclk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
  543. clks[CLKGEN_I2S_SRC_CLK] = thead_clk_light_gate_shared("clkgen_i2s_src_clk", "peri_i2s_src_clk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
  544. clks[CLKGEN_QSPI1_PCLK] = thead_clk_light_gate_shared("clkgen_qspi1_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 16, &share_cnt_qspi1_clk_en);
  545. clks[CLKGEN_QSPI1_SSI_CLK] = thead_clk_light_gate_shared("clkgen_qspi1_ssi_clk", "qspi1_ssi_clk", ap_base + 0x204, 16, &share_cnt_qspi1_clk_en);
  546. clks[CLKGEN_UART1_PCLK] = thead_clk_light_gate_shared("clkgen_uart1_pclk", "per2sys_apb_pclk", ap_base + 0x204, 13, &share_cnt_uart1_clk_en);
  547. clks[CLKGEN_UART1_SCLK] = thead_clk_light_gate_shared("clkgen_uart1_sclk", "uart_sclk", ap_base + 0x204, 13, &share_cnt_uart1_clk_en);
  548. clks[CLKGEN_UART3_PCLK] = thead_clk_light_gate_shared("clkgen_uart3_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 11, &share_cnt_uart3_clk_en);
  549. clks[CLKGEN_UART3_SCLK] = thead_clk_light_gate_shared("clkgen_uart3_sclk", "uart_sclk", ap_base + 0x204, 11, &share_cnt_uart3_clk_en);
  550. clks[CLKGEN_UART4_PCLK] = thead_clk_light_gate_shared("clkgen_uart4_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 10, &share_cnt_uart4_clk_en);
  551. clks[CLKGEN_UART4_SCLK] = thead_clk_light_gate_shared("clkgen_uart4_sclk", "uart_sclk", ap_base + 0x204, 10, &share_cnt_uart4_clk_en);
  552. clks[CLKGEN_UART5_PCLK] = thead_clk_light_gate_shared("clkgen_uart5_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 9, &share_cnt_uart5_clk_en);
  553. clks[CLKGEN_UART5_SCLK] = thead_clk_light_gate_shared("clkgen_uart5_sclk", "uart_sclk", ap_base + 0x204, 9, &share_cnt_uart5_clk_en);
  554. clks[CLKGEN_I2C0_PCLK] = thead_clk_light_gate_shared("clkgen_i2c0_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 5, &share_cnt_i2c0_clk_en);
  555. clks[CLKGEN_I2C0_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c0_ic_clk", "i2c_ic_clk", ap_base + 0x204, 5, &share_cnt_i2c0_clk_en);
  556. clks[CLKGEN_I2C1_PCLK] = thead_clk_light_gate_shared("clkgen_i2c1_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 4, &share_cnt_i2c1_clk_en);
  557. clks[CLKGEN_I2C1_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c1_ic_clk", "i2c_ic_clk", ap_base + 0x204, 4, &share_cnt_i2c1_clk_en);
  558. clks[CLKGEN_I2C4_PCLK] = thead_clk_light_gate_shared("clkgen_i2c4_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 1, &share_cnt_i2c4_clk_en);
  559. clks[CLKGEN_I2C4_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c4_ic_clk", "i2c_ic_clk", ap_base + 0x204, 1, &share_cnt_i2c4_clk_en);
  560. clks[CLKGEN_I2C5_PCLK] = thead_clk_light_gate_shared("clkgen_i2c5_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 0, &share_cnt_i2c5_clk_en);
  561. clks[CLKGEN_I2C5_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c5_ic_clk", "i2c_ic_clk", ap_base + 0x204, 0, &share_cnt_i2c5_clk_en);
  562. clks[CLKGEN_GPIO2_PCLK] = thead_clk_light_gate_shared("clkgen_gpio2_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 6, &share_cnt_gpio2_clk_en);
  563. clks[CLKGEN_GPIO2_DBCLK] = thead_clk_light_gate_shared("clkgen_gpio2_dbclk", "gpio2_dbclk", ap_base + 0x204, 6, &share_cnt_gpio2_clk_en);
  564. clks[CLKGEN_GPIO3_PCLK] = thead_clk_light_gate_shared("clkgen_gpio3_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 6, &share_cnt_gpio2_clk_en); //!!! gpio3 pclk is controlled by gpio2_clk_en
  565. clks[CLKGEN_GPIO3_DBCLK] = thead_clk_light_gate_shared("clkgen_gpio3_dbclk", "gpio3_dbclk", ap_base + 0x204, 20, &share_cnt_gpio3_clk_en);
  566. clks[CLKGEN_VOSYS_AXI_ACLK] = thead_clk_light_gate_shared("clkgen_vosys_axi_aclk", "vosys_aclk_m", ap_base + 0x1dc, 5, &share_cnt_vosys_axi_aclk_en);
  567. clks[CLKGEN_VOSYS_X2X_ACLK_S] = thead_clk_light_gate_shared("clkgen_vosys_x2x_aclk_s", "npu_cclk", ap_base + 0x1dc, 5, &share_cnt_vosys_axi_aclk_en);
  568. clk_data.clks = clks;
  569. clk_data.clk_num = ARRAY_SIZE(clks);
  570. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  571. if (ret < 0) {
  572. dev_err(dev, "failed to register clks for light\n");
  573. goto unregister_clks;
  574. }
  575. #ifndef FPGA_EMU
  576. /* HW defalut */
  577. clk_prepare_enable(clks[CPU_PLL1_FOUTPOSTDIV]);
  578. udelay(1);
  579. clk_set_parent(clks[C910_CCLK], clks[CPU_PLL1_FOUTPOSTDIV]);
  580. #else
  581. clk_set_parent(clks[C910_CCLK_I0], clks[OSC_24M]);
  582. clk_set_parent(clks[C910_CCLK], clks[C910_CCLK_I0]);
  583. #endif
  584. dev_info(dev, "succeed to register light fullmask clock driver\n");
  585. return 0;
  586. unregister_clks:
  587. thead_unregister_clocks(clks, ARRAY_SIZE(clks));
  588. return ret;
  589. }
  590. const bool tee_sys_flag;
  591. static const struct of_device_id light_clk_of_match[] = {
  592. { .compatible = "thead,light-fm-ree-clk" },
  593. { .compatible = "thead,light-fm-tee-clk", .data = &tee_sys_flag,},
  594. { /* Sentinel */ },
  595. };
  596. MODULE_DEVICE_TABLE(of, light_clk_of_match);
  597. static struct platform_driver light_clk_driver = {
  598. .probe = light_clocks_probe,
  599. .driver = {
  600. .name = "light-fm-clk",
  601. .of_match_table = of_match_ptr(light_clk_of_match),
  602. },
  603. };
  604. module_platform_driver(light_clk_driver);
  605. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  606. MODULE_DESCRIPTION("Thead Light Fullmask clock driver");
  607. MODULE_LICENSE("GPL v2");