clk-tegra30.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/clkdev.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/clk/tegra.h>
  12. #include <soc/tegra/pmc.h>
  13. #include <dt-bindings/clock/tegra30-car.h>
  14. #include "clk.h"
  15. #include "clk-id.h"
  16. #define OSC_CTRL 0x50
  17. #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
  18. #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
  19. #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
  20. #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
  21. #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
  22. #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
  23. #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
  24. #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
  25. #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
  26. #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
  27. #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
  28. #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
  29. #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
  30. #define OSC_FREQ_DET 0x58
  31. #define OSC_FREQ_DET_TRIG BIT(31)
  32. #define OSC_FREQ_DET_STATUS 0x5c
  33. #define OSC_FREQ_DET_BUSY BIT(31)
  34. #define OSC_FREQ_DET_CNT_MASK 0xffff
  35. #define CCLKG_BURST_POLICY 0x368
  36. #define SUPER_CCLKG_DIVIDER 0x36c
  37. #define CCLKLP_BURST_POLICY 0x370
  38. #define SUPER_CCLKLP_DIVIDER 0x374
  39. #define SCLK_BURST_POLICY 0x028
  40. #define SUPER_SCLK_DIVIDER 0x02c
  41. #define SYSTEM_CLK_RATE 0x030
  42. #define TEGRA30_CLK_PERIPH_BANKS 5
  43. #define PLLC_BASE 0x80
  44. #define PLLC_MISC 0x8c
  45. #define PLLM_BASE 0x90
  46. #define PLLM_MISC 0x9c
  47. #define PLLP_BASE 0xa0
  48. #define PLLP_MISC 0xac
  49. #define PLLX_BASE 0xe0
  50. #define PLLX_MISC 0xe4
  51. #define PLLD_BASE 0xd0
  52. #define PLLD_MISC 0xdc
  53. #define PLLD2_BASE 0x4b8
  54. #define PLLD2_MISC 0x4bc
  55. #define PLLE_BASE 0xe8
  56. #define PLLE_MISC 0xec
  57. #define PLLA_BASE 0xb0
  58. #define PLLA_MISC 0xbc
  59. #define PLLU_BASE 0xc0
  60. #define PLLU_MISC 0xcc
  61. #define PLL_MISC_LOCK_ENABLE 18
  62. #define PLLDU_MISC_LOCK_ENABLE 22
  63. #define PLLE_MISC_LOCK_ENABLE 9
  64. #define PLL_BASE_LOCK BIT(27)
  65. #define PLLE_MISC_LOCK BIT(11)
  66. #define PLLE_AUX 0x48c
  67. #define PLLC_OUT 0x84
  68. #define PLLM_OUT 0x94
  69. #define PLLP_OUTA 0xa4
  70. #define PLLP_OUTB 0xa8
  71. #define PLLA_OUT 0xb4
  72. #define AUDIO_SYNC_CLK_I2S0 0x4a0
  73. #define AUDIO_SYNC_CLK_I2S1 0x4a4
  74. #define AUDIO_SYNC_CLK_I2S2 0x4a8
  75. #define AUDIO_SYNC_CLK_I2S3 0x4ac
  76. #define AUDIO_SYNC_CLK_I2S4 0x4b0
  77. #define AUDIO_SYNC_CLK_SPDIF 0x4b4
  78. #define CLK_SOURCE_SPDIF_OUT 0x108
  79. #define CLK_SOURCE_PWM 0x110
  80. #define CLK_SOURCE_D_AUDIO 0x3d0
  81. #define CLK_SOURCE_DAM0 0x3d8
  82. #define CLK_SOURCE_DAM1 0x3dc
  83. #define CLK_SOURCE_DAM2 0x3e0
  84. #define CLK_SOURCE_3D2 0x3b0
  85. #define CLK_SOURCE_2D 0x15c
  86. #define CLK_SOURCE_HDMI 0x18c
  87. #define CLK_SOURCE_DSIB 0xd0
  88. #define CLK_SOURCE_SE 0x42c
  89. #define CLK_SOURCE_EMC 0x19c
  90. #define AUDIO_SYNC_DOUBLER 0x49c
  91. /* Tegra CPU clock and reset control regs */
  92. #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
  93. #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
  94. #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
  95. #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
  96. #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
  97. #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
  98. #define CPU_RESET(cpu) (0x1111ul << (cpu))
  99. #define CLK_RESET_CCLK_BURST 0x20
  100. #define CLK_RESET_CCLK_DIVIDER 0x24
  101. #define CLK_RESET_PLLX_BASE 0xe0
  102. #define CLK_RESET_PLLX_MISC 0xe4
  103. #define CLK_RESET_SOURCE_CSITE 0x1d4
  104. #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
  105. #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
  106. #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
  107. #define CLK_RESET_CCLK_IDLE_POLICY 1
  108. #define CLK_RESET_CCLK_RUN_POLICY 2
  109. #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
  110. /* PLLM override registers */
  111. #define PMC_PLLM_WB0_OVERRIDE 0x1dc
  112. #ifdef CONFIG_PM_SLEEP
  113. static struct cpu_clk_suspend_context {
  114. u32 pllx_misc;
  115. u32 pllx_base;
  116. u32 cpu_burst;
  117. u32 clk_csite_src;
  118. u32 cclk_divider;
  119. } tegra30_cpu_clk_sctx;
  120. #endif
  121. static void __iomem *clk_base;
  122. static void __iomem *pmc_base;
  123. static unsigned long input_freq;
  124. static DEFINE_SPINLOCK(cml_lock);
  125. static DEFINE_SPINLOCK(pll_d_lock);
  126. #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
  127. _clk_num, _gate_flags, _clk_id) \
  128. TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
  129. 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
  130. _clk_num, _gate_flags, _clk_id)
  131. #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
  132. _clk_num, _gate_flags, _clk_id) \
  133. TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
  134. 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
  135. _clk_num, _gate_flags, _clk_id)
  136. #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
  137. _clk_num, _gate_flags, _clk_id) \
  138. TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
  139. 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
  140. TEGRA_DIVIDER_ROUND_UP, _clk_num, \
  141. _gate_flags, _clk_id)
  142. #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
  143. _mux_shift, _mux_width, _clk_num, \
  144. _gate_flags, _clk_id) \
  145. TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
  146. _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
  147. _clk_num, _gate_flags, \
  148. _clk_id)
  149. static struct clk **clks;
  150. static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
  151. { 12000000, 1040000000, 520, 6, 1, 8 },
  152. { 13000000, 1040000000, 480, 6, 1, 8 },
  153. { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
  154. { 19200000, 1040000000, 325, 6, 1, 6 },
  155. { 26000000, 1040000000, 520, 13, 1, 8 },
  156. { 12000000, 832000000, 416, 6, 1, 8 },
  157. { 13000000, 832000000, 832, 13, 1, 8 },
  158. { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
  159. { 19200000, 832000000, 260, 6, 1, 8 },
  160. { 26000000, 832000000, 416, 13, 1, 8 },
  161. { 12000000, 624000000, 624, 12, 1, 8 },
  162. { 13000000, 624000000, 624, 13, 1, 8 },
  163. { 16800000, 600000000, 520, 14, 1, 8 },
  164. { 19200000, 624000000, 520, 16, 1, 8 },
  165. { 26000000, 624000000, 624, 26, 1, 8 },
  166. { 12000000, 600000000, 600, 12, 1, 8 },
  167. { 13000000, 600000000, 600, 13, 1, 8 },
  168. { 16800000, 600000000, 500, 14, 1, 8 },
  169. { 19200000, 600000000, 375, 12, 1, 6 },
  170. { 26000000, 600000000, 600, 26, 1, 8 },
  171. { 12000000, 520000000, 520, 12, 1, 8 },
  172. { 13000000, 520000000, 520, 13, 1, 8 },
  173. { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
  174. { 19200000, 520000000, 325, 12, 1, 6 },
  175. { 26000000, 520000000, 520, 26, 1, 8 },
  176. { 12000000, 416000000, 416, 12, 1, 8 },
  177. { 13000000, 416000000, 416, 13, 1, 8 },
  178. { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
  179. { 19200000, 416000000, 260, 12, 1, 6 },
  180. { 26000000, 416000000, 416, 26, 1, 8 },
  181. { 0, 0, 0, 0, 0, 0 },
  182. };
  183. static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
  184. { 12000000, 666000000, 666, 12, 1, 8 },
  185. { 13000000, 666000000, 666, 13, 1, 8 },
  186. { 16800000, 666000000, 555, 14, 1, 8 },
  187. { 19200000, 666000000, 555, 16, 1, 8 },
  188. { 26000000, 666000000, 666, 26, 1, 8 },
  189. { 12000000, 600000000, 600, 12, 1, 8 },
  190. { 13000000, 600000000, 600, 13, 1, 8 },
  191. { 16800000, 600000000, 500, 14, 1, 8 },
  192. { 19200000, 600000000, 375, 12, 1, 6 },
  193. { 26000000, 600000000, 600, 26, 1, 8 },
  194. { 0, 0, 0, 0, 0, 0 },
  195. };
  196. static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
  197. { 12000000, 216000000, 432, 12, 2, 8 },
  198. { 13000000, 216000000, 432, 13, 2, 8 },
  199. { 16800000, 216000000, 360, 14, 2, 8 },
  200. { 19200000, 216000000, 360, 16, 2, 8 },
  201. { 26000000, 216000000, 432, 26, 2, 8 },
  202. { 0, 0, 0, 0, 0, 0 },
  203. };
  204. static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
  205. { 9600000, 564480000, 294, 5, 1, 4 },
  206. { 9600000, 552960000, 288, 5, 1, 4 },
  207. { 9600000, 24000000, 5, 2, 1, 1 },
  208. { 28800000, 56448000, 49, 25, 1, 1 },
  209. { 28800000, 73728000, 64, 25, 1, 1 },
  210. { 28800000, 24000000, 5, 6, 1, 1 },
  211. { 0, 0, 0, 0, 0, 0 },
  212. };
  213. static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
  214. { 12000000, 216000000, 216, 12, 1, 4 },
  215. { 13000000, 216000000, 216, 13, 1, 4 },
  216. { 16800000, 216000000, 180, 14, 1, 4 },
  217. { 19200000, 216000000, 180, 16, 1, 4 },
  218. { 26000000, 216000000, 216, 26, 1, 4 },
  219. { 12000000, 594000000, 594, 12, 1, 8 },
  220. { 13000000, 594000000, 594, 13, 1, 8 },
  221. { 16800000, 594000000, 495, 14, 1, 8 },
  222. { 19200000, 594000000, 495, 16, 1, 8 },
  223. { 26000000, 594000000, 594, 26, 1, 8 },
  224. { 12000000, 1000000000, 1000, 12, 1, 12 },
  225. { 13000000, 1000000000, 1000, 13, 1, 12 },
  226. { 19200000, 1000000000, 625, 12, 1, 8 },
  227. { 26000000, 1000000000, 1000, 26, 1, 12 },
  228. { 0, 0, 0, 0, 0, 0 },
  229. };
  230. static const struct pdiv_map pllu_p[] = {
  231. { .pdiv = 1, .hw_val = 1 },
  232. { .pdiv = 2, .hw_val = 0 },
  233. { .pdiv = 0, .hw_val = 0 },
  234. };
  235. static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
  236. { 12000000, 480000000, 960, 12, 2, 12 },
  237. { 13000000, 480000000, 960, 13, 2, 12 },
  238. { 16800000, 480000000, 400, 7, 2, 5 },
  239. { 19200000, 480000000, 200, 4, 2, 3 },
  240. { 26000000, 480000000, 960, 26, 2, 12 },
  241. { 0, 0, 0, 0, 0, 0 },
  242. };
  243. static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
  244. /* 1.7 GHz */
  245. { 12000000, 1700000000, 850, 6, 1, 8 },
  246. { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
  247. { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
  248. { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
  249. { 26000000, 1700000000, 850, 13, 1, 8 },
  250. /* 1.6 GHz */
  251. { 12000000, 1600000000, 800, 6, 1, 8 },
  252. { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
  253. { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
  254. { 19200000, 1600000000, 500, 6, 1, 8 },
  255. { 26000000, 1600000000, 800, 13, 1, 8 },
  256. /* 1.5 GHz */
  257. { 12000000, 1500000000, 750, 6, 1, 8 },
  258. { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
  259. { 16800000, 1500000000, 625, 7, 1, 8 },
  260. { 19200000, 1500000000, 625, 8, 1, 8 },
  261. { 26000000, 1500000000, 750, 13, 1, 8 },
  262. /* 1.4 GHz */
  263. { 12000000, 1400000000, 700, 6, 1, 8 },
  264. { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
  265. { 16800000, 1400000000, 1000, 12, 1, 8 },
  266. { 19200000, 1400000000, 875, 12, 1, 8 },
  267. { 26000000, 1400000000, 700, 13, 1, 8 },
  268. /* 1.3 GHz */
  269. { 12000000, 1300000000, 975, 9, 1, 8 },
  270. { 13000000, 1300000000, 1000, 10, 1, 8 },
  271. { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
  272. { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
  273. { 26000000, 1300000000, 650, 13, 1, 8 },
  274. /* 1.2 GHz */
  275. { 12000000, 1200000000, 1000, 10, 1, 8 },
  276. { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
  277. { 16800000, 1200000000, 1000, 14, 1, 8 },
  278. { 19200000, 1200000000, 1000, 16, 1, 8 },
  279. { 26000000, 1200000000, 600, 13, 1, 8 },
  280. /* 1.1 GHz */
  281. { 12000000, 1100000000, 825, 9, 1, 8 },
  282. { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
  283. { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
  284. { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
  285. { 26000000, 1100000000, 550, 13, 1, 8 },
  286. /* 1 GHz */
  287. { 12000000, 1000000000, 1000, 12, 1, 8 },
  288. { 13000000, 1000000000, 1000, 13, 1, 8 },
  289. { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
  290. { 19200000, 1000000000, 625, 12, 1, 8 },
  291. { 26000000, 1000000000, 1000, 26, 1, 8 },
  292. { 0, 0, 0, 0, 0, 0 },
  293. };
  294. static const struct pdiv_map plle_p[] = {
  295. { .pdiv = 18, .hw_val = 18 },
  296. { .pdiv = 24, .hw_val = 24 },
  297. { .pdiv = 0, .hw_val = 0 },
  298. };
  299. static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
  300. /* PLLE special case: use cpcon field to store cml divider value */
  301. { 12000000, 100000000, 150, 1, 18, 11 },
  302. { 216000000, 100000000, 200, 18, 24, 13 },
  303. { 0, 0, 0, 0, 0, 0 },
  304. };
  305. /* PLL parameters */
  306. static struct tegra_clk_pll_params pll_c_params __ro_after_init = {
  307. .input_min = 2000000,
  308. .input_max = 31000000,
  309. .cf_min = 1000000,
  310. .cf_max = 6000000,
  311. .vco_min = 20000000,
  312. .vco_max = 1400000000,
  313. .base_reg = PLLC_BASE,
  314. .misc_reg = PLLC_MISC,
  315. .lock_mask = PLL_BASE_LOCK,
  316. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  317. .lock_delay = 300,
  318. .freq_table = pll_c_freq_table,
  319. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
  320. TEGRA_PLL_HAS_LOCK_ENABLE,
  321. };
  322. static struct div_nmp pllm_nmp = {
  323. .divn_shift = 8,
  324. .divn_width = 10,
  325. .override_divn_shift = 5,
  326. .divm_shift = 0,
  327. .divm_width = 5,
  328. .override_divm_shift = 0,
  329. .divp_shift = 20,
  330. .divp_width = 3,
  331. .override_divp_shift = 15,
  332. };
  333. static struct tegra_clk_pll_params pll_m_params __ro_after_init = {
  334. .input_min = 2000000,
  335. .input_max = 31000000,
  336. .cf_min = 1000000,
  337. .cf_max = 6000000,
  338. .vco_min = 20000000,
  339. .vco_max = 1200000000,
  340. .base_reg = PLLM_BASE,
  341. .misc_reg = PLLM_MISC,
  342. .lock_mask = PLL_BASE_LOCK,
  343. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  344. .lock_delay = 300,
  345. .div_nmp = &pllm_nmp,
  346. .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
  347. .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
  348. .freq_table = pll_m_freq_table,
  349. .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
  350. TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
  351. TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
  352. };
  353. static struct tegra_clk_pll_params pll_p_params __ro_after_init = {
  354. .input_min = 2000000,
  355. .input_max = 31000000,
  356. .cf_min = 1000000,
  357. .cf_max = 6000000,
  358. .vco_min = 20000000,
  359. .vco_max = 1400000000,
  360. .base_reg = PLLP_BASE,
  361. .misc_reg = PLLP_MISC,
  362. .lock_mask = PLL_BASE_LOCK,
  363. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  364. .lock_delay = 300,
  365. .freq_table = pll_p_freq_table,
  366. .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
  367. TEGRA_PLL_HAS_LOCK_ENABLE,
  368. .fixed_rate = 408000000,
  369. };
  370. static struct tegra_clk_pll_params pll_a_params = {
  371. .input_min = 2000000,
  372. .input_max = 31000000,
  373. .cf_min = 1000000,
  374. .cf_max = 6000000,
  375. .vco_min = 20000000,
  376. .vco_max = 1400000000,
  377. .base_reg = PLLA_BASE,
  378. .misc_reg = PLLA_MISC,
  379. .lock_mask = PLL_BASE_LOCK,
  380. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  381. .lock_delay = 300,
  382. .freq_table = pll_a_freq_table,
  383. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
  384. TEGRA_PLL_HAS_LOCK_ENABLE,
  385. };
  386. static struct tegra_clk_pll_params pll_d_params __ro_after_init = {
  387. .input_min = 2000000,
  388. .input_max = 40000000,
  389. .cf_min = 1000000,
  390. .cf_max = 6000000,
  391. .vco_min = 40000000,
  392. .vco_max = 1000000000,
  393. .base_reg = PLLD_BASE,
  394. .misc_reg = PLLD_MISC,
  395. .lock_mask = PLL_BASE_LOCK,
  396. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  397. .lock_delay = 1000,
  398. .freq_table = pll_d_freq_table,
  399. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  400. TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  401. };
  402. static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {
  403. .input_min = 2000000,
  404. .input_max = 40000000,
  405. .cf_min = 1000000,
  406. .cf_max = 6000000,
  407. .vco_min = 40000000,
  408. .vco_max = 1000000000,
  409. .base_reg = PLLD2_BASE,
  410. .misc_reg = PLLD2_MISC,
  411. .lock_mask = PLL_BASE_LOCK,
  412. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  413. .lock_delay = 1000,
  414. .freq_table = pll_d_freq_table,
  415. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  416. TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  417. };
  418. static struct tegra_clk_pll_params pll_u_params __ro_after_init = {
  419. .input_min = 2000000,
  420. .input_max = 40000000,
  421. .cf_min = 1000000,
  422. .cf_max = 6000000,
  423. .vco_min = 48000000,
  424. .vco_max = 960000000,
  425. .base_reg = PLLU_BASE,
  426. .misc_reg = PLLU_MISC,
  427. .lock_mask = PLL_BASE_LOCK,
  428. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  429. .lock_delay = 1000,
  430. .pdiv_tohw = pllu_p,
  431. .freq_table = pll_u_freq_table,
  432. .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  433. TEGRA_PLL_HAS_LOCK_ENABLE,
  434. };
  435. static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
  436. .input_min = 2000000,
  437. .input_max = 31000000,
  438. .cf_min = 1000000,
  439. .cf_max = 6000000,
  440. .vco_min = 20000000,
  441. .vco_max = 1700000000,
  442. .base_reg = PLLX_BASE,
  443. .misc_reg = PLLX_MISC,
  444. .lock_mask = PLL_BASE_LOCK,
  445. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  446. .lock_delay = 300,
  447. .freq_table = pll_x_freq_table,
  448. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
  449. TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  450. .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
  451. .post_rate_change = tegra_cclk_post_pllx_rate_change,
  452. };
  453. static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
  454. .input_min = 12000000,
  455. .input_max = 216000000,
  456. .cf_min = 12000000,
  457. .cf_max = 12000000,
  458. .vco_min = 1200000000,
  459. .vco_max = 2400000000U,
  460. .base_reg = PLLE_BASE,
  461. .misc_reg = PLLE_MISC,
  462. .lock_mask = PLLE_MISC_LOCK,
  463. .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
  464. .lock_delay = 300,
  465. .pdiv_tohw = plle_p,
  466. .freq_table = pll_e_freq_table,
  467. .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
  468. TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
  469. .fixed_rate = 100000000,
  470. };
  471. static unsigned long tegra30_input_freq[] = {
  472. [ 0] = 13000000,
  473. [ 1] = 16800000,
  474. [ 4] = 19200000,
  475. [ 5] = 38400000,
  476. [ 8] = 12000000,
  477. [ 9] = 48000000,
  478. [12] = 26000000,
  479. };
  480. static struct tegra_devclk devclks[] __initdata = {
  481. { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
  482. { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
  483. { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
  484. { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
  485. { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
  486. { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
  487. { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
  488. { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
  489. { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
  490. { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
  491. { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
  492. { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
  493. { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
  494. { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
  495. { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
  496. { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
  497. { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
  498. { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
  499. { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
  500. { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
  501. { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
  502. { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
  503. { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
  504. { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
  505. { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
  506. { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
  507. { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
  508. { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
  509. { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
  510. { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
  511. { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
  512. { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
  513. { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
  514. { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
  515. { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
  516. { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
  517. { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
  518. { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
  519. { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
  520. { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
  521. { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
  522. { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
  523. { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
  524. { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
  525. { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
  526. { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
  527. { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
  528. { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
  529. { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
  530. { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
  531. { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
  532. { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
  533. { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
  534. { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
  535. { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
  536. { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
  537. { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
  538. { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
  539. { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
  540. { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
  541. { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
  542. { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
  543. { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
  544. { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
  545. { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
  546. { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
  547. { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
  548. { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
  549. { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
  550. { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
  551. { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
  552. { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
  553. { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
  554. { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
  555. { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
  556. { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
  557. { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
  558. { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
  559. { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
  560. { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
  561. { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
  562. { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
  563. { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
  564. { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
  565. { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
  566. { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
  567. { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
  568. { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
  569. { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
  570. { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
  571. { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
  572. { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
  573. { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
  574. { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
  575. { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
  576. { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
  577. { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
  578. { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
  579. { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
  580. { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
  581. { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
  582. { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
  583. { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
  584. { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
  585. { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
  586. { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
  587. { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
  588. { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
  589. { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
  590. { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
  591. { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
  592. { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
  593. { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
  594. { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
  595. { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
  596. { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
  597. { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
  598. { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
  599. { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
  600. { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
  601. { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
  602. { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
  603. { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
  604. { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
  605. { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
  606. { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
  607. { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
  608. { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
  609. { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
  610. { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
  611. { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
  612. { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
  613. { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
  614. { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
  615. { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
  616. { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
  617. { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
  618. { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
  619. { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
  620. { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
  621. { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
  622. { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
  623. { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
  624. { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
  625. { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
  626. { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
  627. { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
  628. };
  629. static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
  630. [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
  631. [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
  632. [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
  633. [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
  634. [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
  635. [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
  636. [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
  637. [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
  638. [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
  639. [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
  640. [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
  641. [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
  642. [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
  643. [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
  644. [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
  645. [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
  646. [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
  647. [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
  648. [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
  649. [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
  650. [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
  651. [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
  652. [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
  653. [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
  654. [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
  655. [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
  656. [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
  657. [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
  658. [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
  659. [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
  660. [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
  661. [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
  662. [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
  663. [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
  664. [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
  665. [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
  666. [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
  667. [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
  668. [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
  669. [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
  670. [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
  671. [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
  672. [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
  673. [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
  674. [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
  675. [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
  676. [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
  677. [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
  678. [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
  679. [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
  680. [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
  681. [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
  682. [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
  683. [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
  684. [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
  685. [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
  686. [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
  687. [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
  688. [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
  689. [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
  690. [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
  691. [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
  692. [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
  693. [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
  694. [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
  695. [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
  696. [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
  697. [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
  698. [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
  699. [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
  700. [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
  701. [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
  702. [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
  703. [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
  704. [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
  705. [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
  706. [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
  707. [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
  708. [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
  709. [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
  710. [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
  711. [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
  712. [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
  713. [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
  714. [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
  715. [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
  716. [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
  717. [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
  718. [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
  719. [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
  720. [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
  721. [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
  722. [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
  723. [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
  724. [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
  725. [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
  726. [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
  727. [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
  728. [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
  729. [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
  730. [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
  731. [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
  732. [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
  733. [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
  734. [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
  735. [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
  736. [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
  737. [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
  738. [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
  739. [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
  740. [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
  741. [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
  742. [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
  743. [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
  744. [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
  745. [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
  746. [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
  747. [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
  748. [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
  749. [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
  750. [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },
  751. };
  752. static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
  753. static void __init tegra30_pll_init(void)
  754. {
  755. struct clk *clk;
  756. /* PLLC */
  757. clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
  758. &pll_c_params, NULL);
  759. clks[TEGRA30_CLK_PLL_C] = clk;
  760. /* PLLC_OUT1 */
  761. clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
  762. clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  763. 8, 8, 1, NULL);
  764. clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
  765. clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
  766. 0, NULL);
  767. clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
  768. /* PLLM */
  769. clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
  770. CLK_SET_RATE_GATE, &pll_m_params, NULL);
  771. clks[TEGRA30_CLK_PLL_M] = clk;
  772. /* PLLM_OUT1 */
  773. clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
  774. clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  775. 8, 8, 1, NULL);
  776. clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
  777. clk_base + PLLM_OUT, 1, 0,
  778. CLK_SET_RATE_PARENT, 0, NULL);
  779. clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
  780. /* PLLX */
  781. clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
  782. &pll_x_params, NULL);
  783. clks[TEGRA30_CLK_PLL_X] = clk;
  784. /* PLLX_OUT0 */
  785. clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
  786. CLK_SET_RATE_PARENT, 1, 2);
  787. clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
  788. /* PLLU */
  789. clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
  790. &pll_u_params, NULL);
  791. clks[TEGRA30_CLK_PLL_U] = clk;
  792. /* PLLD */
  793. clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
  794. &pll_d_params, &pll_d_lock);
  795. clks[TEGRA30_CLK_PLL_D] = clk;
  796. /* PLLD_OUT0 */
  797. clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
  798. CLK_SET_RATE_PARENT, 1, 2);
  799. clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
  800. /* PLLD2 */
  801. clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
  802. &pll_d2_params, NULL);
  803. clks[TEGRA30_CLK_PLL_D2] = clk;
  804. /* PLLD2_OUT0 */
  805. clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
  806. CLK_SET_RATE_PARENT, 1, 2);
  807. clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
  808. /* PLLE */
  809. clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
  810. ARRAY_SIZE(pll_e_parents),
  811. CLK_SET_RATE_NO_REPARENT,
  812. clk_base + PLLE_AUX, 2, 1, 0, NULL);
  813. clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
  814. CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
  815. clks[TEGRA30_CLK_PLL_E] = clk;
  816. }
  817. static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
  818. "pll_p_cclkg", "pll_p_out4_cclkg",
  819. "pll_p_out3_cclkg", "unused", "pll_x" };
  820. static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
  821. "pll_p_cclklp", "pll_p_out4_cclklp",
  822. "pll_p_out3_cclklp", "unused", "pll_x",
  823. "pll_x_out0" };
  824. static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
  825. "pll_p_out3", "pll_p_out2", "unused",
  826. "clk_32k", "pll_m_out1" };
  827. static void __init tegra30_super_clk_init(void)
  828. {
  829. struct clk *clk;
  830. /*
  831. * Clock input to cclk_g divided from pll_p using
  832. * U71 divider of cclk_g.
  833. */
  834. clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
  835. clk_base + SUPER_CCLKG_DIVIDER, 0,
  836. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  837. clk_register_clkdev(clk, "pll_p_cclkg", NULL);
  838. /*
  839. * Clock input to cclk_g divided from pll_p_out3 using
  840. * U71 divider of cclk_g.
  841. */
  842. clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
  843. clk_base + SUPER_CCLKG_DIVIDER, 0,
  844. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  845. clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
  846. /*
  847. * Clock input to cclk_g divided from pll_p_out4 using
  848. * U71 divider of cclk_g.
  849. */
  850. clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
  851. clk_base + SUPER_CCLKG_DIVIDER, 0,
  852. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  853. clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
  854. /* CCLKG */
  855. clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
  856. ARRAY_SIZE(cclk_g_parents),
  857. CLK_SET_RATE_PARENT,
  858. clk_base + CCLKG_BURST_POLICY,
  859. 0, NULL);
  860. clks[TEGRA30_CLK_CCLK_G] = clk;
  861. /*
  862. * Clock input to cclk_lp divided from pll_p using
  863. * U71 divider of cclk_lp.
  864. */
  865. clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
  866. clk_base + SUPER_CCLKLP_DIVIDER, 0,
  867. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  868. clk_register_clkdev(clk, "pll_p_cclklp", NULL);
  869. /*
  870. * Clock input to cclk_lp divided from pll_p_out3 using
  871. * U71 divider of cclk_lp.
  872. */
  873. clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
  874. clk_base + SUPER_CCLKLP_DIVIDER, 0,
  875. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  876. clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
  877. /*
  878. * Clock input to cclk_lp divided from pll_p_out4 using
  879. * U71 divider of cclk_lp.
  880. */
  881. clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
  882. clk_base + SUPER_CCLKLP_DIVIDER, 0,
  883. TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
  884. clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
  885. /* CCLKLP */
  886. clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
  887. ARRAY_SIZE(cclk_lp_parents),
  888. CLK_SET_RATE_PARENT,
  889. clk_base + CCLKLP_BURST_POLICY,
  890. TEGRA_DIVIDER_2, 4, 8, 9,
  891. NULL);
  892. clks[TEGRA30_CLK_CCLK_LP] = clk;
  893. /* SCLK */
  894. clk = tegra_clk_register_super_mux("sclk", sclk_parents,
  895. ARRAY_SIZE(sclk_parents),
  896. CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
  897. clk_base + SCLK_BURST_POLICY,
  898. 0, 4, 0, 0, NULL);
  899. clks[TEGRA30_CLK_SCLK] = clk;
  900. /* twd */
  901. clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
  902. CLK_SET_RATE_PARENT, 1, 2);
  903. clks[TEGRA30_CLK_TWD] = clk;
  904. tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
  905. }
  906. static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
  907. "clk_m" };
  908. static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
  909. static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
  910. "clk_m" };
  911. static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
  912. static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
  913. "pll_a_out0", "pll_c",
  914. "pll_d2_out0", "clk_m" };
  915. static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
  916. "pll_d2_out0" };
  917. static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
  918. static struct tegra_periph_init_data tegra_periph_clk_list[] = {
  919. TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
  920. TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
  921. TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
  922. TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
  923. TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
  924. TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
  925. TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
  926. TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
  927. TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
  928. };
  929. static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
  930. TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
  931. };
  932. static void __init tegra30_periph_clk_init(void)
  933. {
  934. struct tegra_periph_init_data *data;
  935. struct clk *clk;
  936. unsigned int i;
  937. /* dsia */
  938. clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
  939. 0, 48, periph_clk_enb_refcnt);
  940. clks[TEGRA30_CLK_DSIA] = clk;
  941. /* pcie */
  942. clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
  943. 70, periph_clk_enb_refcnt);
  944. clks[TEGRA30_CLK_PCIE] = clk;
  945. /* afi */
  946. clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
  947. periph_clk_enb_refcnt);
  948. clks[TEGRA30_CLK_AFI] = clk;
  949. /* emc */
  950. clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
  951. clks[TEGRA30_CLK_EMC] = clk;
  952. clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
  953. NULL);
  954. clks[TEGRA30_CLK_MC] = clk;
  955. /* cml0 */
  956. clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
  957. 0, 0, &cml_lock);
  958. clks[TEGRA30_CLK_CML0] = clk;
  959. /* cml1 */
  960. clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
  961. 1, 0, &cml_lock);
  962. clks[TEGRA30_CLK_CML1] = clk;
  963. for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
  964. data = &tegra_periph_clk_list[i];
  965. clk = tegra_clk_register_periph_data(clk_base, data);
  966. clks[data->clk_id] = clk;
  967. }
  968. for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
  969. data = &tegra_periph_nodiv_clk_list[i];
  970. clk = tegra_clk_register_periph_nodiv(data->name,
  971. data->p.parent_names,
  972. data->num_parents, &data->periph,
  973. clk_base, data->offset);
  974. clks[data->clk_id] = clk;
  975. }
  976. tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
  977. }
  978. /* Tegra30 CPU clock and reset control functions */
  979. static void tegra30_wait_cpu_in_reset(u32 cpu)
  980. {
  981. unsigned int reg;
  982. do {
  983. reg = readl(clk_base +
  984. TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
  985. cpu_relax();
  986. } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
  987. return;
  988. }
  989. static void tegra30_put_cpu_in_reset(u32 cpu)
  990. {
  991. writel(CPU_RESET(cpu),
  992. clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
  993. dmb();
  994. }
  995. static void tegra30_cpu_out_of_reset(u32 cpu)
  996. {
  997. writel(CPU_RESET(cpu),
  998. clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
  999. wmb();
  1000. }
  1001. static void tegra30_enable_cpu_clock(u32 cpu)
  1002. {
  1003. unsigned int reg;
  1004. writel(CPU_CLOCK(cpu),
  1005. clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
  1006. reg = readl(clk_base +
  1007. TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
  1008. }
  1009. static void tegra30_disable_cpu_clock(u32 cpu)
  1010. {
  1011. unsigned int reg;
  1012. reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
  1013. writel(reg | CPU_CLOCK(cpu),
  1014. clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
  1015. }
  1016. #ifdef CONFIG_PM_SLEEP
  1017. static bool tegra30_cpu_rail_off_ready(void)
  1018. {
  1019. unsigned int cpu_rst_status;
  1020. int cpu_pwr_status;
  1021. cpu_rst_status = readl(clk_base +
  1022. TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
  1023. cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
  1024. tegra_pmc_cpu_is_powered(2) ||
  1025. tegra_pmc_cpu_is_powered(3);
  1026. if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
  1027. return false;
  1028. return true;
  1029. }
  1030. static void tegra30_cpu_clock_suspend(void)
  1031. {
  1032. /* switch coresite to clk_m, save off original source */
  1033. tegra30_cpu_clk_sctx.clk_csite_src =
  1034. readl(clk_base + CLK_RESET_SOURCE_CSITE);
  1035. writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
  1036. tegra30_cpu_clk_sctx.cpu_burst =
  1037. readl(clk_base + CLK_RESET_CCLK_BURST);
  1038. tegra30_cpu_clk_sctx.pllx_base =
  1039. readl(clk_base + CLK_RESET_PLLX_BASE);
  1040. tegra30_cpu_clk_sctx.pllx_misc =
  1041. readl(clk_base + CLK_RESET_PLLX_MISC);
  1042. tegra30_cpu_clk_sctx.cclk_divider =
  1043. readl(clk_base + CLK_RESET_CCLK_DIVIDER);
  1044. }
  1045. static void tegra30_cpu_clock_resume(void)
  1046. {
  1047. unsigned int reg, policy;
  1048. u32 misc, base;
  1049. /* Is CPU complex already running on PLLX? */
  1050. reg = readl(clk_base + CLK_RESET_CCLK_BURST);
  1051. policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
  1052. if (policy == CLK_RESET_CCLK_IDLE_POLICY)
  1053. reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
  1054. else if (policy == CLK_RESET_CCLK_RUN_POLICY)
  1055. reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
  1056. else
  1057. BUG();
  1058. if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
  1059. misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
  1060. base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
  1061. if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
  1062. base != tegra30_cpu_clk_sctx.pllx_base) {
  1063. /* restore PLLX settings if CPU is on different PLL */
  1064. writel(tegra30_cpu_clk_sctx.pllx_misc,
  1065. clk_base + CLK_RESET_PLLX_MISC);
  1066. writel(tegra30_cpu_clk_sctx.pllx_base,
  1067. clk_base + CLK_RESET_PLLX_BASE);
  1068. /* wait for PLL stabilization if PLLX was enabled */
  1069. if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
  1070. udelay(300);
  1071. }
  1072. }
  1073. /*
  1074. * Restore original burst policy setting for calls resulting from CPU
  1075. * LP2 in idle or system suspend.
  1076. */
  1077. writel(tegra30_cpu_clk_sctx.cclk_divider,
  1078. clk_base + CLK_RESET_CCLK_DIVIDER);
  1079. writel(tegra30_cpu_clk_sctx.cpu_burst,
  1080. clk_base + CLK_RESET_CCLK_BURST);
  1081. writel(tegra30_cpu_clk_sctx.clk_csite_src,
  1082. clk_base + CLK_RESET_SOURCE_CSITE);
  1083. }
  1084. #endif
  1085. static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
  1086. .wait_for_reset = tegra30_wait_cpu_in_reset,
  1087. .put_in_reset = tegra30_put_cpu_in_reset,
  1088. .out_of_reset = tegra30_cpu_out_of_reset,
  1089. .enable_clock = tegra30_enable_cpu_clock,
  1090. .disable_clock = tegra30_disable_cpu_clock,
  1091. #ifdef CONFIG_PM_SLEEP
  1092. .rail_off_ready = tegra30_cpu_rail_off_ready,
  1093. .suspend = tegra30_cpu_clock_suspend,
  1094. .resume = tegra30_cpu_clock_resume,
  1095. #endif
  1096. };
  1097. static struct tegra_clk_init_table init_table[] __initdata = {
  1098. { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
  1099. { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
  1100. { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
  1101. { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
  1102. { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
  1103. { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
  1104. { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
  1105. { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
  1106. { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
  1107. { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
  1108. { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
  1109. { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
  1110. { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
  1111. { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
  1112. { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
  1113. { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
  1114. { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
  1115. { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1116. { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1117. { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1118. { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1119. { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1120. { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
  1121. { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
  1122. { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
  1123. { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
  1124. { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
  1125. { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
  1126. { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
  1127. { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
  1128. { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
  1129. { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1130. { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1131. { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1132. { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1133. { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1134. { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1135. { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
  1136. { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
  1137. { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
  1138. /* must be the last entry */
  1139. { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
  1140. };
  1141. static void __init tegra30_clock_apply_init_table(void)
  1142. {
  1143. tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
  1144. }
  1145. /*
  1146. * Some clocks may be used by different drivers depending on the board
  1147. * configuration. List those here to register them twice in the clock lookup
  1148. * table under two names.
  1149. */
  1150. static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
  1151. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
  1152. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
  1153. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
  1154. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
  1155. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
  1156. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
  1157. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
  1158. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
  1159. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
  1160. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
  1161. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
  1162. /* must be the last entry */
  1163. TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
  1164. };
  1165. static const struct of_device_id pmc_match[] __initconst = {
  1166. { .compatible = "nvidia,tegra30-pmc" },
  1167. { },
  1168. };
  1169. static struct tegra_audio_clk_info tegra30_audio_plls[] = {
  1170. { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
  1171. };
  1172. static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
  1173. void *data)
  1174. {
  1175. struct clk_hw *hw;
  1176. struct clk *clk;
  1177. clk = of_clk_src_onecell_get(clkspec, data);
  1178. if (IS_ERR(clk))
  1179. return clk;
  1180. hw = __clk_get_hw(clk);
  1181. if (clkspec->args[0] == TEGRA30_CLK_EMC) {
  1182. if (!tegra20_clk_emc_driver_available(hw))
  1183. return ERR_PTR(-EPROBE_DEFER);
  1184. }
  1185. return clk;
  1186. }
  1187. static void __init tegra30_clock_init(struct device_node *np)
  1188. {
  1189. struct device_node *node;
  1190. clk_base = of_iomap(np, 0);
  1191. if (!clk_base) {
  1192. pr_err("ioremap tegra30 CAR failed\n");
  1193. return;
  1194. }
  1195. node = of_find_matching_node(NULL, pmc_match);
  1196. if (!node) {
  1197. pr_err("Failed to find pmc node\n");
  1198. BUG();
  1199. }
  1200. pmc_base = of_iomap(node, 0);
  1201. if (!pmc_base) {
  1202. pr_err("Can't map pmc registers\n");
  1203. BUG();
  1204. }
  1205. clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
  1206. TEGRA30_CLK_PERIPH_BANKS);
  1207. if (!clks)
  1208. return;
  1209. if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
  1210. ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
  1211. NULL) < 0)
  1212. return;
  1213. tegra_fixed_clk_init(tegra30_clks);
  1214. tegra30_pll_init();
  1215. tegra30_super_clk_init();
  1216. tegra30_periph_clk_init();
  1217. tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
  1218. tegra30_audio_plls,
  1219. ARRAY_SIZE(tegra30_audio_plls), 24000000);
  1220. tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
  1221. tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
  1222. tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
  1223. tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
  1224. tegra_cpu_car_ops = &tegra30_cpu_car_ops;
  1225. }
  1226. CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);