clk-tegra210-emc.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/clk.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/tegra.h>
  9. #include <linux/device.h>
  10. #include <linux/module.h>
  11. #include <linux/io.h>
  12. #include <linux/slab.h>
  13. #include "clk.h"
  14. #define CLK_SOURCE_EMC 0x19c
  15. #define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29)
  16. #define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16)
  17. #define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0)
  18. #define CLK_SRC_PLLM 0
  19. #define CLK_SRC_PLLC 1
  20. #define CLK_SRC_PLLP 2
  21. #define CLK_SRC_CLK_M 3
  22. #define CLK_SRC_PLLM_UD 4
  23. #define CLK_SRC_PLLMB_UD 5
  24. #define CLK_SRC_PLLMB 6
  25. #define CLK_SRC_PLLP_UD 7
  26. struct tegra210_clk_emc {
  27. struct clk_hw hw;
  28. void __iomem *regs;
  29. struct tegra210_clk_emc_provider *provider;
  30. struct clk *parents[8];
  31. };
  32. static inline struct tegra210_clk_emc *
  33. to_tegra210_clk_emc(struct clk_hw *hw)
  34. {
  35. return container_of(hw, struct tegra210_clk_emc, hw);
  36. }
  37. static const char *tegra210_clk_emc_parents[] = {
  38. "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud",
  39. "pll_mb", "pll_p_ud",
  40. };
  41. static u8 tegra210_clk_emc_get_parent(struct clk_hw *hw)
  42. {
  43. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
  44. u32 value;
  45. u8 src;
  46. value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);
  47. src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, value);
  48. return src;
  49. }
  50. static unsigned long tegra210_clk_emc_recalc_rate(struct clk_hw *hw,
  51. unsigned long parent_rate)
  52. {
  53. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
  54. u32 value, div;
  55. /*
  56. * CCF assumes that neither the parent nor its rate will change during
  57. * ->set_rate(), so the parent rate passed in here was cached from the
  58. * parent before the ->set_rate() call.
  59. *
  60. * This can lead to wrong results being reported for the EMC clock if
  61. * the parent and/or parent rate have changed as part of the EMC rate
  62. * change sequence. Fix this by overriding the parent clock with what
  63. * we know to be the correct value after the rate change.
  64. */
  65. parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  66. value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);
  67. div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, value);
  68. div += 2;
  69. return DIV_ROUND_UP(parent_rate * 2, div);
  70. }
  71. static long tegra210_clk_emc_round_rate(struct clk_hw *hw, unsigned long rate,
  72. unsigned long *prate)
  73. {
  74. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
  75. struct tegra210_clk_emc_provider *provider = emc->provider;
  76. unsigned int i;
  77. if (!provider || !provider->configs || provider->num_configs == 0)
  78. return clk_hw_get_rate(hw);
  79. for (i = 0; i < provider->num_configs; i++) {
  80. if (provider->configs[i].rate >= rate)
  81. return provider->configs[i].rate;
  82. }
  83. return provider->configs[i - 1].rate;
  84. }
  85. static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc,
  86. u8 index)
  87. {
  88. struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index);
  89. const char *name = clk_hw_get_name(parent);
  90. /* XXX implement cache? */
  91. return __clk_lookup(name);
  92. }
  93. static int tegra210_clk_emc_set_rate(struct clk_hw *hw, unsigned long rate,
  94. unsigned long parent_rate)
  95. {
  96. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
  97. struct tegra210_clk_emc_provider *provider = emc->provider;
  98. struct tegra210_clk_emc_config *config;
  99. struct device *dev = provider->dev;
  100. struct clk_hw *old, *new, *parent;
  101. u8 old_idx, new_idx, index;
  102. struct clk *clk;
  103. unsigned int i;
  104. int err;
  105. if (!provider->configs || provider->num_configs == 0)
  106. return -EINVAL;
  107. for (i = 0; i < provider->num_configs; i++) {
  108. if (provider->configs[i].rate >= rate) {
  109. config = &provider->configs[i];
  110. break;
  111. }
  112. }
  113. if (i == provider->num_configs)
  114. config = &provider->configs[i - 1];
  115. old_idx = tegra210_clk_emc_get_parent(hw);
  116. new_idx = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value);
  117. old = clk_hw_get_parent_by_index(hw, old_idx);
  118. new = clk_hw_get_parent_by_index(hw, new_idx);
  119. /* if the rate has changed... */
  120. if (config->parent_rate != clk_hw_get_rate(old)) {
  121. /* ... but the clock source remains the same ... */
  122. if (new_idx == old_idx) {
  123. /* ... switch to the alternative clock source. */
  124. switch (new_idx) {
  125. case CLK_SRC_PLLM:
  126. new_idx = CLK_SRC_PLLMB;
  127. break;
  128. case CLK_SRC_PLLM_UD:
  129. new_idx = CLK_SRC_PLLMB_UD;
  130. break;
  131. case CLK_SRC_PLLMB_UD:
  132. new_idx = CLK_SRC_PLLM_UD;
  133. break;
  134. case CLK_SRC_PLLMB:
  135. new_idx = CLK_SRC_PLLM;
  136. break;
  137. }
  138. /*
  139. * This should never happen because we can't deal with
  140. * it.
  141. */
  142. if (WARN_ON(new_idx == old_idx))
  143. return -EINVAL;
  144. new = clk_hw_get_parent_by_index(hw, new_idx);
  145. }
  146. index = new_idx;
  147. parent = new;
  148. } else {
  149. index = old_idx;
  150. parent = old;
  151. }
  152. clk = tegra210_clk_emc_find_parent(emc, index);
  153. if (IS_ERR(clk)) {
  154. err = PTR_ERR(clk);
  155. dev_err(dev, "failed to get parent clock for index %u: %d\n",
  156. index, err);
  157. return err;
  158. }
  159. /* set the new parent clock to the required rate */
  160. if (clk_get_rate(clk) != config->parent_rate) {
  161. err = clk_set_rate(clk, config->parent_rate);
  162. if (err < 0) {
  163. dev_err(dev, "failed to set rate %lu Hz for %pC: %d\n",
  164. config->parent_rate, clk, err);
  165. return err;
  166. }
  167. }
  168. /* enable the new parent clock */
  169. if (parent != old) {
  170. err = clk_prepare_enable(clk);
  171. if (err < 0) {
  172. dev_err(dev, "failed to enable parent clock %pC: %d\n",
  173. clk, err);
  174. return err;
  175. }
  176. }
  177. /* update the EMC source configuration to reflect the new parent */
  178. config->value &= ~CLK_SOURCE_EMC_2X_CLK_SRC;
  179. config->value |= FIELD_PREP(CLK_SOURCE_EMC_2X_CLK_SRC, index);
  180. /*
  181. * Finally, switch the EMC programming with both old and new parent
  182. * clocks enabled.
  183. */
  184. err = provider->set_rate(dev, config);
  185. if (err < 0) {
  186. dev_err(dev, "failed to set EMC rate to %lu Hz: %d\n", rate,
  187. err);
  188. /*
  189. * If we're unable to switch to the new EMC frequency, we no
  190. * longer need the new parent to be enabled.
  191. */
  192. if (parent != old)
  193. clk_disable_unprepare(clk);
  194. return err;
  195. }
  196. /* reparent to new parent clock and disable the old parent clock */
  197. if (parent != old) {
  198. clk = tegra210_clk_emc_find_parent(emc, old_idx);
  199. if (IS_ERR(clk)) {
  200. err = PTR_ERR(clk);
  201. dev_err(dev,
  202. "failed to get parent clock for index %u: %d\n",
  203. old_idx, err);
  204. return err;
  205. }
  206. clk_hw_reparent(hw, parent);
  207. clk_disable_unprepare(clk);
  208. }
  209. return err;
  210. }
  211. static const struct clk_ops tegra210_clk_emc_ops = {
  212. .get_parent = tegra210_clk_emc_get_parent,
  213. .recalc_rate = tegra210_clk_emc_recalc_rate,
  214. .round_rate = tegra210_clk_emc_round_rate,
  215. .set_rate = tegra210_clk_emc_set_rate,
  216. };
  217. struct clk *tegra210_clk_register_emc(struct device_node *np,
  218. void __iomem *regs)
  219. {
  220. struct tegra210_clk_emc *emc;
  221. struct clk_init_data init;
  222. struct clk *clk;
  223. emc = kzalloc(sizeof(*emc), GFP_KERNEL);
  224. if (!emc)
  225. return ERR_PTR(-ENOMEM);
  226. emc->regs = regs;
  227. init.name = "emc";
  228. init.ops = &tegra210_clk_emc_ops;
  229. init.flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE;
  230. init.parent_names = tegra210_clk_emc_parents;
  231. init.num_parents = ARRAY_SIZE(tegra210_clk_emc_parents);
  232. emc->hw.init = &init;
  233. clk = clk_register(NULL, &emc->hw);
  234. if (IS_ERR(clk)) {
  235. kfree(emc);
  236. return clk;
  237. }
  238. return clk;
  239. }
  240. int tegra210_clk_emc_attach(struct clk *clk,
  241. struct tegra210_clk_emc_provider *provider)
  242. {
  243. struct clk_hw *hw = __clk_get_hw(clk);
  244. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
  245. struct device *dev = provider->dev;
  246. unsigned int i;
  247. int err;
  248. if (!try_module_get(provider->owner))
  249. return -ENODEV;
  250. for (i = 0; i < provider->num_configs; i++) {
  251. struct tegra210_clk_emc_config *config = &provider->configs[i];
  252. struct clk_hw *parent;
  253. bool same_freq;
  254. u8 div, src;
  255. div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, config->value);
  256. src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value);
  257. /* do basic sanity checking on the EMC timings */
  258. if (div & 0x1) {
  259. dev_err(dev, "invalid odd divider %u for rate %lu Hz\n",
  260. div, config->rate);
  261. err = -EINVAL;
  262. goto put;
  263. }
  264. same_freq = config->value & CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
  265. if (same_freq != config->same_freq) {
  266. dev_err(dev,
  267. "ambiguous EMC to MC ratio for rate %lu Hz\n",
  268. config->rate);
  269. err = -EINVAL;
  270. goto put;
  271. }
  272. parent = clk_hw_get_parent_by_index(hw, src);
  273. config->parent = src;
  274. if (src == CLK_SRC_PLLM || src == CLK_SRC_PLLM_UD) {
  275. config->parent_rate = config->rate * (1 + div / 2);
  276. } else {
  277. unsigned long rate = config->rate * (1 + div / 2);
  278. config->parent_rate = clk_hw_get_rate(parent);
  279. if (config->parent_rate != rate) {
  280. dev_err(dev,
  281. "rate %lu Hz does not match input\n",
  282. config->rate);
  283. err = -EINVAL;
  284. goto put;
  285. }
  286. }
  287. }
  288. emc->provider = provider;
  289. return 0;
  290. put:
  291. module_put(provider->owner);
  292. return err;
  293. }
  294. EXPORT_SYMBOL_GPL(tegra210_clk_emc_attach);
  295. void tegra210_clk_emc_detach(struct clk *clk)
  296. {
  297. struct tegra210_clk_emc *emc = to_tegra210_clk_emc(__clk_get_hw(clk));
  298. module_put(emc->provider->owner);
  299. emc->provider = NULL;
  300. }
  301. EXPORT_SYMBOL_GPL(tegra210_clk_emc_detach);