clk-tegra124-emc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/clk/tegra/clk-emc.c
  4. *
  5. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author:
  8. * Mikko Perttunen <mperttunen@nvidia.com>
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clk.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/delay.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/sort.h>
  20. #include <linux/string.h>
  21. #include <soc/tegra/fuse.h>
  22. #include <soc/tegra/emc.h>
  23. #include "clk.h"
  24. #define CLK_SOURCE_EMC 0x19c
  25. #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
  26. #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
  27. #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
  28. CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
  29. #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
  30. #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
  31. #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
  32. CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
  33. static const char * const emc_parent_clk_names[] = {
  34. "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
  35. "pll_c2", "pll_c3", "pll_c_ud"
  36. };
  37. /*
  38. * List of clock sources for various parents the EMC clock can have.
  39. * When we change the timing to a timing with a parent that has the same
  40. * clock source as the current parent, we must first change to a backup
  41. * timing that has a different clock source.
  42. */
  43. #define EMC_SRC_PLL_M 0
  44. #define EMC_SRC_PLL_C 1
  45. #define EMC_SRC_PLL_P 2
  46. #define EMC_SRC_CLK_M 3
  47. #define EMC_SRC_PLL_C2 4
  48. #define EMC_SRC_PLL_C3 5
  49. static const char emc_parent_clk_sources[] = {
  50. EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
  51. EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
  52. };
  53. struct emc_timing {
  54. unsigned long rate, parent_rate;
  55. u8 parent_index;
  56. struct clk *parent;
  57. u32 ram_code;
  58. };
  59. struct tegra_clk_emc {
  60. struct clk_hw hw;
  61. void __iomem *clk_regs;
  62. struct clk *prev_parent;
  63. bool changing_timing;
  64. struct device_node *emc_node;
  65. struct tegra_emc *emc;
  66. int num_timings;
  67. struct emc_timing *timings;
  68. spinlock_t *lock;
  69. };
  70. /* Common clock framework callback implementations */
  71. static unsigned long emc_recalc_rate(struct clk_hw *hw,
  72. unsigned long parent_rate)
  73. {
  74. struct tegra_clk_emc *tegra;
  75. u32 val, div;
  76. tegra = container_of(hw, struct tegra_clk_emc, hw);
  77. /*
  78. * CCF wrongly assumes that the parent won't change during set_rate,
  79. * so get the parent rate explicitly.
  80. */
  81. parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  82. val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
  83. div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
  84. return parent_rate / (div + 2) * 2;
  85. }
  86. /*
  87. * Rounds up unless no higher rate exists, in which case down. This way is
  88. * safer since things have EMC rate floors. Also don't touch parent_rate
  89. * since we don't want the CCF to play with our parent clocks.
  90. */
  91. static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
  92. {
  93. struct tegra_clk_emc *tegra;
  94. u8 ram_code = tegra_read_ram_code();
  95. struct emc_timing *timing = NULL;
  96. int i, k, t;
  97. tegra = container_of(hw, struct tegra_clk_emc, hw);
  98. for (k = 0; k < tegra->num_timings; k++) {
  99. if (tegra->timings[k].ram_code == ram_code)
  100. break;
  101. }
  102. for (t = k; t < tegra->num_timings; t++) {
  103. if (tegra->timings[t].ram_code != ram_code)
  104. break;
  105. }
  106. for (i = k; i < t; i++) {
  107. timing = tegra->timings + i;
  108. if (timing->rate < req->rate && i != t - 1)
  109. continue;
  110. if (timing->rate > req->max_rate) {
  111. i = max(i, k + 1);
  112. req->rate = tegra->timings[i - 1].rate;
  113. return 0;
  114. }
  115. if (timing->rate < req->min_rate)
  116. continue;
  117. req->rate = timing->rate;
  118. return 0;
  119. }
  120. if (timing) {
  121. req->rate = timing->rate;
  122. return 0;
  123. }
  124. req->rate = clk_hw_get_rate(hw);
  125. return 0;
  126. }
  127. static u8 emc_get_parent(struct clk_hw *hw)
  128. {
  129. struct tegra_clk_emc *tegra;
  130. u32 val;
  131. tegra = container_of(hw, struct tegra_clk_emc, hw);
  132. val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
  133. return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
  134. & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
  135. }
  136. static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
  137. {
  138. struct platform_device *pdev;
  139. if (tegra->emc)
  140. return tegra->emc;
  141. if (!tegra->emc_node)
  142. return NULL;
  143. pdev = of_find_device_by_node(tegra->emc_node);
  144. if (!pdev) {
  145. pr_err("%s: could not get external memory controller\n",
  146. __func__);
  147. return NULL;
  148. }
  149. of_node_put(tegra->emc_node);
  150. tegra->emc_node = NULL;
  151. tegra->emc = platform_get_drvdata(pdev);
  152. if (!tegra->emc) {
  153. put_device(&pdev->dev);
  154. pr_err("%s: cannot find EMC driver\n", __func__);
  155. return NULL;
  156. }
  157. return tegra->emc;
  158. }
  159. static int emc_set_timing(struct tegra_clk_emc *tegra,
  160. struct emc_timing *timing)
  161. {
  162. int err;
  163. u8 div;
  164. u32 car_value;
  165. unsigned long flags = 0;
  166. struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
  167. if (!emc)
  168. return -ENOENT;
  169. pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
  170. timing->parent_rate, __clk_get_name(timing->parent));
  171. if (emc_get_parent(&tegra->hw) == timing->parent_index &&
  172. clk_get_rate(timing->parent) != timing->parent_rate) {
  173. WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
  174. __clk_get_name(timing->parent),
  175. clk_get_rate(timing->parent),
  176. timing->parent_rate);
  177. return -EINVAL;
  178. }
  179. tegra->changing_timing = true;
  180. err = clk_set_rate(timing->parent, timing->parent_rate);
  181. if (err) {
  182. pr_err("cannot change parent %s rate to %ld: %d\n",
  183. __clk_get_name(timing->parent), timing->parent_rate,
  184. err);
  185. return err;
  186. }
  187. err = clk_prepare_enable(timing->parent);
  188. if (err) {
  189. pr_err("cannot enable parent clock: %d\n", err);
  190. return err;
  191. }
  192. div = timing->parent_rate / (timing->rate / 2) - 2;
  193. err = tegra_emc_prepare_timing_change(emc, timing->rate);
  194. if (err)
  195. return err;
  196. spin_lock_irqsave(tegra->lock, flags);
  197. car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
  198. car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
  199. car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
  200. car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
  201. car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
  202. writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
  203. spin_unlock_irqrestore(tegra->lock, flags);
  204. tegra_emc_complete_timing_change(emc, timing->rate);
  205. clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
  206. clk_disable_unprepare(tegra->prev_parent);
  207. tegra->prev_parent = timing->parent;
  208. tegra->changing_timing = false;
  209. return 0;
  210. }
  211. /*
  212. * Get backup timing to use as an intermediate step when a change between
  213. * two timings with the same clock source has been requested. First try to
  214. * find a timing with a higher clock rate to avoid a rate below any set rate
  215. * floors. If that is not possible, find a lower rate.
  216. */
  217. static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
  218. int timing_index)
  219. {
  220. int i;
  221. u32 ram_code = tegra_read_ram_code();
  222. struct emc_timing *timing;
  223. for (i = timing_index+1; i < tegra->num_timings; i++) {
  224. timing = tegra->timings + i;
  225. if (timing->ram_code != ram_code)
  226. break;
  227. if (emc_parent_clk_sources[timing->parent_index] !=
  228. emc_parent_clk_sources[
  229. tegra->timings[timing_index].parent_index])
  230. return timing;
  231. }
  232. for (i = timing_index-1; i >= 0; --i) {
  233. timing = tegra->timings + i;
  234. if (timing->ram_code != ram_code)
  235. break;
  236. if (emc_parent_clk_sources[timing->parent_index] !=
  237. emc_parent_clk_sources[
  238. tegra->timings[timing_index].parent_index])
  239. return timing;
  240. }
  241. return NULL;
  242. }
  243. static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
  244. unsigned long parent_rate)
  245. {
  246. struct tegra_clk_emc *tegra;
  247. struct emc_timing *timing = NULL;
  248. int i, err;
  249. u32 ram_code = tegra_read_ram_code();
  250. tegra = container_of(hw, struct tegra_clk_emc, hw);
  251. if (clk_hw_get_rate(hw) == rate)
  252. return 0;
  253. /*
  254. * When emc_set_timing changes the parent rate, CCF will propagate
  255. * that downward to us, so ignore any set_rate calls while a rate
  256. * change is already going on.
  257. */
  258. if (tegra->changing_timing)
  259. return 0;
  260. for (i = 0; i < tegra->num_timings; i++) {
  261. if (tegra->timings[i].rate == rate &&
  262. tegra->timings[i].ram_code == ram_code) {
  263. timing = tegra->timings + i;
  264. break;
  265. }
  266. }
  267. if (!timing) {
  268. pr_err("cannot switch to rate %ld without emc table\n", rate);
  269. return -EINVAL;
  270. }
  271. if (emc_parent_clk_sources[emc_get_parent(hw)] ==
  272. emc_parent_clk_sources[timing->parent_index] &&
  273. clk_get_rate(timing->parent) != timing->parent_rate) {
  274. /*
  275. * Parent clock source not changed but parent rate has changed,
  276. * need to temporarily switch to another parent
  277. */
  278. struct emc_timing *backup_timing;
  279. backup_timing = get_backup_timing(tegra, i);
  280. if (!backup_timing) {
  281. pr_err("cannot find backup timing\n");
  282. return -EINVAL;
  283. }
  284. pr_debug("using %ld as backup rate when going to %ld\n",
  285. backup_timing->rate, rate);
  286. err = emc_set_timing(tegra, backup_timing);
  287. if (err) {
  288. pr_err("cannot set backup timing: %d\n", err);
  289. return err;
  290. }
  291. }
  292. return emc_set_timing(tegra, timing);
  293. }
  294. /* Initialization and deinitialization */
  295. static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
  296. struct emc_timing *timing,
  297. struct device_node *node)
  298. {
  299. int err, i;
  300. u32 tmp;
  301. err = of_property_read_u32(node, "clock-frequency", &tmp);
  302. if (err) {
  303. pr_err("timing %pOF: failed to read rate\n", node);
  304. return err;
  305. }
  306. timing->rate = tmp;
  307. err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
  308. if (err) {
  309. pr_err("timing %pOF: failed to read parent rate\n", node);
  310. return err;
  311. }
  312. timing->parent_rate = tmp;
  313. timing->parent = of_clk_get_by_name(node, "emc-parent");
  314. if (IS_ERR(timing->parent)) {
  315. pr_err("timing %pOF: failed to get parent clock\n", node);
  316. return PTR_ERR(timing->parent);
  317. }
  318. timing->parent_index = 0xff;
  319. i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names),
  320. __clk_get_name(timing->parent));
  321. if (i < 0) {
  322. pr_err("timing %pOF: %s is not a valid parent\n",
  323. node, __clk_get_name(timing->parent));
  324. clk_put(timing->parent);
  325. return -EINVAL;
  326. }
  327. timing->parent_index = i;
  328. return 0;
  329. }
  330. static int cmp_timings(const void *_a, const void *_b)
  331. {
  332. const struct emc_timing *a = _a;
  333. const struct emc_timing *b = _b;
  334. if (a->rate < b->rate)
  335. return -1;
  336. else if (a->rate == b->rate)
  337. return 0;
  338. else
  339. return 1;
  340. }
  341. static int load_timings_from_dt(struct tegra_clk_emc *tegra,
  342. struct device_node *node,
  343. u32 ram_code)
  344. {
  345. struct emc_timing *timings_ptr;
  346. struct device_node *child;
  347. int child_count = of_get_child_count(node);
  348. int i = 0, err;
  349. size_t size;
  350. size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
  351. tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
  352. if (!tegra->timings)
  353. return -ENOMEM;
  354. timings_ptr = tegra->timings + tegra->num_timings;
  355. tegra->num_timings += child_count;
  356. for_each_child_of_node(node, child) {
  357. struct emc_timing *timing = timings_ptr + (i++);
  358. err = load_one_timing_from_dt(tegra, timing, child);
  359. if (err) {
  360. of_node_put(child);
  361. return err;
  362. }
  363. timing->ram_code = ram_code;
  364. }
  365. sort(timings_ptr, child_count, sizeof(struct emc_timing),
  366. cmp_timings, NULL);
  367. return 0;
  368. }
  369. static const struct clk_ops tegra_clk_emc_ops = {
  370. .recalc_rate = emc_recalc_rate,
  371. .determine_rate = emc_determine_rate,
  372. .set_rate = emc_set_rate,
  373. .get_parent = emc_get_parent,
  374. };
  375. struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
  376. spinlock_t *lock)
  377. {
  378. struct tegra_clk_emc *tegra;
  379. struct clk_init_data init;
  380. struct device_node *node;
  381. u32 node_ram_code;
  382. struct clk *clk;
  383. int err;
  384. tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
  385. if (!tegra)
  386. return ERR_PTR(-ENOMEM);
  387. tegra->clk_regs = base;
  388. tegra->lock = lock;
  389. tegra->num_timings = 0;
  390. for_each_child_of_node(np, node) {
  391. err = of_property_read_u32(node, "nvidia,ram-code",
  392. &node_ram_code);
  393. if (err)
  394. continue;
  395. /*
  396. * Store timings for all ram codes as we cannot read the
  397. * fuses until the apbmisc driver is loaded.
  398. */
  399. err = load_timings_from_dt(tegra, node, node_ram_code);
  400. if (err) {
  401. of_node_put(node);
  402. return ERR_PTR(err);
  403. }
  404. }
  405. if (tegra->num_timings == 0)
  406. pr_warn("%s: no memory timings registered\n", __func__);
  407. tegra->emc_node = of_parse_phandle(np,
  408. "nvidia,external-memory-controller", 0);
  409. if (!tegra->emc_node)
  410. pr_warn("%s: couldn't find node for EMC driver\n", __func__);
  411. init.name = "emc";
  412. init.ops = &tegra_clk_emc_ops;
  413. init.flags = CLK_IS_CRITICAL;
  414. init.parent_names = emc_parent_clk_names;
  415. init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
  416. tegra->hw.init = &init;
  417. clk = clk_register(NULL, &tegra->hw);
  418. if (IS_ERR(clk))
  419. return clk;
  420. tegra->prev_parent = clk_hw_get_parent_by_index(
  421. &tegra->hw, emc_get_parent(&tegra->hw))->clk;
  422. tegra->changing_timing = false;
  423. /* Allow debugging tools to see the EMC clock */
  424. clk_register_clkdev(clk, "emc", "tegra-clk-debug");
  425. return clk;
  426. };