clk-tegra124-dfll-fcpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Tegra124 DFLL FCPU clock source driver
  4. *
  5. * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
  6. *
  7. * Aleksandr Frid <afrid@nvidia.com>
  8. * Paul Walmsley <pwalmsley@nvidia.com>
  9. */
  10. #include <linux/cpu.h>
  11. #include <linux/err.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <soc/tegra/fuse.h>
  18. #include "clk.h"
  19. #include "clk-dfll.h"
  20. #include "cvb.h"
  21. struct dfll_fcpu_data {
  22. const unsigned long *cpu_max_freq_table;
  23. unsigned int cpu_max_freq_table_size;
  24. const struct cvb_table *cpu_cvb_tables;
  25. unsigned int cpu_cvb_tables_size;
  26. };
  27. /* Maximum CPU frequency, indexed by CPU speedo id */
  28. static const unsigned long tegra124_cpu_max_freq_table[] = {
  29. [0] = 2014500000UL,
  30. [1] = 2320500000UL,
  31. [2] = 2116500000UL,
  32. [3] = 2524500000UL,
  33. };
  34. static const struct cvb_table tegra124_cpu_cvb_tables[] = {
  35. {
  36. .speedo_id = -1,
  37. .process_id = -1,
  38. .min_millivolts = 900,
  39. .max_millivolts = 1260,
  40. .speedo_scale = 100,
  41. .voltage_scale = 1000,
  42. .entries = {
  43. { 204000000UL, { 1112619, -29295, 402 } },
  44. { 306000000UL, { 1150460, -30585, 402 } },
  45. { 408000000UL, { 1190122, -31865, 402 } },
  46. { 510000000UL, { 1231606, -33155, 402 } },
  47. { 612000000UL, { 1274912, -34435, 402 } },
  48. { 714000000UL, { 1320040, -35725, 402 } },
  49. { 816000000UL, { 1366990, -37005, 402 } },
  50. { 918000000UL, { 1415762, -38295, 402 } },
  51. { 1020000000UL, { 1466355, -39575, 402 } },
  52. { 1122000000UL, { 1518771, -40865, 402 } },
  53. { 1224000000UL, { 1573009, -42145, 402 } },
  54. { 1326000000UL, { 1629068, -43435, 402 } },
  55. { 1428000000UL, { 1686950, -44715, 402 } },
  56. { 1530000000UL, { 1746653, -46005, 402 } },
  57. { 1632000000UL, { 1808179, -47285, 402 } },
  58. { 1734000000UL, { 1871526, -48575, 402 } },
  59. { 1836000000UL, { 1936696, -49855, 402 } },
  60. { 1938000000UL, { 2003687, -51145, 402 } },
  61. { 2014500000UL, { 2054787, -52095, 402 } },
  62. { 2116500000UL, { 2124957, -53385, 402 } },
  63. { 2218500000UL, { 2196950, -54665, 402 } },
  64. { 2320500000UL, { 2270765, -55955, 402 } },
  65. { 2422500000UL, { 2346401, -57235, 402 } },
  66. { 2524500000UL, { 2437299, -58535, 402 } },
  67. { 0UL, { 0, 0, 0 } },
  68. },
  69. .cpu_dfll_data = {
  70. .tune0_low = 0x005020ff,
  71. .tune0_high = 0x005040ff,
  72. .tune1 = 0x00000060,
  73. }
  74. },
  75. };
  76. static const unsigned long tegra210_cpu_max_freq_table[] = {
  77. [0] = 1912500000UL,
  78. [1] = 1912500000UL,
  79. [2] = 2218500000UL,
  80. [3] = 1785000000UL,
  81. [4] = 1632000000UL,
  82. [5] = 1912500000UL,
  83. [6] = 2014500000UL,
  84. [7] = 1734000000UL,
  85. [8] = 1683000000UL,
  86. [9] = 1555500000UL,
  87. [10] = 1504500000UL,
  88. };
  89. #define CPU_CVB_TABLE \
  90. .speedo_scale = 100, \
  91. .voltage_scale = 1000, \
  92. .entries = { \
  93. { 204000000UL, { 1007452, -23865, 370 } }, \
  94. { 306000000UL, { 1052709, -24875, 370 } }, \
  95. { 408000000UL, { 1099069, -25895, 370 } }, \
  96. { 510000000UL, { 1146534, -26905, 370 } }, \
  97. { 612000000UL, { 1195102, -27915, 370 } }, \
  98. { 714000000UL, { 1244773, -28925, 370 } }, \
  99. { 816000000UL, { 1295549, -29935, 370 } }, \
  100. { 918000000UL, { 1347428, -30955, 370 } }, \
  101. { 1020000000UL, { 1400411, -31965, 370 } }, \
  102. { 1122000000UL, { 1454497, -32975, 370 } }, \
  103. { 1224000000UL, { 1509687, -33985, 370 } }, \
  104. { 1326000000UL, { 1565981, -35005, 370 } }, \
  105. { 1428000000UL, { 1623379, -36015, 370 } }, \
  106. { 1530000000UL, { 1681880, -37025, 370 } }, \
  107. { 1632000000UL, { 1741485, -38035, 370 } }, \
  108. { 1734000000UL, { 1802194, -39055, 370 } }, \
  109. { 1836000000UL, { 1864006, -40065, 370 } }, \
  110. { 1912500000UL, { 1910780, -40815, 370 } }, \
  111. { 2014500000UL, { 1227000, 0, 0 } }, \
  112. { 2218500000UL, { 1227000, 0, 0 } }, \
  113. { 0UL, { 0, 0, 0 } }, \
  114. }
  115. #define CPU_CVB_TABLE_XA \
  116. .speedo_scale = 100, \
  117. .voltage_scale = 1000, \
  118. .entries = { \
  119. { 204000000UL, { 1250024, -39785, 565 } }, \
  120. { 306000000UL, { 1297556, -41145, 565 } }, \
  121. { 408000000UL, { 1346718, -42505, 565 } }, \
  122. { 510000000UL, { 1397511, -43855, 565 } }, \
  123. { 612000000UL, { 1449933, -45215, 565 } }, \
  124. { 714000000UL, { 1503986, -46575, 565 } }, \
  125. { 816000000UL, { 1559669, -47935, 565 } }, \
  126. { 918000000UL, { 1616982, -49295, 565 } }, \
  127. { 1020000000UL, { 1675926, -50645, 565 } }, \
  128. { 1122000000UL, { 1736500, -52005, 565 } }, \
  129. { 1224000000UL, { 1798704, -53365, 565 } }, \
  130. { 1326000000UL, { 1862538, -54725, 565 } }, \
  131. { 1428000000UL, { 1928003, -56085, 565 } }, \
  132. { 1530000000UL, { 1995097, -57435, 565 } }, \
  133. { 1606500000UL, { 2046149, -58445, 565 } }, \
  134. { 1632000000UL, { 2063822, -58795, 565 } }, \
  135. { 0UL, { 0, 0, 0 } }, \
  136. }
  137. #define CPU_CVB_TABLE_EUCM1 \
  138. .speedo_scale = 100, \
  139. .voltage_scale = 1000, \
  140. .entries = { \
  141. { 204000000UL, { 734429, 0, 0 } }, \
  142. { 306000000UL, { 768191, 0, 0 } }, \
  143. { 408000000UL, { 801953, 0, 0 } }, \
  144. { 510000000UL, { 835715, 0, 0 } }, \
  145. { 612000000UL, { 869477, 0, 0 } }, \
  146. { 714000000UL, { 903239, 0, 0 } }, \
  147. { 816000000UL, { 937001, 0, 0 } }, \
  148. { 918000000UL, { 970763, 0, 0 } }, \
  149. { 1020000000UL, { 1004525, 0, 0 } }, \
  150. { 1122000000UL, { 1038287, 0, 0 } }, \
  151. { 1224000000UL, { 1072049, 0, 0 } }, \
  152. { 1326000000UL, { 1105811, 0, 0 } }, \
  153. { 1428000000UL, { 1130000, 0, 0 } }, \
  154. { 1555500000UL, { 1130000, 0, 0 } }, \
  155. { 1632000000UL, { 1170000, 0, 0 } }, \
  156. { 1734000000UL, { 1227500, 0, 0 } }, \
  157. { 0UL, { 0, 0, 0 } }, \
  158. }
  159. #define CPU_CVB_TABLE_EUCM2 \
  160. .speedo_scale = 100, \
  161. .voltage_scale = 1000, \
  162. .entries = { \
  163. { 204000000UL, { 742283, 0, 0 } }, \
  164. { 306000000UL, { 776249, 0, 0 } }, \
  165. { 408000000UL, { 810215, 0, 0 } }, \
  166. { 510000000UL, { 844181, 0, 0 } }, \
  167. { 612000000UL, { 878147, 0, 0 } }, \
  168. { 714000000UL, { 912113, 0, 0 } }, \
  169. { 816000000UL, { 946079, 0, 0 } }, \
  170. { 918000000UL, { 980045, 0, 0 } }, \
  171. { 1020000000UL, { 1014011, 0, 0 } }, \
  172. { 1122000000UL, { 1047977, 0, 0 } }, \
  173. { 1224000000UL, { 1081943, 0, 0 } }, \
  174. { 1326000000UL, { 1090000, 0, 0 } }, \
  175. { 1479000000UL, { 1090000, 0, 0 } }, \
  176. { 1555500000UL, { 1162000, 0, 0 } }, \
  177. { 1683000000UL, { 1195000, 0, 0 } }, \
  178. { 0UL, { 0, 0, 0 } }, \
  179. }
  180. #define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
  181. .speedo_scale = 100, \
  182. .voltage_scale = 1000, \
  183. .entries = { \
  184. { 204000000UL, { 742283, 0, 0 } }, \
  185. { 306000000UL, { 776249, 0, 0 } }, \
  186. { 408000000UL, { 810215, 0, 0 } }, \
  187. { 510000000UL, { 844181, 0, 0 } }, \
  188. { 612000000UL, { 878147, 0, 0 } }, \
  189. { 714000000UL, { 912113, 0, 0 } }, \
  190. { 816000000UL, { 946079, 0, 0 } }, \
  191. { 918000000UL, { 980045, 0, 0 } }, \
  192. { 1020000000UL, { 1014011, 0, 0 } }, \
  193. { 1122000000UL, { 1047977, 0, 0 } }, \
  194. { 1224000000UL, { 1081943, 0, 0 } }, \
  195. { 1326000000UL, { 1090000, 0, 0 } }, \
  196. { 1479000000UL, { 1090000, 0, 0 } }, \
  197. { 1504500000UL, { 1120000, 0, 0 } }, \
  198. { 0UL, { 0, 0, 0 } }, \
  199. }
  200. #define CPU_CVB_TABLE_ODN \
  201. .speedo_scale = 100, \
  202. .voltage_scale = 1000, \
  203. .entries = { \
  204. { 204000000UL, { 721094, 0, 0 } }, \
  205. { 306000000UL, { 754040, 0, 0 } }, \
  206. { 408000000UL, { 786986, 0, 0 } }, \
  207. { 510000000UL, { 819932, 0, 0 } }, \
  208. { 612000000UL, { 852878, 0, 0 } }, \
  209. { 714000000UL, { 885824, 0, 0 } }, \
  210. { 816000000UL, { 918770, 0, 0 } }, \
  211. { 918000000UL, { 915716, 0, 0 } }, \
  212. { 1020000000UL, { 984662, 0, 0 } }, \
  213. { 1122000000UL, { 1017608, 0, 0 } }, \
  214. { 1224000000UL, { 1050554, 0, 0 } }, \
  215. { 1326000000UL, { 1083500, 0, 0 } }, \
  216. { 1428000000UL, { 1116446, 0, 0 } }, \
  217. { 1581000000UL, { 1130000, 0, 0 } }, \
  218. { 1683000000UL, { 1168000, 0, 0 } }, \
  219. { 1785000000UL, { 1227500, 0, 0 } }, \
  220. { 0UL, { 0, 0, 0 } }, \
  221. }
  222. static struct cvb_table tegra210_cpu_cvb_tables[] = {
  223. {
  224. .speedo_id = 10,
  225. .process_id = 0,
  226. .min_millivolts = 840,
  227. .max_millivolts = 1120,
  228. CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
  229. .cpu_dfll_data = {
  230. .tune0_low = 0xffead0ff,
  231. .tune0_high = 0xffead0ff,
  232. .tune1 = 0x20091d9,
  233. .tune_high_min_millivolts = 864,
  234. }
  235. },
  236. {
  237. .speedo_id = 10,
  238. .process_id = 1,
  239. .min_millivolts = 840,
  240. .max_millivolts = 1120,
  241. CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
  242. .cpu_dfll_data = {
  243. .tune0_low = 0xffead0ff,
  244. .tune0_high = 0xffead0ff,
  245. .tune1 = 0x20091d9,
  246. .tune_high_min_millivolts = 864,
  247. }
  248. },
  249. {
  250. .speedo_id = 9,
  251. .process_id = 0,
  252. .min_millivolts = 900,
  253. .max_millivolts = 1162,
  254. CPU_CVB_TABLE_EUCM2,
  255. .cpu_dfll_data = {
  256. .tune0_low = 0xffead0ff,
  257. .tune0_high = 0xffead0ff,
  258. .tune1 = 0x20091d9,
  259. }
  260. },
  261. {
  262. .speedo_id = 9,
  263. .process_id = 1,
  264. .min_millivolts = 900,
  265. .max_millivolts = 1162,
  266. CPU_CVB_TABLE_EUCM2,
  267. .cpu_dfll_data = {
  268. .tune0_low = 0xffead0ff,
  269. .tune0_high = 0xffead0ff,
  270. .tune1 = 0x20091d9,
  271. }
  272. },
  273. {
  274. .speedo_id = 8,
  275. .process_id = 0,
  276. .min_millivolts = 900,
  277. .max_millivolts = 1195,
  278. CPU_CVB_TABLE_EUCM2,
  279. .cpu_dfll_data = {
  280. .tune0_low = 0xffead0ff,
  281. .tune0_high = 0xffead0ff,
  282. .tune1 = 0x20091d9,
  283. }
  284. },
  285. {
  286. .speedo_id = 8,
  287. .process_id = 1,
  288. .min_millivolts = 900,
  289. .max_millivolts = 1195,
  290. CPU_CVB_TABLE_EUCM2,
  291. .cpu_dfll_data = {
  292. .tune0_low = 0xffead0ff,
  293. .tune0_high = 0xffead0ff,
  294. .tune1 = 0x20091d9,
  295. }
  296. },
  297. {
  298. .speedo_id = 7,
  299. .process_id = 0,
  300. .min_millivolts = 841,
  301. .max_millivolts = 1227,
  302. CPU_CVB_TABLE_EUCM1,
  303. .cpu_dfll_data = {
  304. .tune0_low = 0xffead0ff,
  305. .tune0_high = 0xffead0ff,
  306. .tune1 = 0x20091d9,
  307. .tune_high_min_millivolts = 864,
  308. }
  309. },
  310. {
  311. .speedo_id = 7,
  312. .process_id = 1,
  313. .min_millivolts = 841,
  314. .max_millivolts = 1227,
  315. CPU_CVB_TABLE_EUCM1,
  316. .cpu_dfll_data = {
  317. .tune0_low = 0xffead0ff,
  318. .tune0_high = 0xffead0ff,
  319. .tune1 = 0x20091d9,
  320. .tune_high_min_millivolts = 864,
  321. }
  322. },
  323. {
  324. .speedo_id = 6,
  325. .process_id = 0,
  326. .min_millivolts = 870,
  327. .max_millivolts = 1150,
  328. CPU_CVB_TABLE,
  329. .cpu_dfll_data = {
  330. .tune0_low = 0xffead0ff,
  331. .tune1 = 0x20091d9,
  332. }
  333. },
  334. {
  335. .speedo_id = 6,
  336. .process_id = 1,
  337. .min_millivolts = 870,
  338. .max_millivolts = 1150,
  339. CPU_CVB_TABLE,
  340. .cpu_dfll_data = {
  341. .tune0_low = 0xffead0ff,
  342. .tune1 = 0x25501d0,
  343. }
  344. },
  345. {
  346. .speedo_id = 5,
  347. .process_id = 0,
  348. .min_millivolts = 818,
  349. .max_millivolts = 1227,
  350. CPU_CVB_TABLE,
  351. .cpu_dfll_data = {
  352. .tune0_low = 0xffead0ff,
  353. .tune0_high = 0xffead0ff,
  354. .tune1 = 0x20091d9,
  355. .tune_high_min_millivolts = 864,
  356. }
  357. },
  358. {
  359. .speedo_id = 5,
  360. .process_id = 1,
  361. .min_millivolts = 818,
  362. .max_millivolts = 1227,
  363. CPU_CVB_TABLE,
  364. .cpu_dfll_data = {
  365. .tune0_low = 0xffead0ff,
  366. .tune0_high = 0xffead0ff,
  367. .tune1 = 0x25501d0,
  368. .tune_high_min_millivolts = 864,
  369. }
  370. },
  371. {
  372. .speedo_id = 4,
  373. .process_id = -1,
  374. .min_millivolts = 918,
  375. .max_millivolts = 1113,
  376. CPU_CVB_TABLE_XA,
  377. .cpu_dfll_data = {
  378. .tune0_low = 0xffead0ff,
  379. .tune1 = 0x17711BD,
  380. }
  381. },
  382. {
  383. .speedo_id = 3,
  384. .process_id = 0,
  385. .min_millivolts = 825,
  386. .max_millivolts = 1227,
  387. CPU_CVB_TABLE_ODN,
  388. .cpu_dfll_data = {
  389. .tune0_low = 0xffead0ff,
  390. .tune0_high = 0xffead0ff,
  391. .tune1 = 0x20091d9,
  392. .tune_high_min_millivolts = 864,
  393. }
  394. },
  395. {
  396. .speedo_id = 3,
  397. .process_id = 1,
  398. .min_millivolts = 825,
  399. .max_millivolts = 1227,
  400. CPU_CVB_TABLE_ODN,
  401. .cpu_dfll_data = {
  402. .tune0_low = 0xffead0ff,
  403. .tune0_high = 0xffead0ff,
  404. .tune1 = 0x25501d0,
  405. .tune_high_min_millivolts = 864,
  406. }
  407. },
  408. {
  409. .speedo_id = 2,
  410. .process_id = 0,
  411. .min_millivolts = 870,
  412. .max_millivolts = 1227,
  413. CPU_CVB_TABLE,
  414. .cpu_dfll_data = {
  415. .tune0_low = 0xffead0ff,
  416. .tune1 = 0x20091d9,
  417. }
  418. },
  419. {
  420. .speedo_id = 2,
  421. .process_id = 1,
  422. .min_millivolts = 870,
  423. .max_millivolts = 1227,
  424. CPU_CVB_TABLE,
  425. .cpu_dfll_data = {
  426. .tune0_low = 0xffead0ff,
  427. .tune1 = 0x25501d0,
  428. }
  429. },
  430. {
  431. .speedo_id = 1,
  432. .process_id = 0,
  433. .min_millivolts = 837,
  434. .max_millivolts = 1227,
  435. CPU_CVB_TABLE,
  436. .cpu_dfll_data = {
  437. .tune0_low = 0xffead0ff,
  438. .tune0_high = 0xffead0ff,
  439. .tune1 = 0x20091d9,
  440. .tune_high_min_millivolts = 864,
  441. }
  442. },
  443. {
  444. .speedo_id = 1,
  445. .process_id = 1,
  446. .min_millivolts = 837,
  447. .max_millivolts = 1227,
  448. CPU_CVB_TABLE,
  449. .cpu_dfll_data = {
  450. .tune0_low = 0xffead0ff,
  451. .tune0_high = 0xffead0ff,
  452. .tune1 = 0x25501d0,
  453. .tune_high_min_millivolts = 864,
  454. }
  455. },
  456. {
  457. .speedo_id = 0,
  458. .process_id = 0,
  459. .min_millivolts = 850,
  460. .max_millivolts = 1170,
  461. CPU_CVB_TABLE,
  462. .cpu_dfll_data = {
  463. .tune0_low = 0xffead0ff,
  464. .tune0_high = 0xffead0ff,
  465. .tune1 = 0x20091d9,
  466. .tune_high_min_millivolts = 864,
  467. }
  468. },
  469. {
  470. .speedo_id = 0,
  471. .process_id = 1,
  472. .min_millivolts = 850,
  473. .max_millivolts = 1170,
  474. CPU_CVB_TABLE,
  475. .cpu_dfll_data = {
  476. .tune0_low = 0xffead0ff,
  477. .tune0_high = 0xffead0ff,
  478. .tune1 = 0x25501d0,
  479. .tune_high_min_millivolts = 864,
  480. }
  481. },
  482. };
  483. static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
  484. .cpu_max_freq_table = tegra124_cpu_max_freq_table,
  485. .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
  486. .cpu_cvb_tables = tegra124_cpu_cvb_tables,
  487. .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
  488. };
  489. static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
  490. .cpu_max_freq_table = tegra210_cpu_max_freq_table,
  491. .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
  492. .cpu_cvb_tables = tegra210_cpu_cvb_tables,
  493. .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
  494. };
  495. static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
  496. {
  497. .compatible = "nvidia,tegra124-dfll",
  498. .data = &tegra124_dfll_fcpu_data,
  499. },
  500. {
  501. .compatible = "nvidia,tegra210-dfll",
  502. .data = &tegra210_dfll_fcpu_data
  503. },
  504. { },
  505. };
  506. static void get_alignment_from_dt(struct device *dev,
  507. struct rail_alignment *align)
  508. {
  509. if (of_property_read_u32(dev->of_node,
  510. "nvidia,pwm-voltage-step-microvolts",
  511. &align->step_uv))
  512. align->step_uv = 0;
  513. if (of_property_read_u32(dev->of_node,
  514. "nvidia,pwm-min-microvolts",
  515. &align->offset_uv))
  516. align->offset_uv = 0;
  517. }
  518. static int get_alignment_from_regulator(struct device *dev,
  519. struct rail_alignment *align)
  520. {
  521. struct regulator *reg = devm_regulator_get(dev, "vdd-cpu");
  522. if (IS_ERR(reg))
  523. return PTR_ERR(reg);
  524. align->offset_uv = regulator_list_voltage(reg, 0);
  525. align->step_uv = regulator_get_linear_step(reg);
  526. devm_regulator_put(reg);
  527. return 0;
  528. }
  529. static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
  530. {
  531. int process_id, speedo_id, speedo_value, err;
  532. struct tegra_dfll_soc_data *soc;
  533. const struct dfll_fcpu_data *fcpu_data;
  534. struct rail_alignment align;
  535. fcpu_data = of_device_get_match_data(&pdev->dev);
  536. if (!fcpu_data)
  537. return -ENODEV;
  538. process_id = tegra_sku_info.cpu_process_id;
  539. speedo_id = tegra_sku_info.cpu_speedo_id;
  540. speedo_value = tegra_sku_info.cpu_speedo_value;
  541. if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
  542. dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
  543. speedo_id);
  544. return -ENODEV;
  545. }
  546. soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
  547. if (!soc)
  548. return -ENOMEM;
  549. soc->dev = get_cpu_device(0);
  550. if (!soc->dev) {
  551. dev_err(&pdev->dev, "no CPU0 device\n");
  552. return -ENODEV;
  553. }
  554. if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) {
  555. get_alignment_from_dt(&pdev->dev, &align);
  556. } else {
  557. err = get_alignment_from_regulator(&pdev->dev, &align);
  558. if (err)
  559. return err;
  560. }
  561. soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
  562. soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
  563. fcpu_data->cpu_cvb_tables_size,
  564. &align, process_id, speedo_id,
  565. speedo_value, soc->max_freq);
  566. soc->alignment = align;
  567. if (IS_ERR(soc->cvb)) {
  568. dev_err(&pdev->dev, "couldn't add OPP table: %ld\n",
  569. PTR_ERR(soc->cvb));
  570. return PTR_ERR(soc->cvb);
  571. }
  572. err = tegra_dfll_register(pdev, soc);
  573. if (err < 0) {
  574. tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
  575. return err;
  576. }
  577. return 0;
  578. }
  579. static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
  580. {
  581. struct tegra_dfll_soc_data *soc;
  582. soc = tegra_dfll_unregister(pdev);
  583. if (IS_ERR(soc)) {
  584. dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
  585. PTR_ERR(soc));
  586. return PTR_ERR(soc);
  587. }
  588. tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
  589. return 0;
  590. }
  591. static const struct dev_pm_ops tegra124_dfll_pm_ops = {
  592. SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
  593. tegra_dfll_runtime_resume, NULL)
  594. SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
  595. };
  596. static struct platform_driver tegra124_dfll_fcpu_driver = {
  597. .probe = tegra124_dfll_fcpu_probe,
  598. .remove = tegra124_dfll_fcpu_remove,
  599. .driver = {
  600. .name = "tegra124-dfll",
  601. .of_match_table = tegra124_dfll_fcpu_of_match,
  602. .pm = &tegra124_dfll_pm_ops,
  603. },
  604. };
  605. builtin_platform_driver(tegra124_dfll_fcpu_driver);