clk-tegra114.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/delay.h>
  10. #include <linux/export.h>
  11. #include <linux/clk/tegra.h>
  12. #include <dt-bindings/clock/tegra114-car.h>
  13. #include "clk.h"
  14. #include "clk-id.h"
  15. #define RST_DFLL_DVCO 0x2F4
  16. #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
  17. #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
  18. #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
  19. /* RST_DFLL_DVCO bitfields */
  20. #define DVFS_DFLL_RESET_SHIFT 0
  21. /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
  22. #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
  23. #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
  24. #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
  25. #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
  26. #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
  27. #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
  28. /* CPU_FINETRIM_R bitfields */
  29. #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
  30. #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
  31. #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
  32. #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
  33. #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
  34. #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
  35. #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
  36. #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
  37. #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
  38. #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
  39. #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
  40. #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
  41. #define TEGRA114_CLK_PERIPH_BANKS 5
  42. #define PLLC_BASE 0x80
  43. #define PLLC_MISC2 0x88
  44. #define PLLC_MISC 0x8c
  45. #define PLLC2_BASE 0x4e8
  46. #define PLLC2_MISC 0x4ec
  47. #define PLLC3_BASE 0x4fc
  48. #define PLLC3_MISC 0x500
  49. #define PLLM_BASE 0x90
  50. #define PLLM_MISC 0x9c
  51. #define PLLP_BASE 0xa0
  52. #define PLLP_MISC 0xac
  53. #define PLLX_BASE 0xe0
  54. #define PLLX_MISC 0xe4
  55. #define PLLX_MISC2 0x514
  56. #define PLLX_MISC3 0x518
  57. #define PLLD_BASE 0xd0
  58. #define PLLD_MISC 0xdc
  59. #define PLLD2_BASE 0x4b8
  60. #define PLLD2_MISC 0x4bc
  61. #define PLLE_BASE 0xe8
  62. #define PLLE_MISC 0xec
  63. #define PLLA_BASE 0xb0
  64. #define PLLA_MISC 0xbc
  65. #define PLLU_BASE 0xc0
  66. #define PLLU_MISC 0xcc
  67. #define PLLRE_BASE 0x4c4
  68. #define PLLRE_MISC 0x4c8
  69. #define PLL_MISC_LOCK_ENABLE 18
  70. #define PLLC_MISC_LOCK_ENABLE 24
  71. #define PLLDU_MISC_LOCK_ENABLE 22
  72. #define PLLE_MISC_LOCK_ENABLE 9
  73. #define PLLRE_MISC_LOCK_ENABLE 30
  74. #define PLLC_IDDQ_BIT 26
  75. #define PLLX_IDDQ_BIT 3
  76. #define PLLRE_IDDQ_BIT 16
  77. #define PLL_BASE_LOCK BIT(27)
  78. #define PLLE_MISC_LOCK BIT(11)
  79. #define PLLRE_MISC_LOCK BIT(24)
  80. #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
  81. #define PLLE_AUX 0x48c
  82. #define PLLC_OUT 0x84
  83. #define PLLM_OUT 0x94
  84. #define OSC_CTRL 0x50
  85. #define OSC_CTRL_OSC_FREQ_SHIFT 28
  86. #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
  87. #define PLLXC_SW_MAX_P 6
  88. #define CCLKG_BURST_POLICY 0x368
  89. #define CLK_SOURCE_CSITE 0x1d4
  90. #define CLK_SOURCE_EMC 0x19c
  91. /* PLLM override registers */
  92. #define PMC_PLLM_WB0_OVERRIDE 0x1dc
  93. #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
  94. /* Tegra CPU clock and reset control regs */
  95. #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
  96. #define MUX8(_name, _parents, _offset, \
  97. _clk_num, _gate_flags, _clk_id) \
  98. TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
  99. 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
  100. _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
  101. NULL)
  102. #ifdef CONFIG_PM_SLEEP
  103. static struct cpu_clk_suspend_context {
  104. u32 clk_csite_src;
  105. u32 cclkg_burst;
  106. u32 cclkg_divider;
  107. } tegra114_cpu_clk_sctx;
  108. #endif
  109. static void __iomem *clk_base;
  110. static void __iomem *pmc_base;
  111. static DEFINE_SPINLOCK(pll_d_lock);
  112. static DEFINE_SPINLOCK(pll_d2_lock);
  113. static DEFINE_SPINLOCK(pll_u_lock);
  114. static DEFINE_SPINLOCK(pll_re_lock);
  115. static DEFINE_SPINLOCK(emc_lock);
  116. static struct div_nmp pllxc_nmp = {
  117. .divm_shift = 0,
  118. .divm_width = 8,
  119. .divn_shift = 8,
  120. .divn_width = 8,
  121. .divp_shift = 20,
  122. .divp_width = 4,
  123. };
  124. static const struct pdiv_map pllxc_p[] = {
  125. { .pdiv = 1, .hw_val = 0 },
  126. { .pdiv = 2, .hw_val = 1 },
  127. { .pdiv = 3, .hw_val = 2 },
  128. { .pdiv = 4, .hw_val = 3 },
  129. { .pdiv = 5, .hw_val = 4 },
  130. { .pdiv = 6, .hw_val = 5 },
  131. { .pdiv = 8, .hw_val = 6 },
  132. { .pdiv = 10, .hw_val = 7 },
  133. { .pdiv = 12, .hw_val = 8 },
  134. { .pdiv = 16, .hw_val = 9 },
  135. { .pdiv = 12, .hw_val = 10 },
  136. { .pdiv = 16, .hw_val = 11 },
  137. { .pdiv = 20, .hw_val = 12 },
  138. { .pdiv = 24, .hw_val = 13 },
  139. { .pdiv = 32, .hw_val = 14 },
  140. { .pdiv = 0, .hw_val = 0 },
  141. };
  142. static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
  143. { 12000000, 624000000, 104, 1, 2, 0 },
  144. { 12000000, 600000000, 100, 1, 2, 0 },
  145. { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
  146. { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
  147. { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
  148. { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
  149. { 0, 0, 0, 0, 0, 0 },
  150. };
  151. static struct tegra_clk_pll_params pll_c_params = {
  152. .input_min = 12000000,
  153. .input_max = 800000000,
  154. .cf_min = 12000000,
  155. .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
  156. .vco_min = 600000000,
  157. .vco_max = 1400000000,
  158. .base_reg = PLLC_BASE,
  159. .misc_reg = PLLC_MISC,
  160. .lock_mask = PLL_BASE_LOCK,
  161. .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
  162. .lock_delay = 300,
  163. .iddq_reg = PLLC_MISC,
  164. .iddq_bit_idx = PLLC_IDDQ_BIT,
  165. .max_p = PLLXC_SW_MAX_P,
  166. .dyn_ramp_reg = PLLC_MISC2,
  167. .stepa_shift = 17,
  168. .stepb_shift = 9,
  169. .pdiv_tohw = pllxc_p,
  170. .div_nmp = &pllxc_nmp,
  171. .freq_table = pll_c_freq_table,
  172. .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  173. };
  174. static struct div_nmp pllcx_nmp = {
  175. .divm_shift = 0,
  176. .divm_width = 2,
  177. .divn_shift = 8,
  178. .divn_width = 8,
  179. .divp_shift = 20,
  180. .divp_width = 3,
  181. };
  182. static const struct pdiv_map pllc_p[] = {
  183. { .pdiv = 1, .hw_val = 0 },
  184. { .pdiv = 2, .hw_val = 1 },
  185. { .pdiv = 4, .hw_val = 3 },
  186. { .pdiv = 8, .hw_val = 5 },
  187. { .pdiv = 16, .hw_val = 7 },
  188. { .pdiv = 0, .hw_val = 0 },
  189. };
  190. static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
  191. { 12000000, 600000000, 100, 1, 2, 0 },
  192. { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
  193. { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
  194. { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
  195. { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
  196. { 0, 0, 0, 0, 0, 0 },
  197. };
  198. static struct tegra_clk_pll_params pll_c2_params = {
  199. .input_min = 12000000,
  200. .input_max = 48000000,
  201. .cf_min = 12000000,
  202. .cf_max = 19200000,
  203. .vco_min = 600000000,
  204. .vco_max = 1200000000,
  205. .base_reg = PLLC2_BASE,
  206. .misc_reg = PLLC2_MISC,
  207. .lock_mask = PLL_BASE_LOCK,
  208. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  209. .lock_delay = 300,
  210. .pdiv_tohw = pllc_p,
  211. .div_nmp = &pllcx_nmp,
  212. .max_p = 7,
  213. .ext_misc_reg[0] = 0x4f0,
  214. .ext_misc_reg[1] = 0x4f4,
  215. .ext_misc_reg[2] = 0x4f8,
  216. .freq_table = pll_cx_freq_table,
  217. .flags = TEGRA_PLL_USE_LOCK,
  218. };
  219. static struct tegra_clk_pll_params pll_c3_params = {
  220. .input_min = 12000000,
  221. .input_max = 48000000,
  222. .cf_min = 12000000,
  223. .cf_max = 19200000,
  224. .vco_min = 600000000,
  225. .vco_max = 1200000000,
  226. .base_reg = PLLC3_BASE,
  227. .misc_reg = PLLC3_MISC,
  228. .lock_mask = PLL_BASE_LOCK,
  229. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  230. .lock_delay = 300,
  231. .pdiv_tohw = pllc_p,
  232. .div_nmp = &pllcx_nmp,
  233. .max_p = 7,
  234. .ext_misc_reg[0] = 0x504,
  235. .ext_misc_reg[1] = 0x508,
  236. .ext_misc_reg[2] = 0x50c,
  237. .freq_table = pll_cx_freq_table,
  238. .flags = TEGRA_PLL_USE_LOCK,
  239. };
  240. static struct div_nmp pllm_nmp = {
  241. .divm_shift = 0,
  242. .divm_width = 8,
  243. .override_divm_shift = 0,
  244. .divn_shift = 8,
  245. .divn_width = 8,
  246. .override_divn_shift = 8,
  247. .divp_shift = 20,
  248. .divp_width = 1,
  249. .override_divp_shift = 27,
  250. };
  251. static const struct pdiv_map pllm_p[] = {
  252. { .pdiv = 1, .hw_val = 0 },
  253. { .pdiv = 2, .hw_val = 1 },
  254. { .pdiv = 0, .hw_val = 0 },
  255. };
  256. static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
  257. { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
  258. { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
  259. { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
  260. { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
  261. { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
  262. { 0, 0, 0, 0, 0, 0 },
  263. };
  264. static struct tegra_clk_pll_params pll_m_params = {
  265. .input_min = 12000000,
  266. .input_max = 500000000,
  267. .cf_min = 12000000,
  268. .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
  269. .vco_min = 400000000,
  270. .vco_max = 1066000000,
  271. .base_reg = PLLM_BASE,
  272. .misc_reg = PLLM_MISC,
  273. .lock_mask = PLL_BASE_LOCK,
  274. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  275. .lock_delay = 300,
  276. .max_p = 2,
  277. .pdiv_tohw = pllm_p,
  278. .div_nmp = &pllm_nmp,
  279. .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
  280. .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
  281. .freq_table = pll_m_freq_table,
  282. .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
  283. TEGRA_PLL_FIXED,
  284. };
  285. static struct div_nmp pllp_nmp = {
  286. .divm_shift = 0,
  287. .divm_width = 5,
  288. .divn_shift = 8,
  289. .divn_width = 10,
  290. .divp_shift = 20,
  291. .divp_width = 3,
  292. };
  293. static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
  294. { 12000000, 216000000, 432, 12, 2, 8 },
  295. { 13000000, 216000000, 432, 13, 2, 8 },
  296. { 16800000, 216000000, 360, 14, 2, 8 },
  297. { 19200000, 216000000, 360, 16, 2, 8 },
  298. { 26000000, 216000000, 432, 26, 2, 8 },
  299. { 0, 0, 0, 0, 0, 0 },
  300. };
  301. static struct tegra_clk_pll_params pll_p_params = {
  302. .input_min = 2000000,
  303. .input_max = 31000000,
  304. .cf_min = 1000000,
  305. .cf_max = 6000000,
  306. .vco_min = 200000000,
  307. .vco_max = 700000000,
  308. .base_reg = PLLP_BASE,
  309. .misc_reg = PLLP_MISC,
  310. .lock_mask = PLL_BASE_LOCK,
  311. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  312. .lock_delay = 300,
  313. .div_nmp = &pllp_nmp,
  314. .freq_table = pll_p_freq_table,
  315. .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
  316. TEGRA_PLL_HAS_LOCK_ENABLE,
  317. .fixed_rate = 408000000,
  318. };
  319. static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
  320. { 9600000, 282240000, 147, 5, 1, 4 },
  321. { 9600000, 368640000, 192, 5, 1, 4 },
  322. { 9600000, 240000000, 200, 8, 1, 8 },
  323. { 28800000, 282240000, 245, 25, 1, 8 },
  324. { 28800000, 368640000, 320, 25, 1, 8 },
  325. { 28800000, 240000000, 200, 24, 1, 8 },
  326. { 0, 0, 0, 0, 0, 0 },
  327. };
  328. static struct tegra_clk_pll_params pll_a_params = {
  329. .input_min = 2000000,
  330. .input_max = 31000000,
  331. .cf_min = 1000000,
  332. .cf_max = 6000000,
  333. .vco_min = 200000000,
  334. .vco_max = 700000000,
  335. .base_reg = PLLA_BASE,
  336. .misc_reg = PLLA_MISC,
  337. .lock_mask = PLL_BASE_LOCK,
  338. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  339. .lock_delay = 300,
  340. .div_nmp = &pllp_nmp,
  341. .freq_table = pll_a_freq_table,
  342. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
  343. TEGRA_PLL_HAS_LOCK_ENABLE,
  344. };
  345. static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
  346. { 12000000, 216000000, 864, 12, 4, 12 },
  347. { 13000000, 216000000, 864, 13, 4, 12 },
  348. { 16800000, 216000000, 720, 14, 4, 12 },
  349. { 19200000, 216000000, 720, 16, 4, 12 },
  350. { 26000000, 216000000, 864, 26, 4, 12 },
  351. { 12000000, 594000000, 594, 12, 1, 12 },
  352. { 13000000, 594000000, 594, 13, 1, 12 },
  353. { 16800000, 594000000, 495, 14, 1, 12 },
  354. { 19200000, 594000000, 495, 16, 1, 12 },
  355. { 26000000, 594000000, 594, 26, 1, 12 },
  356. { 12000000, 1000000000, 1000, 12, 1, 12 },
  357. { 13000000, 1000000000, 1000, 13, 1, 12 },
  358. { 19200000, 1000000000, 625, 12, 1, 12 },
  359. { 26000000, 1000000000, 1000, 26, 1, 12 },
  360. { 0, 0, 0, 0, 0, 0 },
  361. };
  362. static struct tegra_clk_pll_params pll_d_params = {
  363. .input_min = 2000000,
  364. .input_max = 40000000,
  365. .cf_min = 1000000,
  366. .cf_max = 6000000,
  367. .vco_min = 500000000,
  368. .vco_max = 1000000000,
  369. .base_reg = PLLD_BASE,
  370. .misc_reg = PLLD_MISC,
  371. .lock_mask = PLL_BASE_LOCK,
  372. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  373. .lock_delay = 1000,
  374. .div_nmp = &pllp_nmp,
  375. .freq_table = pll_d_freq_table,
  376. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  377. TEGRA_PLL_HAS_LOCK_ENABLE,
  378. };
  379. static struct tegra_clk_pll_params pll_d2_params = {
  380. .input_min = 2000000,
  381. .input_max = 40000000,
  382. .cf_min = 1000000,
  383. .cf_max = 6000000,
  384. .vco_min = 500000000,
  385. .vco_max = 1000000000,
  386. .base_reg = PLLD2_BASE,
  387. .misc_reg = PLLD2_MISC,
  388. .lock_mask = PLL_BASE_LOCK,
  389. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  390. .lock_delay = 1000,
  391. .div_nmp = &pllp_nmp,
  392. .freq_table = pll_d_freq_table,
  393. .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  394. TEGRA_PLL_HAS_LOCK_ENABLE,
  395. };
  396. static const struct pdiv_map pllu_p[] = {
  397. { .pdiv = 1, .hw_val = 1 },
  398. { .pdiv = 2, .hw_val = 0 },
  399. { .pdiv = 0, .hw_val = 0 },
  400. };
  401. static struct div_nmp pllu_nmp = {
  402. .divm_shift = 0,
  403. .divm_width = 5,
  404. .divn_shift = 8,
  405. .divn_width = 10,
  406. .divp_shift = 20,
  407. .divp_width = 1,
  408. };
  409. static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
  410. { 12000000, 480000000, 960, 12, 2, 12 },
  411. { 13000000, 480000000, 960, 13, 2, 12 },
  412. { 16800000, 480000000, 400, 7, 2, 5 },
  413. { 19200000, 480000000, 200, 4, 2, 3 },
  414. { 26000000, 480000000, 960, 26, 2, 12 },
  415. { 0, 0, 0, 0, 0, 0 },
  416. };
  417. static struct tegra_clk_pll_params pll_u_params = {
  418. .input_min = 2000000,
  419. .input_max = 40000000,
  420. .cf_min = 1000000,
  421. .cf_max = 6000000,
  422. .vco_min = 480000000,
  423. .vco_max = 960000000,
  424. .base_reg = PLLU_BASE,
  425. .misc_reg = PLLU_MISC,
  426. .lock_mask = PLL_BASE_LOCK,
  427. .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
  428. .lock_delay = 1000,
  429. .pdiv_tohw = pllu_p,
  430. .div_nmp = &pllu_nmp,
  431. .freq_table = pll_u_freq_table,
  432. .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
  433. TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  434. };
  435. static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
  436. /* 1 GHz */
  437. { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
  438. { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
  439. { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
  440. { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
  441. { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
  442. { 0, 0, 0, 0, 0, 0 },
  443. };
  444. static struct tegra_clk_pll_params pll_x_params = {
  445. .input_min = 12000000,
  446. .input_max = 800000000,
  447. .cf_min = 12000000,
  448. .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
  449. .vco_min = 700000000,
  450. .vco_max = 2400000000U,
  451. .base_reg = PLLX_BASE,
  452. .misc_reg = PLLX_MISC,
  453. .lock_mask = PLL_BASE_LOCK,
  454. .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
  455. .lock_delay = 300,
  456. .iddq_reg = PLLX_MISC3,
  457. .iddq_bit_idx = PLLX_IDDQ_BIT,
  458. .max_p = PLLXC_SW_MAX_P,
  459. .dyn_ramp_reg = PLLX_MISC2,
  460. .stepa_shift = 16,
  461. .stepb_shift = 24,
  462. .pdiv_tohw = pllxc_p,
  463. .div_nmp = &pllxc_nmp,
  464. .freq_table = pll_x_freq_table,
  465. .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
  466. };
  467. static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
  468. /* PLLE special case: use cpcon field to store cml divider value */
  469. { 336000000, 100000000, 100, 21, 16, 11 },
  470. { 312000000, 100000000, 200, 26, 24, 13 },
  471. { 12000000, 100000000, 200, 1, 24, 13 },
  472. { 0, 0, 0, 0, 0, 0 },
  473. };
  474. static const struct pdiv_map plle_p[] = {
  475. { .pdiv = 1, .hw_val = 0 },
  476. { .pdiv = 2, .hw_val = 1 },
  477. { .pdiv = 3, .hw_val = 2 },
  478. { .pdiv = 4, .hw_val = 3 },
  479. { .pdiv = 5, .hw_val = 4 },
  480. { .pdiv = 6, .hw_val = 5 },
  481. { .pdiv = 8, .hw_val = 6 },
  482. { .pdiv = 10, .hw_val = 7 },
  483. { .pdiv = 12, .hw_val = 8 },
  484. { .pdiv = 16, .hw_val = 9 },
  485. { .pdiv = 12, .hw_val = 10 },
  486. { .pdiv = 16, .hw_val = 11 },
  487. { .pdiv = 20, .hw_val = 12 },
  488. { .pdiv = 24, .hw_val = 13 },
  489. { .pdiv = 32, .hw_val = 14 },
  490. { .pdiv = 0, .hw_val = 0 }
  491. };
  492. static struct div_nmp plle_nmp = {
  493. .divm_shift = 0,
  494. .divm_width = 8,
  495. .divn_shift = 8,
  496. .divn_width = 8,
  497. .divp_shift = 24,
  498. .divp_width = 4,
  499. };
  500. static struct tegra_clk_pll_params pll_e_params = {
  501. .input_min = 12000000,
  502. .input_max = 1000000000,
  503. .cf_min = 12000000,
  504. .cf_max = 75000000,
  505. .vco_min = 1600000000,
  506. .vco_max = 2400000000U,
  507. .base_reg = PLLE_BASE,
  508. .misc_reg = PLLE_MISC,
  509. .aux_reg = PLLE_AUX,
  510. .lock_mask = PLLE_MISC_LOCK,
  511. .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
  512. .lock_delay = 300,
  513. .pdiv_tohw = plle_p,
  514. .div_nmp = &plle_nmp,
  515. .freq_table = pll_e_freq_table,
  516. .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
  517. .fixed_rate = 100000000,
  518. };
  519. static struct div_nmp pllre_nmp = {
  520. .divm_shift = 0,
  521. .divm_width = 8,
  522. .divn_shift = 8,
  523. .divn_width = 8,
  524. .divp_shift = 16,
  525. .divp_width = 4,
  526. };
  527. static struct tegra_clk_pll_params pll_re_vco_params = {
  528. .input_min = 12000000,
  529. .input_max = 1000000000,
  530. .cf_min = 12000000,
  531. .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
  532. .vco_min = 300000000,
  533. .vco_max = 600000000,
  534. .base_reg = PLLRE_BASE,
  535. .misc_reg = PLLRE_MISC,
  536. .lock_mask = PLLRE_MISC_LOCK,
  537. .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
  538. .lock_delay = 300,
  539. .iddq_reg = PLLRE_MISC,
  540. .iddq_bit_idx = PLLRE_IDDQ_BIT,
  541. .div_nmp = &pllre_nmp,
  542. .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
  543. TEGRA_PLL_LOCK_MISC,
  544. };
  545. /* possible OSC frequencies in Hz */
  546. static unsigned long tegra114_input_freq[] = {
  547. [ 0] = 13000000,
  548. [ 1] = 16800000,
  549. [ 4] = 19200000,
  550. [ 5] = 38400000,
  551. [ 8] = 12000000,
  552. [ 9] = 48000000,
  553. [12] = 26000000,
  554. };
  555. #define MASK(x) (BIT(x) - 1)
  556. /* peripheral mux definitions */
  557. static const char *mux_plld_out0_plld2_out0[] = {
  558. "pll_d_out0", "pll_d2_out0",
  559. };
  560. #define mux_plld_out0_plld2_out0_idx NULL
  561. static const char *mux_pllmcp_clkm[] = {
  562. "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
  563. };
  564. static const struct clk_div_table pll_re_div_table[] = {
  565. { .val = 0, .div = 1 },
  566. { .val = 1, .div = 2 },
  567. { .val = 2, .div = 3 },
  568. { .val = 3, .div = 4 },
  569. { .val = 4, .div = 5 },
  570. { .val = 5, .div = 6 },
  571. { .val = 0, .div = 0 },
  572. };
  573. static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
  574. [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
  575. [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
  576. [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
  577. [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
  578. [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
  579. [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
  580. [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
  581. [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
  582. [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
  583. [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
  584. [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
  585. [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
  586. [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
  587. [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
  588. [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
  589. [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
  590. [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
  591. [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
  592. [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
  593. [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
  594. [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
  595. [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
  596. [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
  597. [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
  598. [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
  599. [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
  600. [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
  601. [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
  602. [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
  603. [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
  604. [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
  605. [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
  606. [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
  607. [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
  608. [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
  609. [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
  610. [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
  611. [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
  612. [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
  613. [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
  614. [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
  615. [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
  616. [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
  617. [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
  618. [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
  619. [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
  620. [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
  621. [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
  622. [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
  623. [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
  624. [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
  625. [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
  626. [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
  627. [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
  628. [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
  629. [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
  630. [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
  631. [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
  632. [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
  633. [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
  634. [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
  635. [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
  636. [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
  637. [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
  638. [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
  639. [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
  640. [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
  641. [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
  642. [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
  643. [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
  644. [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
  645. [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
  646. [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
  647. [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
  648. [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
  649. [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
  650. [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
  651. [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
  652. [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
  653. [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
  654. [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
  655. [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
  656. [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
  657. [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
  658. [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
  659. [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
  660. [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
  661. [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
  662. [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
  663. [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
  664. [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
  665. [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
  666. [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
  667. [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
  668. [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
  669. [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
  670. [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
  671. [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
  672. [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
  673. [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
  674. [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
  675. [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
  676. [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
  677. [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
  678. [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
  679. [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
  680. [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
  681. [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
  682. [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
  683. [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
  684. [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
  685. [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
  686. [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
  687. [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
  688. [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
  689. [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
  690. [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
  691. [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
  692. [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
  693. [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
  694. [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
  695. [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
  696. [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
  697. [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
  698. [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
  699. [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
  700. [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
  701. [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
  702. [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
  703. [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
  704. [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
  705. [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
  706. [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
  707. [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
  708. [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
  709. [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
  710. [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
  711. [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
  712. [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
  713. [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
  714. [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
  715. [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
  716. [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
  717. [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
  718. [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
  719. [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
  720. [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
  721. [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
  722. [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
  723. [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
  724. [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
  725. [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
  726. [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
  727. [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
  728. [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
  729. [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
  730. [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
  731. [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
  732. [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
  733. [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
  734. [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
  735. [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
  736. [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
  737. [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
  738. [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
  739. [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
  740. [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
  741. [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
  742. [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
  743. };
  744. static struct tegra_devclk devclks[] __initdata = {
  745. { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
  746. { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
  747. { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
  748. { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
  749. { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
  750. { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
  751. { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
  752. { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
  753. { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
  754. { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
  755. { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
  756. { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
  757. { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
  758. { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
  759. { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
  760. { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
  761. { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
  762. { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
  763. { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
  764. { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
  765. { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
  766. { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
  767. { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
  768. { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
  769. { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
  770. { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
  771. { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
  772. { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
  773. { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
  774. { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
  775. { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
  776. { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
  777. { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
  778. { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
  779. { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
  780. { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
  781. { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
  782. { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
  783. { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
  784. { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
  785. { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
  786. { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
  787. { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
  788. { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
  789. { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
  790. { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
  791. { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
  792. { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
  793. { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
  794. { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
  795. { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
  796. { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
  797. { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
  798. { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
  799. { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
  800. { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
  801. { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
  802. { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
  803. { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
  804. { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
  805. { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
  806. { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
  807. { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
  808. };
  809. static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
  810. "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
  811. };
  812. static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
  813. [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
  814. };
  815. static struct tegra_audio_clk_info tegra114_audio_plls[] = {
  816. { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
  817. };
  818. static struct clk **clks;
  819. static unsigned long osc_freq;
  820. static unsigned long pll_ref_freq;
  821. static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
  822. {
  823. struct clk *clk;
  824. /* clk_32k */
  825. clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
  826. clks[TEGRA114_CLK_CLK_32K] = clk;
  827. }
  828. static void __init tegra114_pll_init(void __iomem *clk_base,
  829. void __iomem *pmc)
  830. {
  831. struct clk *clk;
  832. /* PLLC */
  833. clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
  834. pmc, 0, &pll_c_params, NULL);
  835. clks[TEGRA114_CLK_PLL_C] = clk;
  836. /* PLLC_OUT1 */
  837. clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
  838. clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  839. 8, 8, 1, NULL);
  840. clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
  841. clk_base + PLLC_OUT, 1, 0,
  842. CLK_SET_RATE_PARENT, 0, NULL);
  843. clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
  844. /* PLLC2 */
  845. clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
  846. &pll_c2_params, NULL);
  847. clks[TEGRA114_CLK_PLL_C2] = clk;
  848. /* PLLC3 */
  849. clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
  850. &pll_c3_params, NULL);
  851. clks[TEGRA114_CLK_PLL_C3] = clk;
  852. /* PLLM */
  853. clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
  854. CLK_SET_RATE_GATE, &pll_m_params, NULL);
  855. clks[TEGRA114_CLK_PLL_M] = clk;
  856. /* PLLM_OUT1 */
  857. clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
  858. clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  859. 8, 8, 1, NULL);
  860. clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
  861. clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
  862. CLK_SET_RATE_PARENT, 0, NULL);
  863. clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
  864. /* PLLM_UD */
  865. clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
  866. CLK_SET_RATE_PARENT, 1, 1);
  867. /* PLLU */
  868. clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
  869. &pll_u_params, &pll_u_lock);
  870. clks[TEGRA114_CLK_PLL_U] = clk;
  871. /* PLLU_480M */
  872. clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
  873. CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
  874. 22, 0, &pll_u_lock);
  875. clks[TEGRA114_CLK_PLL_U_480M] = clk;
  876. /* PLLU_60M */
  877. clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
  878. CLK_SET_RATE_PARENT, 1, 8);
  879. clks[TEGRA114_CLK_PLL_U_60M] = clk;
  880. /* PLLU_48M */
  881. clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
  882. CLK_SET_RATE_PARENT, 1, 10);
  883. clks[TEGRA114_CLK_PLL_U_48M] = clk;
  884. /* PLLU_12M */
  885. clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
  886. CLK_SET_RATE_PARENT, 1, 40);
  887. clks[TEGRA114_CLK_PLL_U_12M] = clk;
  888. /* PLLD */
  889. clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
  890. &pll_d_params, &pll_d_lock);
  891. clks[TEGRA114_CLK_PLL_D] = clk;
  892. /* PLLD_OUT0 */
  893. clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
  894. CLK_SET_RATE_PARENT, 1, 2);
  895. clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
  896. /* PLLD2 */
  897. clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
  898. &pll_d2_params, &pll_d2_lock);
  899. clks[TEGRA114_CLK_PLL_D2] = clk;
  900. /* PLLD2_OUT0 */
  901. clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
  902. CLK_SET_RATE_PARENT, 1, 2);
  903. clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
  904. /* PLLRE */
  905. clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
  906. 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
  907. clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
  908. clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
  909. clk_base + PLLRE_BASE, 16, 4, 0,
  910. pll_re_div_table, &pll_re_lock);
  911. clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
  912. /* PLLE */
  913. clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
  914. clk_base, 0, &pll_e_params, NULL);
  915. clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
  916. }
  917. #define CLK_SOURCE_VI_SENSOR 0x1a8
  918. static struct tegra_periph_init_data tegra_periph_clk_list[] = {
  919. MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
  920. };
  921. static __init void tegra114_periph_clk_init(void __iomem *clk_base,
  922. void __iomem *pmc_base)
  923. {
  924. struct clk *clk;
  925. struct tegra_periph_init_data *data;
  926. unsigned int i;
  927. /* xusb_ss_div2 */
  928. clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
  929. 1, 2);
  930. clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
  931. /* dsia mux */
  932. clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
  933. ARRAY_SIZE(mux_plld_out0_plld2_out0),
  934. CLK_SET_RATE_NO_REPARENT,
  935. clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
  936. clks[TEGRA114_CLK_DSIA_MUX] = clk;
  937. /* dsib mux */
  938. clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
  939. ARRAY_SIZE(mux_plld_out0_plld2_out0),
  940. CLK_SET_RATE_NO_REPARENT,
  941. clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
  942. clks[TEGRA114_CLK_DSIB_MUX] = clk;
  943. clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
  944. 0, 48, periph_clk_enb_refcnt);
  945. clks[TEGRA114_CLK_DSIA] = clk;
  946. clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
  947. 0, 82, periph_clk_enb_refcnt);
  948. clks[TEGRA114_CLK_DSIB] = clk;
  949. /* emc mux */
  950. clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
  951. ARRAY_SIZE(mux_pllmcp_clkm),
  952. CLK_SET_RATE_NO_REPARENT,
  953. clk_base + CLK_SOURCE_EMC,
  954. 29, 3, 0, &emc_lock);
  955. clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
  956. &emc_lock);
  957. clks[TEGRA114_CLK_MC] = clk;
  958. clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
  959. CLK_SET_RATE_PARENT, 56,
  960. periph_clk_enb_refcnt);
  961. clks[TEGRA114_CLK_MIPI_CAL] = clk;
  962. for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
  963. data = &tegra_periph_clk_list[i];
  964. clk = tegra_clk_register_periph_data(clk_base, data);
  965. clks[data->clk_id] = clk;
  966. }
  967. tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
  968. &pll_p_params);
  969. }
  970. /* Tegra114 CPU clock and reset control functions */
  971. static void tegra114_wait_cpu_in_reset(u32 cpu)
  972. {
  973. unsigned int reg;
  974. do {
  975. reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
  976. cpu_relax();
  977. } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
  978. }
  979. static void tegra114_disable_cpu_clock(u32 cpu)
  980. {
  981. /* flow controller would take care in the power sequence. */
  982. }
  983. #ifdef CONFIG_PM_SLEEP
  984. static void tegra114_cpu_clock_suspend(void)
  985. {
  986. /* switch coresite to clk_m, save off original source */
  987. tegra114_cpu_clk_sctx.clk_csite_src =
  988. readl(clk_base + CLK_SOURCE_CSITE);
  989. writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
  990. tegra114_cpu_clk_sctx.cclkg_burst =
  991. readl(clk_base + CCLKG_BURST_POLICY);
  992. tegra114_cpu_clk_sctx.cclkg_divider =
  993. readl(clk_base + CCLKG_BURST_POLICY + 4);
  994. }
  995. static void tegra114_cpu_clock_resume(void)
  996. {
  997. writel(tegra114_cpu_clk_sctx.clk_csite_src,
  998. clk_base + CLK_SOURCE_CSITE);
  999. writel(tegra114_cpu_clk_sctx.cclkg_burst,
  1000. clk_base + CCLKG_BURST_POLICY);
  1001. writel(tegra114_cpu_clk_sctx.cclkg_divider,
  1002. clk_base + CCLKG_BURST_POLICY + 4);
  1003. }
  1004. #endif
  1005. static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
  1006. .wait_for_reset = tegra114_wait_cpu_in_reset,
  1007. .disable_clock = tegra114_disable_cpu_clock,
  1008. #ifdef CONFIG_PM_SLEEP
  1009. .suspend = tegra114_cpu_clock_suspend,
  1010. .resume = tegra114_cpu_clock_resume,
  1011. #endif
  1012. };
  1013. static const struct of_device_id pmc_match[] __initconst = {
  1014. { .compatible = "nvidia,tegra114-pmc" },
  1015. { },
  1016. };
  1017. /*
  1018. * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
  1019. * breaks
  1020. */
  1021. static struct tegra_clk_init_table init_table[] __initdata = {
  1022. { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
  1023. { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
  1024. { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
  1025. { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
  1026. { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
  1027. { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
  1028. { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
  1029. { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
  1030. { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
  1031. { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
  1032. { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
  1033. { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
  1034. { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
  1035. { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
  1036. { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
  1037. { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
  1038. { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
  1039. { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
  1040. { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
  1041. { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
  1042. { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
  1043. { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
  1044. { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
  1045. { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
  1046. { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
  1047. { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
  1048. { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
  1049. { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1050. { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1051. { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1052. { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1053. { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1054. { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1055. { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
  1056. /* must be the last entry */
  1057. { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
  1058. };
  1059. static void __init tegra114_clock_apply_init_table(void)
  1060. {
  1061. tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
  1062. }
  1063. /**
  1064. * tegra114_car_barrier - wait for pending writes to the CAR to complete
  1065. *
  1066. * Wait for any outstanding writes to the CAR MMIO space from this CPU
  1067. * to complete before continuing execution. No return value.
  1068. */
  1069. static void tegra114_car_barrier(void)
  1070. {
  1071. wmb(); /* probably unnecessary */
  1072. readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
  1073. }
  1074. /**
  1075. * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
  1076. *
  1077. * When the CPU rail voltage is in the high-voltage range, use the
  1078. * built-in hardwired clock propagation delays in the CPU clock
  1079. * shaper. No return value.
  1080. */
  1081. void tegra114_clock_tune_cpu_trimmers_high(void)
  1082. {
  1083. u32 select = 0;
  1084. /* Use hardwired rise->rise & fall->fall clock propagation delays */
  1085. select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
  1086. CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
  1087. CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
  1088. writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
  1089. tegra114_car_barrier();
  1090. }
  1091. EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
  1092. /**
  1093. * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
  1094. *
  1095. * When the CPU rail voltage is in the low-voltage range, use the
  1096. * extended clock propagation delays set by
  1097. * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
  1098. * maintain the input clock duty cycle that the FCPU subsystem
  1099. * expects. No return value.
  1100. */
  1101. void tegra114_clock_tune_cpu_trimmers_low(void)
  1102. {
  1103. u32 select = 0;
  1104. /*
  1105. * Use software-specified rise->rise & fall->fall clock
  1106. * propagation delays (from
  1107. * tegra114_clock_tune_cpu_trimmers_init()
  1108. */
  1109. select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
  1110. CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
  1111. CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
  1112. writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
  1113. tegra114_car_barrier();
  1114. }
  1115. EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
  1116. /**
  1117. * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
  1118. *
  1119. * Program extended clock propagation delays into the FCPU clock
  1120. * shaper and enable them. XXX Define the purpose - peak current
  1121. * reduction? No return value.
  1122. */
  1123. /* XXX Initial voltage rail state assumption issues? */
  1124. void tegra114_clock_tune_cpu_trimmers_init(void)
  1125. {
  1126. u32 dr = 0, r = 0;
  1127. /* Increment the rise->rise clock delay by four steps */
  1128. r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
  1129. CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
  1130. CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
  1131. writel_relaxed(r, clk_base + CPU_FINETRIM_R);
  1132. /*
  1133. * Use the rise->rise clock propagation delay specified in the
  1134. * r field
  1135. */
  1136. dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
  1137. CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
  1138. CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
  1139. writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
  1140. tegra114_clock_tune_cpu_trimmers_low();
  1141. }
  1142. EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
  1143. /**
  1144. * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
  1145. *
  1146. * Assert the reset line of the DFLL's DVCO. No return value.
  1147. */
  1148. void tegra114_clock_assert_dfll_dvco_reset(void)
  1149. {
  1150. u32 v;
  1151. v = readl_relaxed(clk_base + RST_DFLL_DVCO);
  1152. v |= (1 << DVFS_DFLL_RESET_SHIFT);
  1153. writel_relaxed(v, clk_base + RST_DFLL_DVCO);
  1154. tegra114_car_barrier();
  1155. }
  1156. EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
  1157. /**
  1158. * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
  1159. *
  1160. * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
  1161. * operate. No return value.
  1162. */
  1163. void tegra114_clock_deassert_dfll_dvco_reset(void)
  1164. {
  1165. u32 v;
  1166. v = readl_relaxed(clk_base + RST_DFLL_DVCO);
  1167. v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
  1168. writel_relaxed(v, clk_base + RST_DFLL_DVCO);
  1169. tegra114_car_barrier();
  1170. }
  1171. EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
  1172. static void __init tegra114_clock_init(struct device_node *np)
  1173. {
  1174. struct device_node *node;
  1175. clk_base = of_iomap(np, 0);
  1176. if (!clk_base) {
  1177. pr_err("ioremap tegra114 CAR failed\n");
  1178. return;
  1179. }
  1180. node = of_find_matching_node(NULL, pmc_match);
  1181. if (!node) {
  1182. pr_err("Failed to find pmc node\n");
  1183. WARN_ON(1);
  1184. return;
  1185. }
  1186. pmc_base = of_iomap(node, 0);
  1187. if (!pmc_base) {
  1188. pr_err("Can't map pmc registers\n");
  1189. WARN_ON(1);
  1190. return;
  1191. }
  1192. clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
  1193. TEGRA114_CLK_PERIPH_BANKS);
  1194. if (!clks)
  1195. return;
  1196. if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
  1197. ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
  1198. &pll_ref_freq) < 0)
  1199. return;
  1200. tegra114_fixed_clk_init(clk_base);
  1201. tegra114_pll_init(clk_base, pmc_base);
  1202. tegra114_periph_clk_init(clk_base, pmc_base);
  1203. tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
  1204. tegra114_audio_plls,
  1205. ARRAY_SIZE(tegra114_audio_plls), 24000000);
  1206. tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
  1207. &pll_x_params);
  1208. tegra_add_of_provider(np, of_clk_src_onecell_get);
  1209. tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
  1210. tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
  1211. tegra_cpu_car_ops = &tegra114_cpu_car_ops;
  1212. }
  1213. CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);