clk-tegra-fixed.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/delay.h>
  10. #include <linux/export.h>
  11. #include <linux/clk/tegra.h>
  12. #include "clk.h"
  13. #include "clk-id.h"
  14. #define OSC_CTRL 0x50
  15. #define OSC_CTRL_OSC_FREQ_SHIFT 28
  16. #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
  17. #define OSC_CTRL_MASK (0x3f2 | \
  18. (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
  19. static u32 osc_ctrl_ctx;
  20. int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
  21. unsigned long *input_freqs, unsigned int num,
  22. unsigned int clk_m_div, unsigned long *osc_freq,
  23. unsigned long *pll_ref_freq)
  24. {
  25. struct clk *clk, *osc;
  26. struct clk **dt_clk;
  27. u32 val, pll_ref_div;
  28. unsigned osc_idx;
  29. val = readl_relaxed(clk_base + OSC_CTRL);
  30. osc_ctrl_ctx = val & OSC_CTRL_MASK;
  31. osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
  32. if (osc_idx < num)
  33. *osc_freq = input_freqs[osc_idx];
  34. else
  35. *osc_freq = 0;
  36. if (!*osc_freq) {
  37. WARN_ON(1);
  38. return -EINVAL;
  39. }
  40. dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
  41. if (!dt_clk)
  42. return 0;
  43. osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
  44. *dt_clk = osc;
  45. /* osc_div2 */
  46. dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
  47. if (dt_clk) {
  48. clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
  49. 0, 1, 2);
  50. *dt_clk = clk;
  51. }
  52. /* osc_div4 */
  53. dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
  54. if (dt_clk) {
  55. clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
  56. 0, 1, 4);
  57. *dt_clk = clk;
  58. }
  59. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
  60. if (!dt_clk)
  61. return 0;
  62. clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
  63. 0, 1, clk_m_div);
  64. *dt_clk = clk;
  65. /* pll_ref */
  66. val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
  67. pll_ref_div = 1 << val;
  68. dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
  69. if (!dt_clk)
  70. return 0;
  71. clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
  72. 0, 1, pll_ref_div);
  73. *dt_clk = clk;
  74. if (pll_ref_freq)
  75. *pll_ref_freq = *osc_freq / pll_ref_div;
  76. return 0;
  77. }
  78. void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
  79. {
  80. struct clk *clk;
  81. struct clk **dt_clk;
  82. /* clk_32k */
  83. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
  84. if (dt_clk) {
  85. clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
  86. *dt_clk = clk;
  87. }
  88. }
  89. void tegra_clk_osc_resume(void __iomem *clk_base)
  90. {
  91. u32 val;
  92. val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
  93. val |= osc_ctrl_ctx;
  94. writel_relaxed(val, clk_base + OSC_CTRL);
  95. fence_udelay(2, clk_base);
  96. }