clk-tegra-audio.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/delay.h>
  10. #include <linux/export.h>
  11. #include <linux/clk/tegra.h>
  12. #include "clk.h"
  13. #include "clk-id.h"
  14. #define AUDIO_SYNC_CLK_I2S0 0x4a0
  15. #define AUDIO_SYNC_CLK_I2S1 0x4a4
  16. #define AUDIO_SYNC_CLK_I2S2 0x4a8
  17. #define AUDIO_SYNC_CLK_I2S3 0x4ac
  18. #define AUDIO_SYNC_CLK_I2S4 0x4b0
  19. #define AUDIO_SYNC_CLK_SPDIF 0x4b4
  20. #define AUDIO_SYNC_CLK_DMIC1 0x560
  21. #define AUDIO_SYNC_CLK_DMIC2 0x564
  22. #define AUDIO_SYNC_CLK_DMIC3 0x6b8
  23. #define AUDIO_SYNC_DOUBLER 0x49c
  24. #define PLLA_OUT 0xb4
  25. struct tegra_sync_source_initdata {
  26. char *name;
  27. unsigned long rate;
  28. unsigned long max_rate;
  29. int clk_id;
  30. };
  31. #define SYNC(_name) \
  32. {\
  33. .name = #_name,\
  34. .clk_id = tegra_clk_ ## _name,\
  35. }
  36. struct tegra_audio_clk_initdata {
  37. char *gate_name;
  38. char *mux_name;
  39. u32 offset;
  40. int gate_clk_id;
  41. int mux_clk_id;
  42. };
  43. #define AUDIO(_name, _offset) \
  44. {\
  45. .gate_name = #_name,\
  46. .mux_name = #_name"_mux",\
  47. .offset = _offset,\
  48. .gate_clk_id = tegra_clk_ ## _name,\
  49. .mux_clk_id = tegra_clk_ ## _name ## _mux,\
  50. }
  51. struct tegra_audio2x_clk_initdata {
  52. char *parent;
  53. char *gate_name;
  54. char *name_2x;
  55. char *div_name;
  56. int clk_id;
  57. int clk_num;
  58. u8 div_offset;
  59. };
  60. #define AUDIO2X(_name, _num, _offset) \
  61. {\
  62. .parent = #_name,\
  63. .gate_name = #_name"_2x",\
  64. .name_2x = #_name"_doubler",\
  65. .div_name = #_name"_div",\
  66. .clk_id = tegra_clk_ ## _name ## _2x,\
  67. .clk_num = _num,\
  68. .div_offset = _offset,\
  69. }
  70. static DEFINE_SPINLOCK(clk_doubler_lock);
  71. static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
  72. "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
  73. "pll_a_out0", "vimclk_sync",
  74. };
  75. static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
  76. "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
  77. "vimclk_sync",
  78. };
  79. static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
  80. SYNC(spdif_in_sync),
  81. SYNC(i2s0_sync),
  82. SYNC(i2s1_sync),
  83. SYNC(i2s2_sync),
  84. SYNC(i2s3_sync),
  85. SYNC(i2s4_sync),
  86. SYNC(vimclk_sync),
  87. };
  88. static struct tegra_audio_clk_initdata audio_clks[] = {
  89. AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
  90. AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
  91. AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
  92. AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
  93. AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
  94. AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
  95. };
  96. static struct tegra_audio_clk_initdata dmic_clks[] = {
  97. AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
  98. AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
  99. AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
  100. };
  101. static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
  102. AUDIO2X(audio0, 113, 24),
  103. AUDIO2X(audio1, 114, 25),
  104. AUDIO2X(audio2, 115, 26),
  105. AUDIO2X(audio3, 116, 27),
  106. AUDIO2X(audio4, 117, 28),
  107. AUDIO2X(spdif, 118, 29),
  108. };
  109. static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
  110. struct tegra_clk *tegra_clks,
  111. struct tegra_audio_clk_initdata *sync,
  112. int num_sync_clks,
  113. const char * const *mux_names,
  114. int num_mux_inputs)
  115. {
  116. struct clk *clk;
  117. struct clk **dt_clk;
  118. struct tegra_audio_clk_initdata *data;
  119. int i;
  120. for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
  121. dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
  122. if (!dt_clk)
  123. continue;
  124. clk = clk_register_mux(NULL, data->mux_name, mux_names,
  125. num_mux_inputs,
  126. CLK_SET_RATE_NO_REPARENT,
  127. clk_base + data->offset, 0, 3, 0,
  128. NULL);
  129. *dt_clk = clk;
  130. dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
  131. if (!dt_clk)
  132. continue;
  133. clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
  134. 0, clk_base + data->offset, 4,
  135. CLK_GATE_SET_TO_DISABLE, NULL);
  136. *dt_clk = clk;
  137. }
  138. }
  139. void __init tegra_audio_clk_init(void __iomem *clk_base,
  140. void __iomem *pmc_base, struct tegra_clk *tegra_clks,
  141. struct tegra_audio_clk_info *audio_info,
  142. unsigned int num_plls, unsigned long sync_max_rate)
  143. {
  144. struct clk *clk;
  145. struct clk **dt_clk;
  146. int i;
  147. if (!audio_info || num_plls < 1) {
  148. pr_err("No audio data passed to tegra_audio_clk_init\n");
  149. WARN_ON(1);
  150. return;
  151. }
  152. for (i = 0; i < num_plls; i++) {
  153. struct tegra_audio_clk_info *info = &audio_info[i];
  154. dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
  155. if (dt_clk) {
  156. clk = tegra_clk_register_pll(info->name, info->parent,
  157. clk_base, pmc_base, 0, info->pll_params,
  158. NULL);
  159. *dt_clk = clk;
  160. }
  161. }
  162. /* PLLA_OUT0 */
  163. dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
  164. if (dt_clk) {
  165. clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
  166. clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  167. 8, 8, 1, NULL);
  168. clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
  169. clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
  170. CLK_SET_RATE_PARENT, 0, NULL);
  171. *dt_clk = clk;
  172. }
  173. for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
  174. struct tegra_sync_source_initdata *data;
  175. data = &sync_source_clks[i];
  176. dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
  177. if (!dt_clk)
  178. continue;
  179. clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
  180. *dt_clk = clk;
  181. }
  182. tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
  183. ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
  184. ARRAY_SIZE(mux_audio_sync_clk));
  185. /* make sure the DMIC sync clocks have a valid parent */
  186. for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
  187. writel_relaxed(1, clk_base + dmic_clks[i].offset);
  188. tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
  189. ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
  190. ARRAY_SIZE(mux_dmic_sync_clk));
  191. for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
  192. struct tegra_audio2x_clk_initdata *data;
  193. data = &audio2x_clks[i];
  194. dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
  195. if (!dt_clk)
  196. continue;
  197. clk = clk_register_fixed_factor(NULL, data->name_2x,
  198. data->parent, CLK_SET_RATE_PARENT, 2, 1);
  199. clk = tegra_clk_register_divider(data->div_name,
  200. data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
  201. 0, 0, data->div_offset, 1, 0,
  202. &clk_doubler_lock);
  203. clk = tegra_clk_register_periph_gate(data->gate_name,
  204. data->div_name, TEGRA_PERIPH_NO_RESET,
  205. clk_base, CLK_SET_RATE_PARENT, data->clk_num,
  206. periph_clk_enb_refcnt);
  207. *dt_clk = clk;
  208. }
  209. }