clk-sdmmc-mux.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * based on clk-mux.c
  6. *
  7. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  8. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  9. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  10. *
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/types.h>
  16. #include "clk.h"
  17. #define DIV_MASK GENMASK(7, 0)
  18. #define MUX_SHIFT 29
  19. #define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
  20. #define SDMMC_MUL 2
  21. #define get_max_div(d) DIV_MASK
  22. #define get_div_field(val) ((val) & DIV_MASK)
  23. #define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
  24. static const char * const mux_sdmmc_parents[] = {
  25. "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
  26. };
  27. static const u8 mux_lj_idx[] = {
  28. [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
  29. };
  30. static const u8 mux_non_lj_idx[] = {
  31. [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
  32. };
  33. static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
  34. {
  35. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  36. int num_parents, i;
  37. u32 src, val;
  38. const u8 *mux_idx;
  39. num_parents = clk_hw_get_num_parents(hw);
  40. val = readl_relaxed(sdmmc_mux->reg);
  41. src = get_mux_field(val);
  42. if (get_div_field(val))
  43. mux_idx = mux_non_lj_idx;
  44. else
  45. mux_idx = mux_lj_idx;
  46. for (i = 0; i < num_parents; i++) {
  47. if (mux_idx[i] == src)
  48. return i;
  49. }
  50. WARN(1, "Unknown parent selector %d\n", src);
  51. return 0;
  52. }
  53. static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
  54. {
  55. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  56. u32 val;
  57. val = readl_relaxed(sdmmc_mux->reg);
  58. if (get_div_field(val))
  59. index = mux_non_lj_idx[index];
  60. else
  61. index = mux_lj_idx[index];
  62. val &= ~MUX_MASK;
  63. val |= index << MUX_SHIFT;
  64. writel(val, sdmmc_mux->reg);
  65. return 0;
  66. }
  67. static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
  68. unsigned long parent_rate)
  69. {
  70. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  71. u32 val;
  72. int div;
  73. u64 rate = parent_rate;
  74. val = readl_relaxed(sdmmc_mux->reg);
  75. div = get_div_field(val);
  76. div += SDMMC_MUL;
  77. rate *= SDMMC_MUL;
  78. rate += div - 1;
  79. do_div(rate, div);
  80. return rate;
  81. }
  82. static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
  83. struct clk_rate_request *req)
  84. {
  85. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  86. int div;
  87. unsigned long output_rate = req->best_parent_rate;
  88. req->rate = max(req->rate, req->min_rate);
  89. req->rate = min(req->rate, req->max_rate);
  90. if (!req->rate)
  91. return output_rate;
  92. div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
  93. if (div < 0)
  94. div = 0;
  95. if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
  96. req->rate = DIV_ROUND_UP(output_rate * SDMMC_MUL,
  97. div + SDMMC_MUL);
  98. else
  99. req->rate = output_rate * SDMMC_MUL / (div + SDMMC_MUL);
  100. return 0;
  101. }
  102. static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
  103. unsigned long parent_rate)
  104. {
  105. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  106. int div;
  107. unsigned long flags = 0;
  108. u32 val;
  109. u8 src;
  110. div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
  111. if (div < 0)
  112. return div;
  113. if (sdmmc_mux->lock)
  114. spin_lock_irqsave(sdmmc_mux->lock, flags);
  115. src = clk_sdmmc_mux_get_parent(hw);
  116. if (div)
  117. src = mux_non_lj_idx[src];
  118. else
  119. src = mux_lj_idx[src];
  120. val = src << MUX_SHIFT;
  121. val |= div;
  122. writel(val, sdmmc_mux->reg);
  123. fence_udelay(2, sdmmc_mux->reg);
  124. if (sdmmc_mux->lock)
  125. spin_unlock_irqrestore(sdmmc_mux->lock, flags);
  126. return 0;
  127. }
  128. static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
  129. {
  130. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  131. const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
  132. struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
  133. __clk_hw_set_clk(gate_hw, hw);
  134. return gate_ops->is_enabled(gate_hw);
  135. }
  136. static int clk_sdmmc_mux_enable(struct clk_hw *hw)
  137. {
  138. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  139. const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
  140. struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
  141. __clk_hw_set_clk(gate_hw, hw);
  142. return gate_ops->enable(gate_hw);
  143. }
  144. static void clk_sdmmc_mux_disable(struct clk_hw *hw)
  145. {
  146. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  147. const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
  148. struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
  149. gate_ops->disable(gate_hw);
  150. }
  151. static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw)
  152. {
  153. struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
  154. const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
  155. struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
  156. gate_ops->disable_unused(gate_hw);
  157. }
  158. static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
  159. {
  160. struct clk_hw *parent = clk_hw_get_parent(hw);
  161. unsigned long parent_rate = clk_hw_get_rate(parent);
  162. unsigned long rate = clk_hw_get_rate(hw);
  163. int parent_id;
  164. parent_id = clk_hw_get_parent_index(hw);
  165. if (WARN_ON(parent_id < 0))
  166. return;
  167. clk_sdmmc_mux_set_parent(hw, parent_id);
  168. clk_sdmmc_mux_set_rate(hw, rate, parent_rate);
  169. }
  170. static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
  171. .get_parent = clk_sdmmc_mux_get_parent,
  172. .set_parent = clk_sdmmc_mux_set_parent,
  173. .determine_rate = clk_sdmmc_mux_determine_rate,
  174. .recalc_rate = clk_sdmmc_mux_recalc_rate,
  175. .set_rate = clk_sdmmc_mux_set_rate,
  176. .is_enabled = clk_sdmmc_mux_is_enabled,
  177. .enable = clk_sdmmc_mux_enable,
  178. .disable = clk_sdmmc_mux_disable,
  179. .disable_unused = clk_sdmmc_mux_disable_unused,
  180. .restore_context = clk_sdmmc_mux_restore_context,
  181. };
  182. struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
  183. void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
  184. unsigned long flags, void *lock)
  185. {
  186. struct clk *clk;
  187. struct clk_init_data init;
  188. const struct tegra_clk_periph_regs *bank;
  189. struct tegra_sdmmc_mux *sdmmc_mux;
  190. init.ops = &tegra_clk_sdmmc_mux_ops;
  191. init.name = name;
  192. init.flags = flags;
  193. init.parent_names = mux_sdmmc_parents;
  194. init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
  195. bank = get_reg_bank(clk_num);
  196. if (!bank)
  197. return ERR_PTR(-EINVAL);
  198. sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
  199. if (!sdmmc_mux)
  200. return ERR_PTR(-ENOMEM);
  201. /* Data in .init is copied by clk_register(), so stack variable OK */
  202. sdmmc_mux->hw.init = &init;
  203. sdmmc_mux->reg = clk_base + offset;
  204. sdmmc_mux->lock = lock;
  205. sdmmc_mux->gate.clk_base = clk_base;
  206. sdmmc_mux->gate.regs = bank;
  207. sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
  208. sdmmc_mux->gate.clk_num = clk_num;
  209. sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
  210. sdmmc_mux->div_flags = div_flags;
  211. sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
  212. clk = clk_register(NULL, &sdmmc_mux->hw);
  213. if (IS_ERR(clk)) {
  214. kfree(sdmmc_mux);
  215. return clk;
  216. }
  217. sdmmc_mux->gate.hw.clk = clk;
  218. return clk;
  219. }