clk-pll.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/io.h>
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include "clk.h"
  12. #define PLL_BASE_BYPASS BIT(31)
  13. #define PLL_BASE_ENABLE BIT(30)
  14. #define PLL_BASE_REF_ENABLE BIT(29)
  15. #define PLL_BASE_OVERRIDE BIT(28)
  16. #define PLL_BASE_DIVP_SHIFT 20
  17. #define PLL_BASE_DIVP_WIDTH 3
  18. #define PLL_BASE_DIVN_SHIFT 8
  19. #define PLL_BASE_DIVN_WIDTH 10
  20. #define PLL_BASE_DIVM_SHIFT 0
  21. #define PLL_BASE_DIVM_WIDTH 5
  22. #define PLLU_POST_DIVP_MASK 0x1
  23. #define PLL_MISC_DCCON_SHIFT 20
  24. #define PLL_MISC_CPCON_SHIFT 8
  25. #define PLL_MISC_CPCON_WIDTH 4
  26. #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  27. #define PLL_MISC_LFCON_SHIFT 4
  28. #define PLL_MISC_LFCON_WIDTH 4
  29. #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  30. #define PLL_MISC_VCOCON_SHIFT 0
  31. #define PLL_MISC_VCOCON_WIDTH 4
  32. #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  33. #define OUT_OF_TABLE_CPCON 8
  34. #define PMC_PLLP_WB0_OVERRIDE 0xf8
  35. #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  36. #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  37. #define PLL_POST_LOCK_DELAY 50
  38. #define PLLDU_LFCON_SET_DIVN 600
  39. #define PLLE_BASE_DIVCML_SHIFT 24
  40. #define PLLE_BASE_DIVCML_MASK 0xf
  41. #define PLLE_BASE_DIVP_SHIFT 16
  42. #define PLLE_BASE_DIVP_WIDTH 6
  43. #define PLLE_BASE_DIVN_SHIFT 8
  44. #define PLLE_BASE_DIVN_WIDTH 8
  45. #define PLLE_BASE_DIVM_SHIFT 0
  46. #define PLLE_BASE_DIVM_WIDTH 8
  47. #define PLLE_BASE_ENABLE BIT(31)
  48. #define PLLE_MISC_SETUP_BASE_SHIFT 16
  49. #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  50. #define PLLE_MISC_LOCK_ENABLE BIT(9)
  51. #define PLLE_MISC_READY BIT(15)
  52. #define PLLE_MISC_SETUP_EX_SHIFT 2
  53. #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  54. #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
  55. PLLE_MISC_SETUP_EX_MASK)
  56. #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  57. #define PLLE_SS_CTRL 0x68
  58. #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  59. #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  60. #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  61. #define PLLE_SS_CNTL_CENTER BIT(14)
  62. #define PLLE_SS_CNTL_INVERT BIT(15)
  63. #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  64. PLLE_SS_CNTL_SSC_BYP)
  65. #define PLLE_SS_MAX_MASK 0x1ff
  66. #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  67. #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  68. #define PLLE_SS_INC_MASK (0xff << 16)
  69. #define PLLE_SS_INC_VAL (0x1 << 16)
  70. #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  71. #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  72. #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  73. #define PLLE_SS_COEFFICIENTS_MASK \
  74. (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  75. #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  76. (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
  77. PLLE_SS_INCINTRV_VAL_TEGRA114)
  78. #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
  79. (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
  80. PLLE_SS_INCINTRV_VAL_TEGRA210)
  81. #define PLLE_AUX_PLLP_SEL BIT(2)
  82. #define PLLE_AUX_USE_LOCKDET BIT(3)
  83. #define PLLE_AUX_ENABLE_SWCTL BIT(4)
  84. #define PLLE_AUX_SS_SWCTL BIT(6)
  85. #define PLLE_AUX_SEQ_ENABLE BIT(24)
  86. #define PLLE_AUX_SEQ_START_STATE BIT(25)
  87. #define PLLE_AUX_PLLRE_SEL BIT(28)
  88. #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
  89. #define XUSBIO_PLL_CFG0 0x51c
  90. #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
  91. #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
  92. #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
  93. #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
  94. #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
  95. #define SATA_PLL_CFG0 0x490
  96. #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
  97. #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
  98. #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
  99. #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
  100. #define PLLE_MISC_PLLE_PTS BIT(8)
  101. #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
  102. #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
  103. #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
  104. #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
  105. #define PLLE_MISC_VREG_CTRL_SHIFT 2
  106. #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
  107. #define PLLCX_MISC_STROBE BIT(31)
  108. #define PLLCX_MISC_RESET BIT(30)
  109. #define PLLCX_MISC_SDM_DIV_SHIFT 28
  110. #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
  111. #define PLLCX_MISC_FILT_DIV_SHIFT 26
  112. #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
  113. #define PLLCX_MISC_ALPHA_SHIFT 18
  114. #define PLLCX_MISC_DIV_LOW_RANGE \
  115. ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
  116. (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
  117. #define PLLCX_MISC_DIV_HIGH_RANGE \
  118. ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
  119. (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
  120. #define PLLCX_MISC_COEF_LOW_RANGE \
  121. ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
  122. #define PLLCX_MISC_KA_SHIFT 2
  123. #define PLLCX_MISC_KB_SHIFT 9
  124. #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
  125. (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
  126. PLLCX_MISC_DIV_LOW_RANGE | \
  127. PLLCX_MISC_RESET)
  128. #define PLLCX_MISC1_DEFAULT 0x000d2308
  129. #define PLLCX_MISC2_DEFAULT 0x30211200
  130. #define PLLCX_MISC3_DEFAULT 0x200
  131. #define PMC_SATA_PWRGT 0x1ac
  132. #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
  133. #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
  134. #define PLLSS_MISC_KCP 0
  135. #define PLLSS_MISC_KVCO 0
  136. #define PLLSS_MISC_SETUP 0
  137. #define PLLSS_EN_SDM 0
  138. #define PLLSS_EN_SSC 0
  139. #define PLLSS_EN_DITHER2 0
  140. #define PLLSS_EN_DITHER 1
  141. #define PLLSS_SDM_RESET 0
  142. #define PLLSS_CLAMP 0
  143. #define PLLSS_SDM_SSC_MAX 0
  144. #define PLLSS_SDM_SSC_MIN 0
  145. #define PLLSS_SDM_SSC_STEP 0
  146. #define PLLSS_SDM_DIN 0
  147. #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
  148. (PLLSS_MISC_KVCO << 24) | \
  149. PLLSS_MISC_SETUP)
  150. #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
  151. (PLLSS_EN_SSC << 30) | \
  152. (PLLSS_EN_DITHER2 << 29) | \
  153. (PLLSS_EN_DITHER << 28) | \
  154. (PLLSS_SDM_RESET) << 27 | \
  155. (PLLSS_CLAMP << 22))
  156. #define PLLSS_CTRL1_DEFAULT \
  157. ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
  158. #define PLLSS_CTRL2_DEFAULT \
  159. ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
  160. #define PLLSS_LOCK_OVERRIDE BIT(24)
  161. #define PLLSS_REF_SRC_SEL_SHIFT 25
  162. #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
  163. #define UTMIP_PLL_CFG1 0x484
  164. #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
  165. #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
  166. #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
  167. #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
  168. #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
  169. #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
  170. #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
  171. #define UTMIP_PLL_CFG2 0x488
  172. #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
  173. #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
  174. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
  175. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
  176. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
  177. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
  178. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
  179. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
  180. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
  181. #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
  182. #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
  183. #define UTMIPLL_HW_PWRDN_CFG0 0x52c
  184. #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
  185. #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
  186. #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
  187. #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
  188. #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
  189. #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
  190. #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
  191. #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
  192. #define PLLU_HW_PWRDN_CFG0 0x530
  193. #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
  194. #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
  195. #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
  196. #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
  197. #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
  198. #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
  199. #define XUSB_PLL_CFG0 0x534
  200. #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
  201. #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
  202. #define PLLU_BASE_CLKENABLE_USB BIT(21)
  203. #define PLLU_BASE_OVERRIDE BIT(24)
  204. #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
  205. #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
  206. #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
  207. #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
  208. #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
  209. #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
  210. #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
  211. #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
  212. #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
  213. #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
  214. #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
  215. #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
  216. #define mask(w) ((1 << (w)) - 1)
  217. #define divm_mask(p) mask(p->params->div_nmp->divm_width)
  218. #define divn_mask(p) mask(p->params->div_nmp->divn_width)
  219. #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
  220. mask(p->params->div_nmp->divp_width))
  221. #define sdm_din_mask(p) p->params->sdm_din_mask
  222. #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
  223. #define divm_shift(p) (p)->params->div_nmp->divm_shift
  224. #define divn_shift(p) (p)->params->div_nmp->divn_shift
  225. #define divp_shift(p) (p)->params->div_nmp->divp_shift
  226. #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
  227. #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
  228. #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
  229. #define divm_max(p) (divm_mask(p))
  230. #define divn_max(p) (divn_mask(p))
  231. #define divp_max(p) (1 << (divp_mask(p)))
  232. #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
  233. #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
  234. static struct div_nmp default_nmp = {
  235. .divn_shift = PLL_BASE_DIVN_SHIFT,
  236. .divn_width = PLL_BASE_DIVN_WIDTH,
  237. .divm_shift = PLL_BASE_DIVM_SHIFT,
  238. .divm_width = PLL_BASE_DIVM_WIDTH,
  239. .divp_shift = PLL_BASE_DIVP_SHIFT,
  240. .divp_width = PLL_BASE_DIVP_WIDTH,
  241. };
  242. static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
  243. {
  244. u32 val;
  245. if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
  246. return;
  247. if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
  248. return;
  249. val = pll_readl_misc(pll);
  250. val |= BIT(pll->params->lock_enable_bit_idx);
  251. pll_writel_misc(val, pll);
  252. }
  253. static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
  254. {
  255. int i;
  256. u32 val, lock_mask;
  257. void __iomem *lock_addr;
  258. if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
  259. udelay(pll->params->lock_delay);
  260. return 0;
  261. }
  262. lock_addr = pll->clk_base;
  263. if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
  264. lock_addr += pll->params->misc_reg;
  265. else
  266. lock_addr += pll->params->base_reg;
  267. lock_mask = pll->params->lock_mask;
  268. for (i = 0; i < pll->params->lock_delay; i++) {
  269. val = readl_relaxed(lock_addr);
  270. if ((val & lock_mask) == lock_mask) {
  271. udelay(PLL_POST_LOCK_DELAY);
  272. return 0;
  273. }
  274. udelay(2); /* timeout = 2 * lock time */
  275. }
  276. pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
  277. clk_hw_get_name(&pll->hw));
  278. return -1;
  279. }
  280. int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
  281. {
  282. return clk_pll_wait_for_lock(pll);
  283. }
  284. static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
  285. {
  286. u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
  287. return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
  288. !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
  289. }
  290. static int clk_pll_is_enabled(struct clk_hw *hw)
  291. {
  292. struct tegra_clk_pll *pll = to_clk_pll(hw);
  293. u32 val;
  294. /*
  295. * Power Management Controller (PMC) can override the PLLM clock
  296. * settings, including the enable-state. The PLLM is enabled when
  297. * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
  298. */
  299. if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
  300. return 0;
  301. val = pll_readl_base(pll);
  302. return val & PLL_BASE_ENABLE ? 1 : 0;
  303. }
  304. static void _clk_pll_enable(struct clk_hw *hw)
  305. {
  306. struct tegra_clk_pll *pll = to_clk_pll(hw);
  307. u32 val;
  308. if (pll->params->iddq_reg) {
  309. val = pll_readl(pll->params->iddq_reg, pll);
  310. val &= ~BIT(pll->params->iddq_bit_idx);
  311. pll_writel(val, pll->params->iddq_reg, pll);
  312. udelay(5);
  313. }
  314. if (pll->params->reset_reg) {
  315. val = pll_readl(pll->params->reset_reg, pll);
  316. val &= ~BIT(pll->params->reset_bit_idx);
  317. pll_writel(val, pll->params->reset_reg, pll);
  318. }
  319. clk_pll_enable_lock(pll);
  320. val = pll_readl_base(pll);
  321. if (pll->params->flags & TEGRA_PLL_BYPASS)
  322. val &= ~PLL_BASE_BYPASS;
  323. val |= PLL_BASE_ENABLE;
  324. pll_writel_base(val, pll);
  325. if (pll->params->flags & TEGRA_PLLM) {
  326. val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
  327. val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
  328. writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
  329. }
  330. }
  331. static void _clk_pll_disable(struct clk_hw *hw)
  332. {
  333. struct tegra_clk_pll *pll = to_clk_pll(hw);
  334. u32 val;
  335. val = pll_readl_base(pll);
  336. if (pll->params->flags & TEGRA_PLL_BYPASS)
  337. val &= ~PLL_BASE_BYPASS;
  338. val &= ~PLL_BASE_ENABLE;
  339. pll_writel_base(val, pll);
  340. if (pll->params->flags & TEGRA_PLLM) {
  341. val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
  342. val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
  343. writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
  344. }
  345. if (pll->params->reset_reg) {
  346. val = pll_readl(pll->params->reset_reg, pll);
  347. val |= BIT(pll->params->reset_bit_idx);
  348. pll_writel(val, pll->params->reset_reg, pll);
  349. }
  350. if (pll->params->iddq_reg) {
  351. val = pll_readl(pll->params->iddq_reg, pll);
  352. val |= BIT(pll->params->iddq_bit_idx);
  353. pll_writel(val, pll->params->iddq_reg, pll);
  354. udelay(2);
  355. }
  356. }
  357. static void pll_clk_start_ss(struct tegra_clk_pll *pll)
  358. {
  359. if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
  360. u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
  361. val |= pll->params->ssc_ctrl_en_mask;
  362. pll_writel(val, pll->params->ssc_ctrl_reg, pll);
  363. }
  364. }
  365. static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
  366. {
  367. if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
  368. u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
  369. val &= ~pll->params->ssc_ctrl_en_mask;
  370. pll_writel(val, pll->params->ssc_ctrl_reg, pll);
  371. }
  372. }
  373. static int clk_pll_enable(struct clk_hw *hw)
  374. {
  375. struct tegra_clk_pll *pll = to_clk_pll(hw);
  376. unsigned long flags = 0;
  377. int ret;
  378. if (clk_pll_is_enabled(hw))
  379. return 0;
  380. if (pll->lock)
  381. spin_lock_irqsave(pll->lock, flags);
  382. _clk_pll_enable(hw);
  383. ret = clk_pll_wait_for_lock(pll);
  384. pll_clk_start_ss(pll);
  385. if (pll->lock)
  386. spin_unlock_irqrestore(pll->lock, flags);
  387. return ret;
  388. }
  389. static void clk_pll_disable(struct clk_hw *hw)
  390. {
  391. struct tegra_clk_pll *pll = to_clk_pll(hw);
  392. unsigned long flags = 0;
  393. if (pll->lock)
  394. spin_lock_irqsave(pll->lock, flags);
  395. pll_clk_stop_ss(pll);
  396. _clk_pll_disable(hw);
  397. if (pll->lock)
  398. spin_unlock_irqrestore(pll->lock, flags);
  399. }
  400. static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
  401. {
  402. struct tegra_clk_pll *pll = to_clk_pll(hw);
  403. const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
  404. if (p_tohw) {
  405. while (p_tohw->pdiv) {
  406. if (p_div <= p_tohw->pdiv)
  407. return p_tohw->hw_val;
  408. p_tohw++;
  409. }
  410. return -EINVAL;
  411. }
  412. return -EINVAL;
  413. }
  414. int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
  415. {
  416. return _p_div_to_hw(&pll->hw, p_div);
  417. }
  418. static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
  419. {
  420. struct tegra_clk_pll *pll = to_clk_pll(hw);
  421. const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
  422. if (p_tohw) {
  423. while (p_tohw->pdiv) {
  424. if (p_div_hw == p_tohw->hw_val)
  425. return p_tohw->pdiv;
  426. p_tohw++;
  427. }
  428. return -EINVAL;
  429. }
  430. return 1 << p_div_hw;
  431. }
  432. static int _get_table_rate(struct clk_hw *hw,
  433. struct tegra_clk_pll_freq_table *cfg,
  434. unsigned long rate, unsigned long parent_rate)
  435. {
  436. struct tegra_clk_pll *pll = to_clk_pll(hw);
  437. struct tegra_clk_pll_freq_table *sel;
  438. int p;
  439. for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
  440. if (sel->input_rate == parent_rate &&
  441. sel->output_rate == rate)
  442. break;
  443. if (sel->input_rate == 0)
  444. return -EINVAL;
  445. if (pll->params->pdiv_tohw) {
  446. p = _p_div_to_hw(hw, sel->p);
  447. if (p < 0)
  448. return p;
  449. } else {
  450. p = ilog2(sel->p);
  451. }
  452. cfg->input_rate = sel->input_rate;
  453. cfg->output_rate = sel->output_rate;
  454. cfg->m = sel->m;
  455. cfg->n = sel->n;
  456. cfg->p = p;
  457. cfg->cpcon = sel->cpcon;
  458. cfg->sdm_data = sel->sdm_data;
  459. return 0;
  460. }
  461. static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
  462. unsigned long rate, unsigned long parent_rate)
  463. {
  464. struct tegra_clk_pll *pll = to_clk_pll(hw);
  465. unsigned long cfreq;
  466. u32 p_div = 0;
  467. int ret;
  468. switch (parent_rate) {
  469. case 12000000:
  470. case 26000000:
  471. cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
  472. break;
  473. case 13000000:
  474. cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
  475. break;
  476. case 16800000:
  477. case 19200000:
  478. cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
  479. break;
  480. case 9600000:
  481. case 28800000:
  482. /*
  483. * PLL_P_OUT1 rate is not listed in PLLA table
  484. */
  485. cfreq = parent_rate / (parent_rate / 1000000);
  486. break;
  487. default:
  488. pr_err("%s Unexpected reference rate %lu\n",
  489. __func__, parent_rate);
  490. BUG();
  491. }
  492. /* Raise VCO to guarantee 0.5% accuracy */
  493. for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
  494. cfg->output_rate <<= 1)
  495. p_div++;
  496. cfg->m = parent_rate / cfreq;
  497. cfg->n = cfg->output_rate / cfreq;
  498. cfg->cpcon = OUT_OF_TABLE_CPCON;
  499. if (cfg->m == 0 || cfg->m > divm_max(pll) ||
  500. cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
  501. cfg->output_rate > pll->params->vco_max) {
  502. return -EINVAL;
  503. }
  504. cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
  505. cfg->output_rate >>= p_div;
  506. if (pll->params->pdiv_tohw) {
  507. ret = _p_div_to_hw(hw, 1 << p_div);
  508. if (ret < 0)
  509. return ret;
  510. else
  511. cfg->p = ret;
  512. } else
  513. cfg->p = p_div;
  514. return 0;
  515. }
  516. /*
  517. * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
  518. * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
  519. * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
  520. * to indicate that SDM is disabled.
  521. *
  522. * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
  523. */
  524. static void clk_pll_set_sdm_data(struct clk_hw *hw,
  525. struct tegra_clk_pll_freq_table *cfg)
  526. {
  527. struct tegra_clk_pll *pll = to_clk_pll(hw);
  528. u32 val;
  529. bool enabled;
  530. if (!pll->params->sdm_din_reg)
  531. return;
  532. if (cfg->sdm_data) {
  533. val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
  534. val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
  535. pll_writel_sdm_din(val, pll);
  536. }
  537. val = pll_readl_sdm_ctrl(pll);
  538. enabled = (val & sdm_en_mask(pll));
  539. if (cfg->sdm_data == 0 && enabled)
  540. val &= ~pll->params->sdm_ctrl_en_mask;
  541. if (cfg->sdm_data != 0 && !enabled)
  542. val |= pll->params->sdm_ctrl_en_mask;
  543. pll_writel_sdm_ctrl(val, pll);
  544. }
  545. static void _update_pll_mnp(struct tegra_clk_pll *pll,
  546. struct tegra_clk_pll_freq_table *cfg)
  547. {
  548. u32 val;
  549. struct tegra_clk_pll_params *params = pll->params;
  550. struct div_nmp *div_nmp = params->div_nmp;
  551. if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
  552. (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
  553. PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
  554. val = pll_override_readl(params->pmc_divp_reg, pll);
  555. val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
  556. val |= cfg->p << div_nmp->override_divp_shift;
  557. pll_override_writel(val, params->pmc_divp_reg, pll);
  558. val = pll_override_readl(params->pmc_divnm_reg, pll);
  559. val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
  560. (divn_mask(pll) << div_nmp->override_divn_shift));
  561. val |= (cfg->m << div_nmp->override_divm_shift) |
  562. (cfg->n << div_nmp->override_divn_shift);
  563. pll_override_writel(val, params->pmc_divnm_reg, pll);
  564. } else {
  565. val = pll_readl_base(pll);
  566. val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
  567. divp_mask_shifted(pll));
  568. val |= (cfg->m << divm_shift(pll)) |
  569. (cfg->n << divn_shift(pll)) |
  570. (cfg->p << divp_shift(pll));
  571. pll_writel_base(val, pll);
  572. clk_pll_set_sdm_data(&pll->hw, cfg);
  573. }
  574. }
  575. static void _get_pll_mnp(struct tegra_clk_pll *pll,
  576. struct tegra_clk_pll_freq_table *cfg)
  577. {
  578. u32 val;
  579. struct tegra_clk_pll_params *params = pll->params;
  580. struct div_nmp *div_nmp = params->div_nmp;
  581. *cfg = (struct tegra_clk_pll_freq_table) { };
  582. if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
  583. (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
  584. PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
  585. val = pll_override_readl(params->pmc_divp_reg, pll);
  586. cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
  587. val = pll_override_readl(params->pmc_divnm_reg, pll);
  588. cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
  589. cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
  590. } else {
  591. val = pll_readl_base(pll);
  592. cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
  593. cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
  594. cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
  595. if (pll->params->sdm_din_reg) {
  596. if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
  597. val = pll_readl_sdm_din(pll);
  598. val &= sdm_din_mask(pll);
  599. cfg->sdm_data = sdin_din_to_data(val);
  600. }
  601. }
  602. }
  603. }
  604. static void _update_pll_cpcon(struct tegra_clk_pll *pll,
  605. struct tegra_clk_pll_freq_table *cfg,
  606. unsigned long rate)
  607. {
  608. u32 val;
  609. val = pll_readl_misc(pll);
  610. val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
  611. val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
  612. if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
  613. val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
  614. if (cfg->n >= PLLDU_LFCON_SET_DIVN)
  615. val |= 1 << PLL_MISC_LFCON_SHIFT;
  616. } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
  617. val &= ~(1 << PLL_MISC_DCCON_SHIFT);
  618. if (rate >= (pll->params->vco_max >> 1))
  619. val |= 1 << PLL_MISC_DCCON_SHIFT;
  620. }
  621. pll_writel_misc(val, pll);
  622. }
  623. static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
  624. unsigned long rate)
  625. {
  626. struct tegra_clk_pll *pll = to_clk_pll(hw);
  627. struct tegra_clk_pll_freq_table old_cfg;
  628. int state, ret = 0;
  629. state = clk_pll_is_enabled(hw);
  630. if (state && pll->params->pre_rate_change) {
  631. ret = pll->params->pre_rate_change();
  632. if (WARN_ON(ret))
  633. return ret;
  634. }
  635. _get_pll_mnp(pll, &old_cfg);
  636. if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
  637. (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
  638. ret = pll->params->dyn_ramp(pll, cfg);
  639. if (!ret)
  640. goto done;
  641. }
  642. if (state) {
  643. pll_clk_stop_ss(pll);
  644. _clk_pll_disable(hw);
  645. }
  646. if (!pll->params->defaults_set && pll->params->set_defaults)
  647. pll->params->set_defaults(pll);
  648. _update_pll_mnp(pll, cfg);
  649. if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
  650. _update_pll_cpcon(pll, cfg, rate);
  651. if (state) {
  652. _clk_pll_enable(hw);
  653. ret = clk_pll_wait_for_lock(pll);
  654. pll_clk_start_ss(pll);
  655. }
  656. done:
  657. if (state && pll->params->post_rate_change)
  658. pll->params->post_rate_change();
  659. return ret;
  660. }
  661. static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  662. unsigned long parent_rate)
  663. {
  664. struct tegra_clk_pll *pll = to_clk_pll(hw);
  665. struct tegra_clk_pll_freq_table cfg, old_cfg;
  666. unsigned long flags = 0;
  667. int ret = 0;
  668. if (pll->params->flags & TEGRA_PLL_FIXED) {
  669. if (rate != pll->params->fixed_rate) {
  670. pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
  671. __func__, clk_hw_get_name(hw),
  672. pll->params->fixed_rate, rate);
  673. return -EINVAL;
  674. }
  675. return 0;
  676. }
  677. if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
  678. pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
  679. pr_err("%s: Failed to set %s rate %lu\n", __func__,
  680. clk_hw_get_name(hw), rate);
  681. WARN_ON(1);
  682. return -EINVAL;
  683. }
  684. if (pll->lock)
  685. spin_lock_irqsave(pll->lock, flags);
  686. _get_pll_mnp(pll, &old_cfg);
  687. if (pll->params->flags & TEGRA_PLL_VCO_OUT)
  688. cfg.p = old_cfg.p;
  689. if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
  690. old_cfg.sdm_data != cfg.sdm_data)
  691. ret = _program_pll(hw, &cfg, rate);
  692. if (pll->lock)
  693. spin_unlock_irqrestore(pll->lock, flags);
  694. return ret;
  695. }
  696. static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  697. unsigned long *prate)
  698. {
  699. struct tegra_clk_pll *pll = to_clk_pll(hw);
  700. struct tegra_clk_pll_freq_table cfg;
  701. if (pll->params->flags & TEGRA_PLL_FIXED) {
  702. /* PLLM/MB are used for memory; we do not change rate */
  703. if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
  704. return clk_hw_get_rate(hw);
  705. return pll->params->fixed_rate;
  706. }
  707. if (_get_table_rate(hw, &cfg, rate, *prate) &&
  708. pll->params->calc_rate(hw, &cfg, rate, *prate))
  709. return -EINVAL;
  710. return cfg.output_rate;
  711. }
  712. static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  713. unsigned long parent_rate)
  714. {
  715. struct tegra_clk_pll *pll = to_clk_pll(hw);
  716. struct tegra_clk_pll_freq_table cfg;
  717. u32 val;
  718. u64 rate = parent_rate;
  719. int pdiv;
  720. val = pll_readl_base(pll);
  721. if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
  722. return parent_rate;
  723. if ((pll->params->flags & TEGRA_PLL_FIXED) &&
  724. !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
  725. !(val & PLL_BASE_OVERRIDE)) {
  726. struct tegra_clk_pll_freq_table sel;
  727. if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
  728. parent_rate)) {
  729. pr_err("Clock %s has unknown fixed frequency\n",
  730. clk_hw_get_name(hw));
  731. BUG();
  732. }
  733. return pll->params->fixed_rate;
  734. }
  735. _get_pll_mnp(pll, &cfg);
  736. if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
  737. pdiv = 1;
  738. } else {
  739. pdiv = _hw_to_p_div(hw, cfg.p);
  740. if (pdiv < 0) {
  741. WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
  742. clk_hw_get_name(hw), cfg.p);
  743. pdiv = 1;
  744. }
  745. }
  746. if (pll->params->set_gain)
  747. pll->params->set_gain(&cfg);
  748. cfg.m *= pdiv;
  749. rate *= cfg.n;
  750. do_div(rate, cfg.m);
  751. return rate;
  752. }
  753. static int clk_plle_training(struct tegra_clk_pll *pll)
  754. {
  755. u32 val;
  756. unsigned long timeout;
  757. if (!pll->pmc)
  758. return -ENOSYS;
  759. /*
  760. * PLLE is already disabled, and setup cleared;
  761. * create falling edge on PLLE IDDQ input.
  762. */
  763. val = readl(pll->pmc + PMC_SATA_PWRGT);
  764. val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
  765. writel(val, pll->pmc + PMC_SATA_PWRGT);
  766. val = readl(pll->pmc + PMC_SATA_PWRGT);
  767. val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
  768. writel(val, pll->pmc + PMC_SATA_PWRGT);
  769. val = readl(pll->pmc + PMC_SATA_PWRGT);
  770. val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
  771. writel(val, pll->pmc + PMC_SATA_PWRGT);
  772. val = pll_readl_misc(pll);
  773. timeout = jiffies + msecs_to_jiffies(100);
  774. while (1) {
  775. val = pll_readl_misc(pll);
  776. if (val & PLLE_MISC_READY)
  777. break;
  778. if (time_after(jiffies, timeout)) {
  779. pr_err("%s: timeout waiting for PLLE\n", __func__);
  780. return -EBUSY;
  781. }
  782. udelay(300);
  783. }
  784. return 0;
  785. }
  786. static int clk_plle_enable(struct clk_hw *hw)
  787. {
  788. struct tegra_clk_pll *pll = to_clk_pll(hw);
  789. struct tegra_clk_pll_freq_table sel;
  790. unsigned long input_rate;
  791. u32 val;
  792. int err;
  793. if (clk_pll_is_enabled(hw))
  794. return 0;
  795. input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  796. if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
  797. return -EINVAL;
  798. clk_pll_disable(hw);
  799. val = pll_readl_misc(pll);
  800. val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
  801. pll_writel_misc(val, pll);
  802. val = pll_readl_misc(pll);
  803. if (!(val & PLLE_MISC_READY)) {
  804. err = clk_plle_training(pll);
  805. if (err)
  806. return err;
  807. }
  808. if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
  809. /* configure dividers */
  810. val = pll_readl_base(pll);
  811. val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
  812. divm_mask_shifted(pll));
  813. val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
  814. val |= sel.m << divm_shift(pll);
  815. val |= sel.n << divn_shift(pll);
  816. val |= sel.p << divp_shift(pll);
  817. val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
  818. pll_writel_base(val, pll);
  819. }
  820. val = pll_readl_misc(pll);
  821. val |= PLLE_MISC_SETUP_VALUE;
  822. val |= PLLE_MISC_LOCK_ENABLE;
  823. pll_writel_misc(val, pll);
  824. val = readl(pll->clk_base + PLLE_SS_CTRL);
  825. val &= ~PLLE_SS_COEFFICIENTS_MASK;
  826. val |= PLLE_SS_DISABLE;
  827. writel(val, pll->clk_base + PLLE_SS_CTRL);
  828. val = pll_readl_base(pll);
  829. val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
  830. pll_writel_base(val, pll);
  831. clk_pll_wait_for_lock(pll);
  832. return 0;
  833. }
  834. static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
  835. unsigned long parent_rate)
  836. {
  837. struct tegra_clk_pll *pll = to_clk_pll(hw);
  838. u32 val = pll_readl_base(pll);
  839. u32 divn = 0, divm = 0, divp = 0;
  840. u64 rate = parent_rate;
  841. divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
  842. divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
  843. divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
  844. divm *= divp;
  845. rate *= divn;
  846. do_div(rate, divm);
  847. return rate;
  848. }
  849. static void tegra_clk_pll_restore_context(struct clk_hw *hw)
  850. {
  851. struct tegra_clk_pll *pll = to_clk_pll(hw);
  852. struct clk_hw *parent = clk_hw_get_parent(hw);
  853. unsigned long parent_rate = clk_hw_get_rate(parent);
  854. unsigned long rate = clk_hw_get_rate(hw);
  855. if (clk_pll_is_enabled(hw))
  856. return;
  857. if (pll->params->set_defaults)
  858. pll->params->set_defaults(pll);
  859. clk_pll_set_rate(hw, rate, parent_rate);
  860. if (!__clk_get_enable_count(hw->clk))
  861. clk_pll_disable(hw);
  862. else
  863. clk_pll_enable(hw);
  864. }
  865. const struct clk_ops tegra_clk_pll_ops = {
  866. .is_enabled = clk_pll_is_enabled,
  867. .enable = clk_pll_enable,
  868. .disable = clk_pll_disable,
  869. .recalc_rate = clk_pll_recalc_rate,
  870. .round_rate = clk_pll_round_rate,
  871. .set_rate = clk_pll_set_rate,
  872. .restore_context = tegra_clk_pll_restore_context,
  873. };
  874. const struct clk_ops tegra_clk_plle_ops = {
  875. .recalc_rate = clk_plle_recalc_rate,
  876. .is_enabled = clk_pll_is_enabled,
  877. .disable = clk_pll_disable,
  878. .enable = clk_plle_enable,
  879. };
  880. /*
  881. * Structure defining the fields for USB UTMI clocks Parameters.
  882. */
  883. struct utmi_clk_param {
  884. /* Oscillator Frequency in Hz */
  885. u32 osc_frequency;
  886. /* UTMIP PLL Enable Delay Count */
  887. u8 enable_delay_count;
  888. /* UTMIP PLL Stable count */
  889. u8 stable_count;
  890. /* UTMIP PLL Active delay count */
  891. u8 active_delay_count;
  892. /* UTMIP PLL Xtal frequency count */
  893. u8 xtal_freq_count;
  894. };
  895. static const struct utmi_clk_param utmi_parameters[] = {
  896. {
  897. .osc_frequency = 13000000, .enable_delay_count = 0x02,
  898. .stable_count = 0x33, .active_delay_count = 0x05,
  899. .xtal_freq_count = 0x7f
  900. }, {
  901. .osc_frequency = 19200000, .enable_delay_count = 0x03,
  902. .stable_count = 0x4b, .active_delay_count = 0x06,
  903. .xtal_freq_count = 0xbb
  904. }, {
  905. .osc_frequency = 12000000, .enable_delay_count = 0x02,
  906. .stable_count = 0x2f, .active_delay_count = 0x04,
  907. .xtal_freq_count = 0x76
  908. }, {
  909. .osc_frequency = 26000000, .enable_delay_count = 0x04,
  910. .stable_count = 0x66, .active_delay_count = 0x09,
  911. .xtal_freq_count = 0xfe
  912. }, {
  913. .osc_frequency = 16800000, .enable_delay_count = 0x03,
  914. .stable_count = 0x41, .active_delay_count = 0x0a,
  915. .xtal_freq_count = 0xa4
  916. }, {
  917. .osc_frequency = 38400000, .enable_delay_count = 0x0,
  918. .stable_count = 0x0, .active_delay_count = 0x6,
  919. .xtal_freq_count = 0x80
  920. },
  921. };
  922. static int clk_pllu_enable(struct clk_hw *hw)
  923. {
  924. struct tegra_clk_pll *pll = to_clk_pll(hw);
  925. struct clk_hw *pll_ref = clk_hw_get_parent(hw);
  926. struct clk_hw *osc = clk_hw_get_parent(pll_ref);
  927. const struct utmi_clk_param *params = NULL;
  928. unsigned long flags = 0, input_rate;
  929. unsigned int i;
  930. int ret = 0;
  931. u32 value;
  932. if (!osc) {
  933. pr_err("%s: failed to get OSC clock\n", __func__);
  934. return -EINVAL;
  935. }
  936. input_rate = clk_hw_get_rate(osc);
  937. if (pll->lock)
  938. spin_lock_irqsave(pll->lock, flags);
  939. if (!clk_pll_is_enabled(hw))
  940. _clk_pll_enable(hw);
  941. ret = clk_pll_wait_for_lock(pll);
  942. if (ret < 0)
  943. goto out;
  944. for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
  945. if (input_rate == utmi_parameters[i].osc_frequency) {
  946. params = &utmi_parameters[i];
  947. break;
  948. }
  949. }
  950. if (!params) {
  951. pr_err("%s: unexpected input rate %lu Hz\n", __func__,
  952. input_rate);
  953. ret = -EINVAL;
  954. goto out;
  955. }
  956. value = pll_readl_base(pll);
  957. value &= ~PLLU_BASE_OVERRIDE;
  958. pll_writel_base(value, pll);
  959. value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
  960. /* Program UTMIP PLL stable and active counts */
  961. value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
  962. value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
  963. value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
  964. value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
  965. /* Remove power downs from UTMIP PLL control bits */
  966. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
  967. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
  968. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
  969. writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
  970. value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
  971. /* Program UTMIP PLL delay and oscillator frequency counts */
  972. value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
  973. value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
  974. value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
  975. value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
  976. /* Remove power downs from UTMIP PLL control bits */
  977. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
  978. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
  979. value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
  980. writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
  981. out:
  982. if (pll->lock)
  983. spin_unlock_irqrestore(pll->lock, flags);
  984. return ret;
  985. }
  986. static const struct clk_ops tegra_clk_pllu_ops = {
  987. .is_enabled = clk_pll_is_enabled,
  988. .enable = clk_pllu_enable,
  989. .disable = clk_pll_disable,
  990. .recalc_rate = clk_pll_recalc_rate,
  991. .round_rate = clk_pll_round_rate,
  992. .set_rate = clk_pll_set_rate,
  993. };
  994. static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
  995. unsigned long parent_rate)
  996. {
  997. u16 mdiv = parent_rate / pll_params->cf_min;
  998. if (pll_params->flags & TEGRA_MDIV_NEW)
  999. return (!pll_params->mdiv_default ? mdiv :
  1000. min(mdiv, pll_params->mdiv_default));
  1001. if (pll_params->mdiv_default)
  1002. return pll_params->mdiv_default;
  1003. if (parent_rate > pll_params->cf_max)
  1004. return 2;
  1005. else
  1006. return 1;
  1007. }
  1008. static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
  1009. struct tegra_clk_pll_freq_table *cfg,
  1010. unsigned long rate, unsigned long parent_rate)
  1011. {
  1012. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1013. unsigned int p;
  1014. int p_div;
  1015. if (!rate)
  1016. return -EINVAL;
  1017. p = DIV_ROUND_UP(pll->params->vco_min, rate);
  1018. cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
  1019. cfg->output_rate = rate * p;
  1020. cfg->n = cfg->output_rate * cfg->m / parent_rate;
  1021. cfg->input_rate = parent_rate;
  1022. p_div = _p_div_to_hw(hw, p);
  1023. if (p_div < 0)
  1024. return p_div;
  1025. cfg->p = p_div;
  1026. if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
  1027. return -EINVAL;
  1028. return 0;
  1029. }
  1030. #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
  1031. defined(CONFIG_ARCH_TEGRA_124_SOC) || \
  1032. defined(CONFIG_ARCH_TEGRA_132_SOC) || \
  1033. defined(CONFIG_ARCH_TEGRA_210_SOC)
  1034. u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
  1035. {
  1036. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1037. return (u16)_pll_fixed_mdiv(pll->params, input_rate);
  1038. }
  1039. static unsigned long _clip_vco_min(unsigned long vco_min,
  1040. unsigned long parent_rate)
  1041. {
  1042. return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
  1043. }
  1044. static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
  1045. void __iomem *clk_base,
  1046. unsigned long parent_rate)
  1047. {
  1048. u32 val;
  1049. u32 step_a, step_b;
  1050. switch (parent_rate) {
  1051. case 12000000:
  1052. case 13000000:
  1053. case 26000000:
  1054. step_a = 0x2B;
  1055. step_b = 0x0B;
  1056. break;
  1057. case 16800000:
  1058. step_a = 0x1A;
  1059. step_b = 0x09;
  1060. break;
  1061. case 19200000:
  1062. step_a = 0x12;
  1063. step_b = 0x08;
  1064. break;
  1065. default:
  1066. pr_err("%s: Unexpected reference rate %lu\n",
  1067. __func__, parent_rate);
  1068. WARN_ON(1);
  1069. return -EINVAL;
  1070. }
  1071. val = step_a << pll_params->stepa_shift;
  1072. val |= step_b << pll_params->stepb_shift;
  1073. writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
  1074. return 0;
  1075. }
  1076. static int _pll_ramp_calc_pll(struct clk_hw *hw,
  1077. struct tegra_clk_pll_freq_table *cfg,
  1078. unsigned long rate, unsigned long parent_rate)
  1079. {
  1080. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1081. int err = 0;
  1082. err = _get_table_rate(hw, cfg, rate, parent_rate);
  1083. if (err < 0)
  1084. err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
  1085. else {
  1086. if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
  1087. WARN_ON(1);
  1088. err = -EINVAL;
  1089. goto out;
  1090. }
  1091. }
  1092. if (cfg->p > pll->params->max_p)
  1093. err = -EINVAL;
  1094. out:
  1095. return err;
  1096. }
  1097. static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
  1098. unsigned long parent_rate)
  1099. {
  1100. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1101. struct tegra_clk_pll_freq_table cfg, old_cfg;
  1102. unsigned long flags = 0;
  1103. int ret;
  1104. ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
  1105. if (ret < 0)
  1106. return ret;
  1107. if (pll->lock)
  1108. spin_lock_irqsave(pll->lock, flags);
  1109. _get_pll_mnp(pll, &old_cfg);
  1110. if (pll->params->flags & TEGRA_PLL_VCO_OUT)
  1111. cfg.p = old_cfg.p;
  1112. if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
  1113. ret = _program_pll(hw, &cfg, rate);
  1114. if (pll->lock)
  1115. spin_unlock_irqrestore(pll->lock, flags);
  1116. return ret;
  1117. }
  1118. static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
  1119. unsigned long *prate)
  1120. {
  1121. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1122. struct tegra_clk_pll_freq_table cfg;
  1123. int ret, p_div;
  1124. u64 output_rate = *prate;
  1125. ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
  1126. if (ret < 0)
  1127. return ret;
  1128. p_div = _hw_to_p_div(hw, cfg.p);
  1129. if (p_div < 0)
  1130. return p_div;
  1131. if (pll->params->set_gain)
  1132. pll->params->set_gain(&cfg);
  1133. output_rate *= cfg.n;
  1134. do_div(output_rate, cfg.m * p_div);
  1135. return output_rate;
  1136. }
  1137. static void _pllcx_strobe(struct tegra_clk_pll *pll)
  1138. {
  1139. u32 val;
  1140. val = pll_readl_misc(pll);
  1141. val |= PLLCX_MISC_STROBE;
  1142. pll_writel_misc(val, pll);
  1143. udelay(2);
  1144. val &= ~PLLCX_MISC_STROBE;
  1145. pll_writel_misc(val, pll);
  1146. }
  1147. static int clk_pllc_enable(struct clk_hw *hw)
  1148. {
  1149. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1150. u32 val;
  1151. int ret;
  1152. unsigned long flags = 0;
  1153. if (clk_pll_is_enabled(hw))
  1154. return 0;
  1155. if (pll->lock)
  1156. spin_lock_irqsave(pll->lock, flags);
  1157. _clk_pll_enable(hw);
  1158. udelay(2);
  1159. val = pll_readl_misc(pll);
  1160. val &= ~PLLCX_MISC_RESET;
  1161. pll_writel_misc(val, pll);
  1162. udelay(2);
  1163. _pllcx_strobe(pll);
  1164. ret = clk_pll_wait_for_lock(pll);
  1165. if (pll->lock)
  1166. spin_unlock_irqrestore(pll->lock, flags);
  1167. return ret;
  1168. }
  1169. static void _clk_pllc_disable(struct clk_hw *hw)
  1170. {
  1171. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1172. u32 val;
  1173. _clk_pll_disable(hw);
  1174. val = pll_readl_misc(pll);
  1175. val |= PLLCX_MISC_RESET;
  1176. pll_writel_misc(val, pll);
  1177. udelay(2);
  1178. }
  1179. static void clk_pllc_disable(struct clk_hw *hw)
  1180. {
  1181. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1182. unsigned long flags = 0;
  1183. if (pll->lock)
  1184. spin_lock_irqsave(pll->lock, flags);
  1185. _clk_pllc_disable(hw);
  1186. if (pll->lock)
  1187. spin_unlock_irqrestore(pll->lock, flags);
  1188. }
  1189. static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
  1190. unsigned long input_rate, u32 n)
  1191. {
  1192. u32 val, n_threshold;
  1193. switch (input_rate) {
  1194. case 12000000:
  1195. n_threshold = 70;
  1196. break;
  1197. case 13000000:
  1198. case 26000000:
  1199. n_threshold = 71;
  1200. break;
  1201. case 16800000:
  1202. n_threshold = 55;
  1203. break;
  1204. case 19200000:
  1205. n_threshold = 48;
  1206. break;
  1207. default:
  1208. pr_err("%s: Unexpected reference rate %lu\n",
  1209. __func__, input_rate);
  1210. return -EINVAL;
  1211. }
  1212. val = pll_readl_misc(pll);
  1213. val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
  1214. val |= n <= n_threshold ?
  1215. PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
  1216. pll_writel_misc(val, pll);
  1217. return 0;
  1218. }
  1219. static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
  1220. unsigned long parent_rate)
  1221. {
  1222. struct tegra_clk_pll_freq_table cfg, old_cfg;
  1223. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1224. unsigned long flags = 0;
  1225. int state, ret = 0;
  1226. if (pll->lock)
  1227. spin_lock_irqsave(pll->lock, flags);
  1228. ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
  1229. if (ret < 0)
  1230. goto out;
  1231. _get_pll_mnp(pll, &old_cfg);
  1232. if (cfg.m != old_cfg.m) {
  1233. WARN_ON(1);
  1234. goto out;
  1235. }
  1236. if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
  1237. goto out;
  1238. state = clk_pll_is_enabled(hw);
  1239. if (state)
  1240. _clk_pllc_disable(hw);
  1241. ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
  1242. if (ret < 0)
  1243. goto out;
  1244. _update_pll_mnp(pll, &cfg);
  1245. if (state)
  1246. ret = clk_pllc_enable(hw);
  1247. out:
  1248. if (pll->lock)
  1249. spin_unlock_irqrestore(pll->lock, flags);
  1250. return ret;
  1251. }
  1252. static long _pllre_calc_rate(struct tegra_clk_pll *pll,
  1253. struct tegra_clk_pll_freq_table *cfg,
  1254. unsigned long rate, unsigned long parent_rate)
  1255. {
  1256. u16 m, n;
  1257. u64 output_rate = parent_rate;
  1258. m = _pll_fixed_mdiv(pll->params, parent_rate);
  1259. n = rate * m / parent_rate;
  1260. output_rate *= n;
  1261. do_div(output_rate, m);
  1262. if (cfg) {
  1263. cfg->m = m;
  1264. cfg->n = n;
  1265. }
  1266. return output_rate;
  1267. }
  1268. static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
  1269. unsigned long parent_rate)
  1270. {
  1271. struct tegra_clk_pll_freq_table cfg, old_cfg;
  1272. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1273. unsigned long flags = 0;
  1274. int state, ret = 0;
  1275. if (pll->lock)
  1276. spin_lock_irqsave(pll->lock, flags);
  1277. _pllre_calc_rate(pll, &cfg, rate, parent_rate);
  1278. _get_pll_mnp(pll, &old_cfg);
  1279. cfg.p = old_cfg.p;
  1280. if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
  1281. state = clk_pll_is_enabled(hw);
  1282. if (state)
  1283. _clk_pll_disable(hw);
  1284. _update_pll_mnp(pll, &cfg);
  1285. if (state) {
  1286. _clk_pll_enable(hw);
  1287. ret = clk_pll_wait_for_lock(pll);
  1288. }
  1289. }
  1290. if (pll->lock)
  1291. spin_unlock_irqrestore(pll->lock, flags);
  1292. return ret;
  1293. }
  1294. static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
  1295. unsigned long parent_rate)
  1296. {
  1297. struct tegra_clk_pll_freq_table cfg;
  1298. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1299. u64 rate = parent_rate;
  1300. _get_pll_mnp(pll, &cfg);
  1301. rate *= cfg.n;
  1302. do_div(rate, cfg.m);
  1303. return rate;
  1304. }
  1305. static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
  1306. unsigned long *prate)
  1307. {
  1308. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1309. return _pllre_calc_rate(pll, NULL, rate, *prate);
  1310. }
  1311. static int clk_plle_tegra114_enable(struct clk_hw *hw)
  1312. {
  1313. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1314. struct tegra_clk_pll_freq_table sel;
  1315. u32 val;
  1316. int ret;
  1317. unsigned long flags = 0;
  1318. unsigned long input_rate;
  1319. input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  1320. if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
  1321. return -EINVAL;
  1322. if (pll->lock)
  1323. spin_lock_irqsave(pll->lock, flags);
  1324. val = pll_readl_base(pll);
  1325. val &= ~BIT(29); /* Disable lock override */
  1326. pll_writel_base(val, pll);
  1327. val = pll_readl(pll->params->aux_reg, pll);
  1328. val |= PLLE_AUX_ENABLE_SWCTL;
  1329. val &= ~PLLE_AUX_SEQ_ENABLE;
  1330. pll_writel(val, pll->params->aux_reg, pll);
  1331. udelay(1);
  1332. val = pll_readl_misc(pll);
  1333. val |= PLLE_MISC_LOCK_ENABLE;
  1334. val |= PLLE_MISC_IDDQ_SW_CTRL;
  1335. val &= ~PLLE_MISC_IDDQ_SW_VALUE;
  1336. val |= PLLE_MISC_PLLE_PTS;
  1337. val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
  1338. pll_writel_misc(val, pll);
  1339. udelay(5);
  1340. val = pll_readl(PLLE_SS_CTRL, pll);
  1341. val |= PLLE_SS_DISABLE;
  1342. pll_writel(val, PLLE_SS_CTRL, pll);
  1343. val = pll_readl_base(pll);
  1344. val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
  1345. divm_mask_shifted(pll));
  1346. val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
  1347. val |= sel.m << divm_shift(pll);
  1348. val |= sel.n << divn_shift(pll);
  1349. val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
  1350. pll_writel_base(val, pll);
  1351. udelay(1);
  1352. _clk_pll_enable(hw);
  1353. ret = clk_pll_wait_for_lock(pll);
  1354. if (ret < 0)
  1355. goto out;
  1356. val = pll_readl(PLLE_SS_CTRL, pll);
  1357. val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
  1358. val &= ~PLLE_SS_COEFFICIENTS_MASK;
  1359. val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
  1360. pll_writel(val, PLLE_SS_CTRL, pll);
  1361. val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
  1362. pll_writel(val, PLLE_SS_CTRL, pll);
  1363. udelay(1);
  1364. val &= ~PLLE_SS_CNTL_INTERP_RESET;
  1365. pll_writel(val, PLLE_SS_CTRL, pll);
  1366. udelay(1);
  1367. /* Enable HW control of XUSB brick PLL */
  1368. val = pll_readl_misc(pll);
  1369. val &= ~PLLE_MISC_IDDQ_SW_CTRL;
  1370. pll_writel_misc(val, pll);
  1371. val = pll_readl(pll->params->aux_reg, pll);
  1372. val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
  1373. val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
  1374. pll_writel(val, pll->params->aux_reg, pll);
  1375. udelay(1);
  1376. val |= PLLE_AUX_SEQ_ENABLE;
  1377. pll_writel(val, pll->params->aux_reg, pll);
  1378. val = pll_readl(XUSBIO_PLL_CFG0, pll);
  1379. val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
  1380. XUSBIO_PLL_CFG0_SEQ_START_STATE);
  1381. val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
  1382. XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
  1383. pll_writel(val, XUSBIO_PLL_CFG0, pll);
  1384. udelay(1);
  1385. val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
  1386. pll_writel(val, XUSBIO_PLL_CFG0, pll);
  1387. /* Enable HW control of SATA PLL */
  1388. val = pll_readl(SATA_PLL_CFG0, pll);
  1389. val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
  1390. val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
  1391. val |= SATA_PLL_CFG0_SEQ_START_STATE;
  1392. pll_writel(val, SATA_PLL_CFG0, pll);
  1393. udelay(1);
  1394. val = pll_readl(SATA_PLL_CFG0, pll);
  1395. val |= SATA_PLL_CFG0_SEQ_ENABLE;
  1396. pll_writel(val, SATA_PLL_CFG0, pll);
  1397. out:
  1398. if (pll->lock)
  1399. spin_unlock_irqrestore(pll->lock, flags);
  1400. return ret;
  1401. }
  1402. static void clk_plle_tegra114_disable(struct clk_hw *hw)
  1403. {
  1404. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1405. unsigned long flags = 0;
  1406. u32 val;
  1407. if (pll->lock)
  1408. spin_lock_irqsave(pll->lock, flags);
  1409. _clk_pll_disable(hw);
  1410. val = pll_readl_misc(pll);
  1411. val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
  1412. pll_writel_misc(val, pll);
  1413. udelay(1);
  1414. if (pll->lock)
  1415. spin_unlock_irqrestore(pll->lock, flags);
  1416. }
  1417. static int clk_pllu_tegra114_enable(struct clk_hw *hw)
  1418. {
  1419. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1420. const struct utmi_clk_param *params = NULL;
  1421. struct clk *osc = __clk_lookup("osc");
  1422. unsigned long flags = 0, input_rate;
  1423. unsigned int i;
  1424. int ret = 0;
  1425. u32 value;
  1426. if (!osc) {
  1427. pr_err("%s: failed to get OSC clock\n", __func__);
  1428. return -EINVAL;
  1429. }
  1430. input_rate = clk_hw_get_rate(__clk_get_hw(osc));
  1431. if (pll->lock)
  1432. spin_lock_irqsave(pll->lock, flags);
  1433. if (!clk_pll_is_enabled(hw))
  1434. _clk_pll_enable(hw);
  1435. ret = clk_pll_wait_for_lock(pll);
  1436. if (ret < 0)
  1437. goto out;
  1438. for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
  1439. if (input_rate == utmi_parameters[i].osc_frequency) {
  1440. params = &utmi_parameters[i];
  1441. break;
  1442. }
  1443. }
  1444. if (!params) {
  1445. pr_err("%s: unexpected input rate %lu Hz\n", __func__,
  1446. input_rate);
  1447. ret = -EINVAL;
  1448. goto out;
  1449. }
  1450. value = pll_readl_base(pll);
  1451. value &= ~PLLU_BASE_OVERRIDE;
  1452. pll_writel_base(value, pll);
  1453. value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
  1454. /* Program UTMIP PLL stable and active counts */
  1455. value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
  1456. value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
  1457. value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
  1458. value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
  1459. /* Remove power downs from UTMIP PLL control bits */
  1460. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
  1461. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
  1462. value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
  1463. writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
  1464. value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
  1465. /* Program UTMIP PLL delay and oscillator frequency counts */
  1466. value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
  1467. value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
  1468. value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
  1469. value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
  1470. /* Remove power downs from UTMIP PLL control bits */
  1471. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
  1472. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
  1473. value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
  1474. value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
  1475. writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
  1476. /* Setup HW control of UTMIPLL */
  1477. value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1478. value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
  1479. value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
  1480. value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
  1481. writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1482. value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
  1483. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
  1484. value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
  1485. writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
  1486. udelay(1);
  1487. /*
  1488. * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
  1489. * to USB2
  1490. */
  1491. value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1492. value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
  1493. value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
  1494. writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1495. udelay(1);
  1496. /* Enable HW control of UTMIPLL */
  1497. value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1498. value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
  1499. writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
  1500. out:
  1501. if (pll->lock)
  1502. spin_unlock_irqrestore(pll->lock, flags);
  1503. return ret;
  1504. }
  1505. static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
  1506. {
  1507. u32 val, val_aux;
  1508. /* ensure parent is set to pll_ref */
  1509. val = pll_readl_base(pll);
  1510. val_aux = pll_readl(pll->params->aux_reg, pll);
  1511. if (val & PLL_BASE_ENABLE) {
  1512. if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
  1513. (val_aux & PLLE_AUX_PLLP_SEL))
  1514. WARN(1, "pll_e enabled with unsupported parent %s\n",
  1515. (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
  1516. "pll_re_vco");
  1517. } else {
  1518. val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
  1519. pll_writel(val_aux, pll->params->aux_reg, pll);
  1520. fence_udelay(1, pll->clk_base);
  1521. }
  1522. }
  1523. #endif
  1524. static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
  1525. void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
  1526. spinlock_t *lock)
  1527. {
  1528. struct tegra_clk_pll *pll;
  1529. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  1530. if (!pll)
  1531. return ERR_PTR(-ENOMEM);
  1532. pll->clk_base = clk_base;
  1533. pll->pmc = pmc;
  1534. pll->params = pll_params;
  1535. pll->lock = lock;
  1536. if (!pll_params->div_nmp)
  1537. pll_params->div_nmp = &default_nmp;
  1538. return pll;
  1539. }
  1540. static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
  1541. const char *name, const char *parent_name, unsigned long flags,
  1542. const struct clk_ops *ops)
  1543. {
  1544. struct clk_init_data init;
  1545. init.name = name;
  1546. init.ops = ops;
  1547. init.flags = flags;
  1548. init.parent_names = (parent_name ? &parent_name : NULL);
  1549. init.num_parents = (parent_name ? 1 : 0);
  1550. /* Default to _calc_rate if unspecified */
  1551. if (!pll->params->calc_rate) {
  1552. if (pll->params->flags & TEGRA_PLLM)
  1553. pll->params->calc_rate = _calc_dynamic_ramp_rate;
  1554. else
  1555. pll->params->calc_rate = _calc_rate;
  1556. }
  1557. if (pll->params->set_defaults)
  1558. pll->params->set_defaults(pll);
  1559. /* Data in .init is copied by clk_register(), so stack variable OK */
  1560. pll->hw.init = &init;
  1561. return clk_register(NULL, &pll->hw);
  1562. }
  1563. struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
  1564. void __iomem *clk_base, void __iomem *pmc,
  1565. unsigned long flags, struct tegra_clk_pll_params *pll_params,
  1566. spinlock_t *lock)
  1567. {
  1568. struct tegra_clk_pll *pll;
  1569. struct clk *clk;
  1570. pll_params->flags |= TEGRA_PLL_BYPASS;
  1571. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1572. if (IS_ERR(pll))
  1573. return ERR_CAST(pll);
  1574. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1575. &tegra_clk_pll_ops);
  1576. if (IS_ERR(clk))
  1577. kfree(pll);
  1578. return clk;
  1579. }
  1580. static struct div_nmp pll_e_nmp = {
  1581. .divn_shift = PLLE_BASE_DIVN_SHIFT,
  1582. .divn_width = PLLE_BASE_DIVN_WIDTH,
  1583. .divm_shift = PLLE_BASE_DIVM_SHIFT,
  1584. .divm_width = PLLE_BASE_DIVM_WIDTH,
  1585. .divp_shift = PLLE_BASE_DIVP_SHIFT,
  1586. .divp_width = PLLE_BASE_DIVP_WIDTH,
  1587. };
  1588. struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
  1589. void __iomem *clk_base, void __iomem *pmc,
  1590. unsigned long flags, struct tegra_clk_pll_params *pll_params,
  1591. spinlock_t *lock)
  1592. {
  1593. struct tegra_clk_pll *pll;
  1594. struct clk *clk;
  1595. pll_params->flags |= TEGRA_PLL_BYPASS;
  1596. if (!pll_params->div_nmp)
  1597. pll_params->div_nmp = &pll_e_nmp;
  1598. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1599. if (IS_ERR(pll))
  1600. return ERR_CAST(pll);
  1601. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1602. &tegra_clk_plle_ops);
  1603. if (IS_ERR(clk))
  1604. kfree(pll);
  1605. return clk;
  1606. }
  1607. struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
  1608. void __iomem *clk_base, unsigned long flags,
  1609. struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
  1610. {
  1611. struct tegra_clk_pll *pll;
  1612. struct clk *clk;
  1613. pll_params->flags |= TEGRA_PLLU;
  1614. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  1615. if (IS_ERR(pll))
  1616. return ERR_CAST(pll);
  1617. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1618. &tegra_clk_pllu_ops);
  1619. if (IS_ERR(clk))
  1620. kfree(pll);
  1621. return clk;
  1622. }
  1623. #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
  1624. defined(CONFIG_ARCH_TEGRA_124_SOC) || \
  1625. defined(CONFIG_ARCH_TEGRA_132_SOC) || \
  1626. defined(CONFIG_ARCH_TEGRA_210_SOC)
  1627. static const struct clk_ops tegra_clk_pllxc_ops = {
  1628. .is_enabled = clk_pll_is_enabled,
  1629. .enable = clk_pll_enable,
  1630. .disable = clk_pll_disable,
  1631. .recalc_rate = clk_pll_recalc_rate,
  1632. .round_rate = clk_pll_ramp_round_rate,
  1633. .set_rate = clk_pllxc_set_rate,
  1634. };
  1635. static const struct clk_ops tegra_clk_pllc_ops = {
  1636. .is_enabled = clk_pll_is_enabled,
  1637. .enable = clk_pllc_enable,
  1638. .disable = clk_pllc_disable,
  1639. .recalc_rate = clk_pll_recalc_rate,
  1640. .round_rate = clk_pll_ramp_round_rate,
  1641. .set_rate = clk_pllc_set_rate,
  1642. };
  1643. static const struct clk_ops tegra_clk_pllre_ops = {
  1644. .is_enabled = clk_pll_is_enabled,
  1645. .enable = clk_pll_enable,
  1646. .disable = clk_pll_disable,
  1647. .recalc_rate = clk_pllre_recalc_rate,
  1648. .round_rate = clk_pllre_round_rate,
  1649. .set_rate = clk_pllre_set_rate,
  1650. };
  1651. static const struct clk_ops tegra_clk_plle_tegra114_ops = {
  1652. .is_enabled = clk_pll_is_enabled,
  1653. .enable = clk_plle_tegra114_enable,
  1654. .disable = clk_plle_tegra114_disable,
  1655. .recalc_rate = clk_pll_recalc_rate,
  1656. };
  1657. static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
  1658. .is_enabled = clk_pll_is_enabled,
  1659. .enable = clk_pllu_tegra114_enable,
  1660. .disable = clk_pll_disable,
  1661. .recalc_rate = clk_pll_recalc_rate,
  1662. };
  1663. struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
  1664. void __iomem *clk_base, void __iomem *pmc,
  1665. unsigned long flags,
  1666. struct tegra_clk_pll_params *pll_params,
  1667. spinlock_t *lock)
  1668. {
  1669. struct tegra_clk_pll *pll;
  1670. struct clk *clk, *parent;
  1671. unsigned long parent_rate;
  1672. u32 val, val_iddq;
  1673. parent = __clk_lookup(parent_name);
  1674. if (!parent) {
  1675. WARN(1, "parent clk %s of %s must be registered first\n",
  1676. parent_name, name);
  1677. return ERR_PTR(-EINVAL);
  1678. }
  1679. if (!pll_params->pdiv_tohw)
  1680. return ERR_PTR(-EINVAL);
  1681. parent_rate = clk_get_rate(parent);
  1682. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1683. if (pll_params->adjust_vco)
  1684. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  1685. parent_rate);
  1686. /*
  1687. * If the pll has a set_defaults callback, it will take care of
  1688. * configuring dynamic ramping and setting IDDQ in that path.
  1689. */
  1690. if (!pll_params->set_defaults) {
  1691. int err;
  1692. err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
  1693. if (err)
  1694. return ERR_PTR(err);
  1695. val = readl_relaxed(clk_base + pll_params->base_reg);
  1696. val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
  1697. if (val & PLL_BASE_ENABLE)
  1698. WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
  1699. else {
  1700. val_iddq |= BIT(pll_params->iddq_bit_idx);
  1701. writel_relaxed(val_iddq,
  1702. clk_base + pll_params->iddq_reg);
  1703. }
  1704. }
  1705. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1706. if (IS_ERR(pll))
  1707. return ERR_CAST(pll);
  1708. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1709. &tegra_clk_pllxc_ops);
  1710. if (IS_ERR(clk))
  1711. kfree(pll);
  1712. return clk;
  1713. }
  1714. struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
  1715. void __iomem *clk_base, void __iomem *pmc,
  1716. unsigned long flags,
  1717. struct tegra_clk_pll_params *pll_params,
  1718. spinlock_t *lock, unsigned long parent_rate)
  1719. {
  1720. u32 val;
  1721. struct tegra_clk_pll *pll;
  1722. struct clk *clk;
  1723. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1724. if (pll_params->adjust_vco)
  1725. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  1726. parent_rate);
  1727. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1728. if (IS_ERR(pll))
  1729. return ERR_CAST(pll);
  1730. /* program minimum rate by default */
  1731. val = pll_readl_base(pll);
  1732. if (val & PLL_BASE_ENABLE)
  1733. WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
  1734. BIT(pll_params->iddq_bit_idx));
  1735. else {
  1736. int m;
  1737. m = _pll_fixed_mdiv(pll_params, parent_rate);
  1738. val = m << divm_shift(pll);
  1739. val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
  1740. pll_writel_base(val, pll);
  1741. }
  1742. /* disable lock override */
  1743. val = pll_readl_misc(pll);
  1744. val &= ~BIT(29);
  1745. pll_writel_misc(val, pll);
  1746. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1747. &tegra_clk_pllre_ops);
  1748. if (IS_ERR(clk))
  1749. kfree(pll);
  1750. return clk;
  1751. }
  1752. struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
  1753. void __iomem *clk_base, void __iomem *pmc,
  1754. unsigned long flags,
  1755. struct tegra_clk_pll_params *pll_params,
  1756. spinlock_t *lock)
  1757. {
  1758. struct tegra_clk_pll *pll;
  1759. struct clk *clk, *parent;
  1760. unsigned long parent_rate;
  1761. if (!pll_params->pdiv_tohw)
  1762. return ERR_PTR(-EINVAL);
  1763. parent = __clk_lookup(parent_name);
  1764. if (!parent) {
  1765. WARN(1, "parent clk %s of %s must be registered first\n",
  1766. parent_name, name);
  1767. return ERR_PTR(-EINVAL);
  1768. }
  1769. parent_rate = clk_get_rate(parent);
  1770. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1771. if (pll_params->adjust_vco)
  1772. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  1773. parent_rate);
  1774. pll_params->flags |= TEGRA_PLL_BYPASS;
  1775. pll_params->flags |= TEGRA_PLLM;
  1776. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1777. if (IS_ERR(pll))
  1778. return ERR_CAST(pll);
  1779. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1780. &tegra_clk_pll_ops);
  1781. if (IS_ERR(clk))
  1782. kfree(pll);
  1783. return clk;
  1784. }
  1785. struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
  1786. void __iomem *clk_base, void __iomem *pmc,
  1787. unsigned long flags,
  1788. struct tegra_clk_pll_params *pll_params,
  1789. spinlock_t *lock)
  1790. {
  1791. struct clk *parent, *clk;
  1792. const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
  1793. struct tegra_clk_pll *pll;
  1794. struct tegra_clk_pll_freq_table cfg;
  1795. unsigned long parent_rate;
  1796. if (!p_tohw)
  1797. return ERR_PTR(-EINVAL);
  1798. parent = __clk_lookup(parent_name);
  1799. if (!parent) {
  1800. WARN(1, "parent clk %s of %s must be registered first\n",
  1801. parent_name, name);
  1802. return ERR_PTR(-EINVAL);
  1803. }
  1804. parent_rate = clk_get_rate(parent);
  1805. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1806. pll_params->flags |= TEGRA_PLL_BYPASS;
  1807. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1808. if (IS_ERR(pll))
  1809. return ERR_CAST(pll);
  1810. /*
  1811. * Most of PLLC register fields are shadowed, and can not be read
  1812. * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
  1813. * Initialize PLL to default state: disabled, reset; shadow registers
  1814. * loaded with default parameters; dividers are preset for half of
  1815. * minimum VCO rate (the latter assured that shadowed divider settings
  1816. * are within supported range).
  1817. */
  1818. cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
  1819. cfg.n = cfg.m * pll_params->vco_min / parent_rate;
  1820. while (p_tohw->pdiv) {
  1821. if (p_tohw->pdiv == 2) {
  1822. cfg.p = p_tohw->hw_val;
  1823. break;
  1824. }
  1825. p_tohw++;
  1826. }
  1827. if (!p_tohw->pdiv) {
  1828. WARN_ON(1);
  1829. return ERR_PTR(-EINVAL);
  1830. }
  1831. pll_writel_base(0, pll);
  1832. _update_pll_mnp(pll, &cfg);
  1833. pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
  1834. pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
  1835. pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
  1836. pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
  1837. _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
  1838. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1839. &tegra_clk_pllc_ops);
  1840. if (IS_ERR(clk))
  1841. kfree(pll);
  1842. return clk;
  1843. }
  1844. struct clk *tegra_clk_register_plle_tegra114(const char *name,
  1845. const char *parent_name,
  1846. void __iomem *clk_base, unsigned long flags,
  1847. struct tegra_clk_pll_params *pll_params,
  1848. spinlock_t *lock)
  1849. {
  1850. struct tegra_clk_pll *pll;
  1851. struct clk *clk;
  1852. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  1853. if (IS_ERR(pll))
  1854. return ERR_CAST(pll);
  1855. _clk_plle_tegra_init_parent(pll);
  1856. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1857. &tegra_clk_plle_tegra114_ops);
  1858. if (IS_ERR(clk))
  1859. kfree(pll);
  1860. return clk;
  1861. }
  1862. struct clk *
  1863. tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
  1864. void __iomem *clk_base, unsigned long flags,
  1865. struct tegra_clk_pll_params *pll_params,
  1866. spinlock_t *lock)
  1867. {
  1868. struct tegra_clk_pll *pll;
  1869. struct clk *clk;
  1870. pll_params->flags |= TEGRA_PLLU;
  1871. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  1872. if (IS_ERR(pll))
  1873. return ERR_CAST(pll);
  1874. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1875. &tegra_clk_pllu_tegra114_ops);
  1876. if (IS_ERR(clk))
  1877. kfree(pll);
  1878. return clk;
  1879. }
  1880. #endif
  1881. #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
  1882. static const struct clk_ops tegra_clk_pllss_ops = {
  1883. .is_enabled = clk_pll_is_enabled,
  1884. .enable = clk_pll_enable,
  1885. .disable = clk_pll_disable,
  1886. .recalc_rate = clk_pll_recalc_rate,
  1887. .round_rate = clk_pll_ramp_round_rate,
  1888. .set_rate = clk_pllxc_set_rate,
  1889. .restore_context = tegra_clk_pll_restore_context,
  1890. };
  1891. struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
  1892. void __iomem *clk_base, unsigned long flags,
  1893. struct tegra_clk_pll_params *pll_params,
  1894. spinlock_t *lock)
  1895. {
  1896. struct tegra_clk_pll *pll;
  1897. struct clk *clk, *parent;
  1898. struct tegra_clk_pll_freq_table cfg;
  1899. unsigned long parent_rate;
  1900. u32 val, val_iddq;
  1901. int i;
  1902. if (!pll_params->div_nmp)
  1903. return ERR_PTR(-EINVAL);
  1904. parent = __clk_lookup(parent_name);
  1905. if (!parent) {
  1906. WARN(1, "parent clk %s of %s must be registered first\n",
  1907. parent_name, name);
  1908. return ERR_PTR(-EINVAL);
  1909. }
  1910. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  1911. if (IS_ERR(pll))
  1912. return ERR_CAST(pll);
  1913. val = pll_readl_base(pll);
  1914. val &= ~PLLSS_REF_SRC_SEL_MASK;
  1915. pll_writel_base(val, pll);
  1916. parent_rate = clk_get_rate(parent);
  1917. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1918. /* initialize PLL to minimum rate */
  1919. cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
  1920. cfg.n = cfg.m * pll_params->vco_min / parent_rate;
  1921. for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
  1922. ;
  1923. if (!i) {
  1924. kfree(pll);
  1925. return ERR_PTR(-EINVAL);
  1926. }
  1927. cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
  1928. _update_pll_mnp(pll, &cfg);
  1929. pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
  1930. pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
  1931. pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
  1932. pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
  1933. val = pll_readl_base(pll);
  1934. val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
  1935. if (val & PLL_BASE_ENABLE) {
  1936. if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
  1937. WARN(1, "%s is on but IDDQ set\n", name);
  1938. kfree(pll);
  1939. return ERR_PTR(-EINVAL);
  1940. }
  1941. } else {
  1942. val_iddq |= BIT(pll_params->iddq_bit_idx);
  1943. writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
  1944. }
  1945. val &= ~PLLSS_LOCK_OVERRIDE;
  1946. pll_writel_base(val, pll);
  1947. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1948. &tegra_clk_pllss_ops);
  1949. if (IS_ERR(clk))
  1950. kfree(pll);
  1951. return clk;
  1952. }
  1953. #endif
  1954. #if defined(CONFIG_ARCH_TEGRA_210_SOC)
  1955. struct clk *tegra_clk_register_pllre_tegra210(const char *name,
  1956. const char *parent_name, void __iomem *clk_base,
  1957. void __iomem *pmc, unsigned long flags,
  1958. struct tegra_clk_pll_params *pll_params,
  1959. spinlock_t *lock, unsigned long parent_rate)
  1960. {
  1961. struct tegra_clk_pll *pll;
  1962. struct clk *clk;
  1963. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  1964. if (pll_params->adjust_vco)
  1965. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  1966. parent_rate);
  1967. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  1968. if (IS_ERR(pll))
  1969. return ERR_CAST(pll);
  1970. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  1971. &tegra_clk_pll_ops);
  1972. if (IS_ERR(clk))
  1973. kfree(pll);
  1974. return clk;
  1975. }
  1976. static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
  1977. {
  1978. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1979. u32 val;
  1980. val = pll_readl_base(pll);
  1981. return val & PLLE_BASE_ENABLE ? 1 : 0;
  1982. }
  1983. static int clk_plle_tegra210_enable(struct clk_hw *hw)
  1984. {
  1985. struct tegra_clk_pll *pll = to_clk_pll(hw);
  1986. struct tegra_clk_pll_freq_table sel;
  1987. u32 val;
  1988. int ret = 0;
  1989. unsigned long flags = 0;
  1990. unsigned long input_rate;
  1991. if (clk_plle_tegra210_is_enabled(hw))
  1992. return 0;
  1993. input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  1994. if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
  1995. return -EINVAL;
  1996. if (pll->lock)
  1997. spin_lock_irqsave(pll->lock, flags);
  1998. val = pll_readl(pll->params->aux_reg, pll);
  1999. if (val & PLLE_AUX_SEQ_ENABLE)
  2000. goto out;
  2001. val = pll_readl_base(pll);
  2002. val &= ~BIT(30); /* Disable lock override */
  2003. pll_writel_base(val, pll);
  2004. val = pll_readl_misc(pll);
  2005. val |= PLLE_MISC_LOCK_ENABLE;
  2006. val |= PLLE_MISC_IDDQ_SW_CTRL;
  2007. val &= ~PLLE_MISC_IDDQ_SW_VALUE;
  2008. val |= PLLE_MISC_PLLE_PTS;
  2009. val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
  2010. pll_writel_misc(val, pll);
  2011. udelay(5);
  2012. val = pll_readl(PLLE_SS_CTRL, pll);
  2013. val |= PLLE_SS_DISABLE;
  2014. pll_writel(val, PLLE_SS_CTRL, pll);
  2015. val = pll_readl_base(pll);
  2016. val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
  2017. divm_mask_shifted(pll));
  2018. val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
  2019. val |= sel.m << divm_shift(pll);
  2020. val |= sel.n << divn_shift(pll);
  2021. val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
  2022. pll_writel_base(val, pll);
  2023. udelay(1);
  2024. val = pll_readl_base(pll);
  2025. val |= PLLE_BASE_ENABLE;
  2026. pll_writel_base(val, pll);
  2027. ret = clk_pll_wait_for_lock(pll);
  2028. if (ret < 0)
  2029. goto out;
  2030. val = pll_readl(PLLE_SS_CTRL, pll);
  2031. val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
  2032. val &= ~PLLE_SS_COEFFICIENTS_MASK;
  2033. val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
  2034. pll_writel(val, PLLE_SS_CTRL, pll);
  2035. val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
  2036. pll_writel(val, PLLE_SS_CTRL, pll);
  2037. udelay(1);
  2038. val &= ~PLLE_SS_CNTL_INTERP_RESET;
  2039. pll_writel(val, PLLE_SS_CTRL, pll);
  2040. udelay(1);
  2041. val = pll_readl_misc(pll);
  2042. val &= ~PLLE_MISC_IDDQ_SW_CTRL;
  2043. pll_writel_misc(val, pll);
  2044. val = pll_readl(pll->params->aux_reg, pll);
  2045. val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
  2046. val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
  2047. pll_writel(val, pll->params->aux_reg, pll);
  2048. udelay(1);
  2049. val |= PLLE_AUX_SEQ_ENABLE;
  2050. pll_writel(val, pll->params->aux_reg, pll);
  2051. out:
  2052. if (pll->lock)
  2053. spin_unlock_irqrestore(pll->lock, flags);
  2054. return ret;
  2055. }
  2056. static void clk_plle_tegra210_disable(struct clk_hw *hw)
  2057. {
  2058. struct tegra_clk_pll *pll = to_clk_pll(hw);
  2059. unsigned long flags = 0;
  2060. u32 val;
  2061. if (pll->lock)
  2062. spin_lock_irqsave(pll->lock, flags);
  2063. /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
  2064. val = pll_readl(pll->params->aux_reg, pll);
  2065. if (val & PLLE_AUX_SEQ_ENABLE)
  2066. goto out;
  2067. val = pll_readl_base(pll);
  2068. val &= ~PLLE_BASE_ENABLE;
  2069. pll_writel_base(val, pll);
  2070. val = pll_readl(pll->params->aux_reg, pll);
  2071. val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
  2072. pll_writel(val, pll->params->aux_reg, pll);
  2073. val = pll_readl_misc(pll);
  2074. val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
  2075. pll_writel_misc(val, pll);
  2076. udelay(1);
  2077. out:
  2078. if (pll->lock)
  2079. spin_unlock_irqrestore(pll->lock, flags);
  2080. }
  2081. static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
  2082. {
  2083. struct tegra_clk_pll *pll = to_clk_pll(hw);
  2084. _clk_plle_tegra_init_parent(pll);
  2085. }
  2086. static const struct clk_ops tegra_clk_plle_tegra210_ops = {
  2087. .is_enabled = clk_plle_tegra210_is_enabled,
  2088. .enable = clk_plle_tegra210_enable,
  2089. .disable = clk_plle_tegra210_disable,
  2090. .recalc_rate = clk_pll_recalc_rate,
  2091. .restore_context = tegra_clk_plle_t210_restore_context,
  2092. };
  2093. struct clk *tegra_clk_register_plle_tegra210(const char *name,
  2094. const char *parent_name,
  2095. void __iomem *clk_base, unsigned long flags,
  2096. struct tegra_clk_pll_params *pll_params,
  2097. spinlock_t *lock)
  2098. {
  2099. struct tegra_clk_pll *pll;
  2100. struct clk *clk;
  2101. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  2102. if (IS_ERR(pll))
  2103. return ERR_CAST(pll);
  2104. _clk_plle_tegra_init_parent(pll);
  2105. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  2106. &tegra_clk_plle_tegra210_ops);
  2107. if (IS_ERR(clk))
  2108. kfree(pll);
  2109. return clk;
  2110. }
  2111. struct clk *tegra_clk_register_pllc_tegra210(const char *name,
  2112. const char *parent_name, void __iomem *clk_base,
  2113. void __iomem *pmc, unsigned long flags,
  2114. struct tegra_clk_pll_params *pll_params,
  2115. spinlock_t *lock)
  2116. {
  2117. struct clk *parent, *clk;
  2118. const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
  2119. struct tegra_clk_pll *pll;
  2120. unsigned long parent_rate;
  2121. if (!p_tohw)
  2122. return ERR_PTR(-EINVAL);
  2123. parent = __clk_lookup(parent_name);
  2124. if (!parent) {
  2125. WARN(1, "parent clk %s of %s must be registered first\n",
  2126. name, parent_name);
  2127. return ERR_PTR(-EINVAL);
  2128. }
  2129. parent_rate = clk_get_rate(parent);
  2130. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  2131. if (pll_params->adjust_vco)
  2132. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  2133. parent_rate);
  2134. pll_params->flags |= TEGRA_PLL_BYPASS;
  2135. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  2136. if (IS_ERR(pll))
  2137. return ERR_CAST(pll);
  2138. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  2139. &tegra_clk_pll_ops);
  2140. if (IS_ERR(clk))
  2141. kfree(pll);
  2142. return clk;
  2143. }
  2144. struct clk *tegra_clk_register_pllss_tegra210(const char *name,
  2145. const char *parent_name, void __iomem *clk_base,
  2146. unsigned long flags,
  2147. struct tegra_clk_pll_params *pll_params,
  2148. spinlock_t *lock)
  2149. {
  2150. struct tegra_clk_pll *pll;
  2151. struct clk *clk, *parent;
  2152. unsigned long parent_rate;
  2153. u32 val;
  2154. if (!pll_params->div_nmp)
  2155. return ERR_PTR(-EINVAL);
  2156. parent = __clk_lookup(parent_name);
  2157. if (!parent) {
  2158. WARN(1, "parent clk %s of %s must be registered first\n",
  2159. name, parent_name);
  2160. return ERR_PTR(-EINVAL);
  2161. }
  2162. val = readl_relaxed(clk_base + pll_params->base_reg);
  2163. if (val & PLLSS_REF_SRC_SEL_MASK) {
  2164. WARN(1, "not supported reference clock for %s\n", name);
  2165. return ERR_PTR(-EINVAL);
  2166. }
  2167. parent_rate = clk_get_rate(parent);
  2168. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  2169. if (pll_params->adjust_vco)
  2170. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  2171. parent_rate);
  2172. pll_params->flags |= TEGRA_PLL_BYPASS;
  2173. pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
  2174. if (IS_ERR(pll))
  2175. return ERR_CAST(pll);
  2176. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  2177. &tegra_clk_pll_ops);
  2178. if (IS_ERR(clk))
  2179. kfree(pll);
  2180. return clk;
  2181. }
  2182. struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
  2183. void __iomem *clk_base, void __iomem *pmc,
  2184. unsigned long flags,
  2185. struct tegra_clk_pll_params *pll_params,
  2186. spinlock_t *lock)
  2187. {
  2188. struct tegra_clk_pll *pll;
  2189. struct clk *clk, *parent;
  2190. unsigned long parent_rate;
  2191. if (!pll_params->pdiv_tohw)
  2192. return ERR_PTR(-EINVAL);
  2193. parent = __clk_lookup(parent_name);
  2194. if (!parent) {
  2195. WARN(1, "parent clk %s of %s must be registered first\n",
  2196. parent_name, name);
  2197. return ERR_PTR(-EINVAL);
  2198. }
  2199. parent_rate = clk_get_rate(parent);
  2200. pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
  2201. if (pll_params->adjust_vco)
  2202. pll_params->vco_min = pll_params->adjust_vco(pll_params,
  2203. parent_rate);
  2204. pll_params->flags |= TEGRA_PLL_BYPASS;
  2205. pll_params->flags |= TEGRA_PLLMB;
  2206. pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
  2207. if (IS_ERR(pll))
  2208. return ERR_CAST(pll);
  2209. clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
  2210. &tegra_clk_pll_ops);
  2211. if (IS_ERR(clk))
  2212. kfree(pll);
  2213. return clk;
  2214. }
  2215. #endif