clk-divider.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/io.h>
  7. #include <linux/err.h>
  8. #include <linux/slab.h>
  9. #include <linux/clk-provider.h>
  10. #include "clk.h"
  11. #define pll_out_override(p) (BIT((p->shift - 6)))
  12. #define div_mask(d) ((1 << (d->width)) - 1)
  13. #define get_mul(d) (1 << d->frac_width)
  14. #define get_max_div(d) div_mask(d)
  15. #define PERIPH_CLK_UART_DIV_ENB BIT(24)
  16. static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
  17. unsigned long parent_rate)
  18. {
  19. int div;
  20. div = div_frac_get(rate, parent_rate, divider->width,
  21. divider->frac_width, divider->flags);
  22. if (div < 0)
  23. return 0;
  24. return div;
  25. }
  26. static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
  27. unsigned long parent_rate)
  28. {
  29. struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
  30. u32 reg;
  31. int div, mul;
  32. u64 rate = parent_rate;
  33. reg = readl_relaxed(divider->reg);
  34. if ((divider->flags & TEGRA_DIVIDER_UART) &&
  35. !(reg & PERIPH_CLK_UART_DIV_ENB))
  36. return rate;
  37. div = (reg >> divider->shift) & div_mask(divider);
  38. mul = get_mul(divider);
  39. div += mul;
  40. rate *= mul;
  41. rate += div - 1;
  42. do_div(rate, div);
  43. return rate;
  44. }
  45. static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
  46. unsigned long *prate)
  47. {
  48. struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
  49. int div, mul;
  50. unsigned long output_rate = *prate;
  51. if (!rate)
  52. return output_rate;
  53. div = get_div(divider, rate, output_rate);
  54. if (div < 0)
  55. return *prate;
  56. mul = get_mul(divider);
  57. return DIV_ROUND_UP(output_rate * mul, div + mul);
  58. }
  59. static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
  60. unsigned long parent_rate)
  61. {
  62. struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
  63. int div;
  64. unsigned long flags = 0;
  65. u32 val;
  66. div = get_div(divider, rate, parent_rate);
  67. if (div < 0)
  68. return div;
  69. if (divider->lock)
  70. spin_lock_irqsave(divider->lock, flags);
  71. val = readl_relaxed(divider->reg);
  72. val &= ~(div_mask(divider) << divider->shift);
  73. val |= div << divider->shift;
  74. if (divider->flags & TEGRA_DIVIDER_UART) {
  75. if (div)
  76. val |= PERIPH_CLK_UART_DIV_ENB;
  77. else
  78. val &= ~PERIPH_CLK_UART_DIV_ENB;
  79. }
  80. if (divider->flags & TEGRA_DIVIDER_FIXED)
  81. val |= pll_out_override(divider);
  82. writel_relaxed(val, divider->reg);
  83. if (divider->lock)
  84. spin_unlock_irqrestore(divider->lock, flags);
  85. return 0;
  86. }
  87. static void clk_divider_restore_context(struct clk_hw *hw)
  88. {
  89. struct clk_hw *parent = clk_hw_get_parent(hw);
  90. unsigned long parent_rate = clk_hw_get_rate(parent);
  91. unsigned long rate = clk_hw_get_rate(hw);
  92. if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
  93. WARN_ON(1);
  94. }
  95. const struct clk_ops tegra_clk_frac_div_ops = {
  96. .recalc_rate = clk_frac_div_recalc_rate,
  97. .set_rate = clk_frac_div_set_rate,
  98. .round_rate = clk_frac_div_round_rate,
  99. .restore_context = clk_divider_restore_context,
  100. };
  101. struct clk *tegra_clk_register_divider(const char *name,
  102. const char *parent_name, void __iomem *reg,
  103. unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
  104. u8 frac_width, spinlock_t *lock)
  105. {
  106. struct tegra_clk_frac_div *divider;
  107. struct clk *clk;
  108. struct clk_init_data init;
  109. divider = kzalloc(sizeof(*divider), GFP_KERNEL);
  110. if (!divider) {
  111. pr_err("%s: could not allocate fractional divider clk\n",
  112. __func__);
  113. return ERR_PTR(-ENOMEM);
  114. }
  115. init.name = name;
  116. init.ops = &tegra_clk_frac_div_ops;
  117. init.flags = flags;
  118. init.parent_names = parent_name ? &parent_name : NULL;
  119. init.num_parents = parent_name ? 1 : 0;
  120. divider->reg = reg;
  121. divider->shift = shift;
  122. divider->width = width;
  123. divider->frac_width = frac_width;
  124. divider->lock = lock;
  125. divider->flags = clk_divider_flags;
  126. /* Data in .init is copied by clk_register(), so stack variable OK */
  127. divider->hw.init = &init;
  128. clk = clk_register(NULL, &divider->hw);
  129. if (IS_ERR(clk))
  130. kfree(divider);
  131. return clk;
  132. }
  133. static const struct clk_div_table mc_div_table[] = {
  134. { .val = 0, .div = 2 },
  135. { .val = 1, .div = 1 },
  136. { .val = 0, .div = 0 },
  137. };
  138. struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
  139. void __iomem *reg, spinlock_t *lock)
  140. {
  141. return clk_register_divider_table(NULL, name, parent_name,
  142. CLK_IS_CRITICAL,
  143. reg, 16, 1, CLK_DIVIDER_READ_ONLY,
  144. mc_div_table, lock);
  145. }