clk-dfll.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
  4. * Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved.
  5. *
  6. * Aleksandr Frid <afrid@nvidia.com>
  7. * Paul Walmsley <pwalmsley@nvidia.com>
  8. */
  9. #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
  10. #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <linux/types.h>
  14. #include "cvb.h"
  15. /**
  16. * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
  17. * @dev: struct device * that holds the OPP table for the DFLL
  18. * @max_freq: maximum frequency supported on this SoC
  19. * @cvb: CPU frequency table for this SoC
  20. * @alignment: parameters of the regulator step and offset
  21. * @init_clock_trimmers: callback to initialize clock trimmers
  22. * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
  23. * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
  24. */
  25. struct tegra_dfll_soc_data {
  26. struct device *dev;
  27. unsigned long max_freq;
  28. const struct cvb_table *cvb;
  29. struct rail_alignment alignment;
  30. void (*init_clock_trimmers)(void);
  31. void (*set_clock_trimmers_high)(void);
  32. void (*set_clock_trimmers_low)(void);
  33. };
  34. int tegra_dfll_register(struct platform_device *pdev,
  35. struct tegra_dfll_soc_data *soc);
  36. struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
  37. int tegra_dfll_runtime_suspend(struct device *dev);
  38. int tegra_dfll_runtime_resume(struct device *dev);
  39. int tegra_dfll_suspend(struct device *dev);
  40. int tegra_dfll_resume(struct device *dev);
  41. #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */