clkgen-pll.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2014 STMicroelectronics (R&D) Limited
  4. */
  5. /*
  6. * Authors:
  7. * Stephen Gallimore <stephen.gallimore@st.com>,
  8. * Pankaj Dev <pankaj.dev@st.com>.
  9. */
  10. #include <linux/slab.h>
  11. #include <linux/of_address.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/iopoll.h>
  15. #include "clkgen.h"
  16. static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
  17. DEFINE_SPINLOCK(clkgen_a9_lock);
  18. /*
  19. * PLL configuration register bits for PLL3200 C32
  20. */
  21. #define C32_NDIV_MASK (0xff)
  22. #define C32_IDF_MASK (0x7)
  23. #define C32_ODF_MASK (0x3f)
  24. #define C32_LDF_MASK (0x7f)
  25. #define C32_CP_MASK (0x1f)
  26. #define C32_MAX_ODFS (4)
  27. /*
  28. * PLL configuration register bits for PLL4600 C28
  29. */
  30. #define C28_NDIV_MASK (0xff)
  31. #define C28_IDF_MASK (0x7)
  32. #define C28_ODF_MASK (0x3f)
  33. struct clkgen_pll_data {
  34. struct clkgen_field pdn_status;
  35. struct clkgen_field pdn_ctrl;
  36. struct clkgen_field locked_status;
  37. struct clkgen_field mdiv;
  38. struct clkgen_field ndiv;
  39. struct clkgen_field pdiv;
  40. struct clkgen_field idf;
  41. struct clkgen_field ldf;
  42. struct clkgen_field cp;
  43. unsigned int num_odfs;
  44. struct clkgen_field odf[C32_MAX_ODFS];
  45. struct clkgen_field odf_gate[C32_MAX_ODFS];
  46. bool switch2pll_en;
  47. struct clkgen_field switch2pll;
  48. spinlock_t *lock;
  49. const struct clk_ops *ops;
  50. };
  51. static const struct clk_ops stm_pll3200c32_ops;
  52. static const struct clk_ops stm_pll3200c32_a9_ops;
  53. static const struct clk_ops stm_pll4600c28_ops;
  54. static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
  55. /* 407 C0 PLL0 */
  56. .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
  57. .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
  58. .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
  59. .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
  60. .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
  61. .num_odfs = 1,
  62. .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
  63. .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
  64. .ops = &stm_pll3200c32_ops,
  65. };
  66. static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
  67. /* 407 C0 PLL1 */
  68. .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
  69. .pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8),
  70. .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
  71. .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
  72. .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
  73. .num_odfs = 1,
  74. .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
  75. .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
  76. .ops = &stm_pll3200c32_ops,
  77. };
  78. static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
  79. /* 407 A9 */
  80. .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
  81. .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
  82. .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
  83. .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
  84. .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
  85. .num_odfs = 1,
  86. .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
  87. .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
  88. .switch2pll_en = true,
  89. .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
  90. .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
  91. .lock = &clkgen_a9_lock,
  92. .ops = &stm_pll3200c32_a9_ops,
  93. };
  94. static struct clkgen_pll_data st_pll4600c28_418_a9 = {
  95. /* 418 A9 */
  96. .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
  97. .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
  98. .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
  99. .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
  100. .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
  101. .num_odfs = 1,
  102. .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
  103. .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
  104. .switch2pll_en = true,
  105. .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
  106. .lock = &clkgen_a9_lock,
  107. .ops = &stm_pll4600c28_ops,
  108. };
  109. /**
  110. * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  111. *
  112. * Traits of this clock:
  113. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  114. * enable - clk_enable/disable only ensures parent is enabled
  115. * rate - rate is fixed. No clk_set_rate support
  116. * parent - fixed parent. No clk_set_parent support
  117. */
  118. /**
  119. * PLL clock that is integrated in the ClockGenA instances on the STiH415
  120. * and STiH416.
  121. *
  122. * @hw: handle between common and hardware-specific interfaces.
  123. * @type: PLL instance type.
  124. * @regs_base: base of the PLL configuration register(s).
  125. *
  126. */
  127. struct clkgen_pll {
  128. struct clk_hw hw;
  129. struct clkgen_pll_data *data;
  130. void __iomem *regs_base;
  131. spinlock_t *lock;
  132. u32 ndiv;
  133. u32 idf;
  134. u32 odf;
  135. u32 cp;
  136. };
  137. #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
  138. struct stm_pll {
  139. unsigned long mdiv;
  140. unsigned long ndiv;
  141. unsigned long pdiv;
  142. unsigned long odf;
  143. unsigned long idf;
  144. unsigned long ldf;
  145. unsigned long cp;
  146. };
  147. static int clkgen_pll_is_locked(struct clk_hw *hw)
  148. {
  149. struct clkgen_pll *pll = to_clkgen_pll(hw);
  150. u32 locked = CLKGEN_READ(pll, locked_status);
  151. return !!locked;
  152. }
  153. static int clkgen_pll_is_enabled(struct clk_hw *hw)
  154. {
  155. struct clkgen_pll *pll = to_clkgen_pll(hw);
  156. u32 poweroff = CLKGEN_READ(pll, pdn_status);
  157. return !poweroff;
  158. }
  159. static int __clkgen_pll_enable(struct clk_hw *hw)
  160. {
  161. struct clkgen_pll *pll = to_clkgen_pll(hw);
  162. void __iomem *base = pll->regs_base;
  163. struct clkgen_field *field = &pll->data->locked_status;
  164. int ret = 0;
  165. u32 reg;
  166. if (clkgen_pll_is_enabled(hw))
  167. return 0;
  168. CLKGEN_WRITE(pll, pdn_ctrl, 0);
  169. ret = readl_relaxed_poll_timeout(base + field->offset, reg,
  170. !!((reg >> field->shift) & field->mask), 0, 10000);
  171. if (!ret) {
  172. if (pll->data->switch2pll_en)
  173. CLKGEN_WRITE(pll, switch2pll, 0);
  174. pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
  175. }
  176. return ret;
  177. }
  178. static int clkgen_pll_enable(struct clk_hw *hw)
  179. {
  180. struct clkgen_pll *pll = to_clkgen_pll(hw);
  181. unsigned long flags = 0;
  182. int ret = 0;
  183. if (pll->lock)
  184. spin_lock_irqsave(pll->lock, flags);
  185. ret = __clkgen_pll_enable(hw);
  186. if (pll->lock)
  187. spin_unlock_irqrestore(pll->lock, flags);
  188. return ret;
  189. }
  190. static void __clkgen_pll_disable(struct clk_hw *hw)
  191. {
  192. struct clkgen_pll *pll = to_clkgen_pll(hw);
  193. if (!clkgen_pll_is_enabled(hw))
  194. return;
  195. if (pll->data->switch2pll_en)
  196. CLKGEN_WRITE(pll, switch2pll, 1);
  197. CLKGEN_WRITE(pll, pdn_ctrl, 1);
  198. pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
  199. }
  200. static void clkgen_pll_disable(struct clk_hw *hw)
  201. {
  202. struct clkgen_pll *pll = to_clkgen_pll(hw);
  203. unsigned long flags = 0;
  204. if (pll->lock)
  205. spin_lock_irqsave(pll->lock, flags);
  206. __clkgen_pll_disable(hw);
  207. if (pll->lock)
  208. spin_unlock_irqrestore(pll->lock, flags);
  209. }
  210. static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
  211. struct stm_pll *pll)
  212. {
  213. unsigned long i, n;
  214. unsigned long deviation = ~0;
  215. unsigned long new_freq;
  216. long new_deviation;
  217. /* Charge pump table: highest ndiv value for cp=6 to 25 */
  218. static const unsigned char cp_table[] = {
  219. 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
  220. 128, 136, 144, 152, 160, 168, 176, 184, 192
  221. };
  222. /* Output clock range: 800Mhz to 1600Mhz */
  223. if (output < 800000000 || output > 1600000000)
  224. return -EINVAL;
  225. input /= 1000;
  226. output /= 1000;
  227. for (i = 1; i <= 7 && deviation; i++) {
  228. n = i * output / (2 * input);
  229. /* Checks */
  230. if (n < 8)
  231. continue;
  232. if (n > 200)
  233. break;
  234. new_freq = (input * 2 * n) / i;
  235. new_deviation = abs(new_freq - output);
  236. if (!new_deviation || new_deviation < deviation) {
  237. pll->idf = i;
  238. pll->ndiv = n;
  239. deviation = new_deviation;
  240. }
  241. }
  242. if (deviation == ~0) /* No solution found */
  243. return -EINVAL;
  244. /* Computing recommended charge pump value */
  245. for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
  246. ;
  247. return 0;
  248. }
  249. static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
  250. unsigned long *rate)
  251. {
  252. if (!pll->idf)
  253. pll->idf = 1;
  254. *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
  255. return 0;
  256. }
  257. static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
  258. unsigned long parent_rate)
  259. {
  260. struct clkgen_pll *pll = to_clkgen_pll(hw);
  261. unsigned long ndiv, idf;
  262. unsigned long rate = 0;
  263. if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
  264. return 0;
  265. ndiv = CLKGEN_READ(pll, ndiv);
  266. idf = CLKGEN_READ(pll, idf);
  267. if (idf)
  268. /* Note: input is divided to avoid overflow */
  269. rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
  270. pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
  271. return rate;
  272. }
  273. static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
  274. unsigned long *prate)
  275. {
  276. struct stm_pll params;
  277. if (!clk_pll3200c32_get_params(*prate, rate, &params))
  278. clk_pll3200c32_get_rate(*prate, &params, &rate);
  279. else {
  280. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  281. __clk_get_name(hw->clk), rate);
  282. return 0;
  283. }
  284. pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
  285. __func__, __clk_get_name(hw->clk),
  286. rate, (unsigned int)params.ndiv,
  287. (unsigned int)params.idf);
  288. return rate;
  289. }
  290. static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
  291. unsigned long parent_rate)
  292. {
  293. struct clkgen_pll *pll = to_clkgen_pll(hw);
  294. struct stm_pll params;
  295. long hwrate = 0;
  296. unsigned long flags = 0;
  297. if (!rate || !parent_rate)
  298. return -EINVAL;
  299. if (!clk_pll3200c32_get_params(parent_rate, rate, &params))
  300. clk_pll3200c32_get_rate(parent_rate, &params, &hwrate);
  301. pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
  302. __func__, __clk_get_name(hw->clk),
  303. hwrate, (unsigned int)params.ndiv,
  304. (unsigned int)params.idf);
  305. if (!hwrate)
  306. return -EINVAL;
  307. pll->ndiv = params.ndiv;
  308. pll->idf = params.idf;
  309. pll->cp = params.cp;
  310. __clkgen_pll_disable(hw);
  311. if (pll->lock)
  312. spin_lock_irqsave(pll->lock, flags);
  313. CLKGEN_WRITE(pll, ndiv, pll->ndiv);
  314. CLKGEN_WRITE(pll, idf, pll->idf);
  315. CLKGEN_WRITE(pll, cp, pll->cp);
  316. if (pll->lock)
  317. spin_unlock_irqrestore(pll->lock, flags);
  318. __clkgen_pll_enable(hw);
  319. return 0;
  320. }
  321. /* PLL output structure
  322. * FVCO >> /2 >> FVCOBY2 (no output)
  323. * |> Divider (ODF) >> PHI
  324. *
  325. * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
  326. *
  327. * Rules:
  328. * 4Mhz <= INFF input <= 350Mhz
  329. * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
  330. * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
  331. * 1 <= i (register/dec value for IDF) <= 7
  332. * 8 <= n (register/dec value for NDIV) <= 246
  333. */
  334. static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
  335. struct stm_pll *pll)
  336. {
  337. unsigned long i, infin, n;
  338. unsigned long deviation = ~0;
  339. unsigned long new_freq, new_deviation;
  340. /* Output clock range: 19Mhz to 3000Mhz */
  341. if (output < 19000000 || output > 3000000000u)
  342. return -EINVAL;
  343. /* For better jitter, IDF should be smallest and NDIV must be maximum */
  344. for (i = 1; i <= 7 && deviation; i++) {
  345. /* INFIN checks */
  346. infin = input / i;
  347. if (infin < 4000000 || infin > 50000000)
  348. continue; /* Invalid case */
  349. n = output / (infin * 2);
  350. if (n < 8 || n > 246)
  351. continue; /* Invalid case */
  352. if (n < 246)
  353. n++; /* To work around 'y' when n=x.y */
  354. for (; n >= 8 && deviation; n--) {
  355. new_freq = infin * 2 * n;
  356. if (new_freq < output)
  357. break; /* Optimization: shorting loop */
  358. new_deviation = new_freq - output;
  359. if (!new_deviation || new_deviation < deviation) {
  360. pll->idf = i;
  361. pll->ndiv = n;
  362. deviation = new_deviation;
  363. }
  364. }
  365. }
  366. if (deviation == ~0) /* No solution found */
  367. return -EINVAL;
  368. return 0;
  369. }
  370. static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
  371. unsigned long *rate)
  372. {
  373. if (!pll->idf)
  374. pll->idf = 1;
  375. *rate = (input / pll->idf) * 2 * pll->ndiv;
  376. return 0;
  377. }
  378. static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
  379. unsigned long parent_rate)
  380. {
  381. struct clkgen_pll *pll = to_clkgen_pll(hw);
  382. struct stm_pll params;
  383. unsigned long rate;
  384. if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
  385. return 0;
  386. params.ndiv = CLKGEN_READ(pll, ndiv);
  387. params.idf = CLKGEN_READ(pll, idf);
  388. clk_pll4600c28_get_rate(parent_rate, &params, &rate);
  389. pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
  390. return rate;
  391. }
  392. static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
  393. unsigned long *prate)
  394. {
  395. struct stm_pll params;
  396. if (!clk_pll4600c28_get_params(*prate, rate, &params)) {
  397. clk_pll4600c28_get_rate(*prate, &params, &rate);
  398. } else {
  399. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  400. __clk_get_name(hw->clk), rate);
  401. return 0;
  402. }
  403. pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
  404. __func__, __clk_get_name(hw->clk),
  405. rate, (unsigned int)params.ndiv,
  406. (unsigned int)params.idf);
  407. return rate;
  408. }
  409. static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
  410. unsigned long parent_rate)
  411. {
  412. struct clkgen_pll *pll = to_clkgen_pll(hw);
  413. struct stm_pll params;
  414. long hwrate;
  415. unsigned long flags = 0;
  416. if (!rate || !parent_rate)
  417. return -EINVAL;
  418. if (!clk_pll4600c28_get_params(parent_rate, rate, &params)) {
  419. clk_pll4600c28_get_rate(parent_rate, &params, &hwrate);
  420. } else {
  421. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  422. __clk_get_name(hw->clk), rate);
  423. return -EINVAL;
  424. }
  425. pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
  426. __func__, __clk_get_name(hw->clk),
  427. hwrate, (unsigned int)params.ndiv,
  428. (unsigned int)params.idf);
  429. if (!hwrate)
  430. return -EINVAL;
  431. pll->ndiv = params.ndiv;
  432. pll->idf = params.idf;
  433. __clkgen_pll_disable(hw);
  434. if (pll->lock)
  435. spin_lock_irqsave(pll->lock, flags);
  436. CLKGEN_WRITE(pll, ndiv, pll->ndiv);
  437. CLKGEN_WRITE(pll, idf, pll->idf);
  438. if (pll->lock)
  439. spin_unlock_irqrestore(pll->lock, flags);
  440. __clkgen_pll_enable(hw);
  441. return 0;
  442. }
  443. static const struct clk_ops stm_pll3200c32_ops = {
  444. .enable = clkgen_pll_enable,
  445. .disable = clkgen_pll_disable,
  446. .is_enabled = clkgen_pll_is_enabled,
  447. .recalc_rate = recalc_stm_pll3200c32,
  448. };
  449. static const struct clk_ops stm_pll3200c32_a9_ops = {
  450. .enable = clkgen_pll_enable,
  451. .disable = clkgen_pll_disable,
  452. .is_enabled = clkgen_pll_is_enabled,
  453. .recalc_rate = recalc_stm_pll3200c32,
  454. .round_rate = round_rate_stm_pll3200c32,
  455. .set_rate = set_rate_stm_pll3200c32,
  456. };
  457. static const struct clk_ops stm_pll4600c28_ops = {
  458. .enable = clkgen_pll_enable,
  459. .disable = clkgen_pll_disable,
  460. .is_enabled = clkgen_pll_is_enabled,
  461. .recalc_rate = recalc_stm_pll4600c28,
  462. .round_rate = round_rate_stm_pll4600c28,
  463. .set_rate = set_rate_stm_pll4600c28,
  464. };
  465. static struct clk * __init clkgen_pll_register(const char *parent_name,
  466. struct clkgen_pll_data *pll_data,
  467. void __iomem *reg, unsigned long pll_flags,
  468. const char *clk_name, spinlock_t *lock)
  469. {
  470. struct clkgen_pll *pll;
  471. struct clk *clk;
  472. struct clk_init_data init;
  473. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  474. if (!pll)
  475. return ERR_PTR(-ENOMEM);
  476. init.name = clk_name;
  477. init.ops = pll_data->ops;
  478. init.flags = pll_flags | CLK_GET_RATE_NOCACHE;
  479. init.parent_names = &parent_name;
  480. init.num_parents = 1;
  481. pll->data = pll_data;
  482. pll->regs_base = reg;
  483. pll->hw.init = &init;
  484. pll->lock = lock;
  485. clk = clk_register(NULL, &pll->hw);
  486. if (IS_ERR(clk)) {
  487. kfree(pll);
  488. return clk;
  489. }
  490. pr_debug("%s: parent %s rate %lu\n",
  491. __clk_get_name(clk),
  492. __clk_get_name(clk_get_parent(clk)),
  493. clk_get_rate(clk));
  494. return clk;
  495. }
  496. static void __iomem * __init clkgen_get_register_base(
  497. struct device_node *np)
  498. {
  499. struct device_node *pnode;
  500. void __iomem *reg = NULL;
  501. pnode = of_get_parent(np);
  502. if (!pnode)
  503. return NULL;
  504. reg = of_iomap(pnode, 0);
  505. of_node_put(pnode);
  506. return reg;
  507. }
  508. static struct clk * __init clkgen_odf_register(const char *parent_name,
  509. void __iomem *reg,
  510. struct clkgen_pll_data *pll_data,
  511. unsigned long pll_flags, int odf,
  512. spinlock_t *odf_lock,
  513. const char *odf_name)
  514. {
  515. struct clk *clk;
  516. unsigned long flags;
  517. struct clk_gate *gate;
  518. struct clk_divider *div;
  519. flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
  520. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  521. if (!gate)
  522. return ERR_PTR(-ENOMEM);
  523. gate->flags = CLK_GATE_SET_TO_DISABLE;
  524. gate->reg = reg + pll_data->odf_gate[odf].offset;
  525. gate->bit_idx = pll_data->odf_gate[odf].shift;
  526. gate->lock = odf_lock;
  527. div = kzalloc(sizeof(*div), GFP_KERNEL);
  528. if (!div) {
  529. kfree(gate);
  530. return ERR_PTR(-ENOMEM);
  531. }
  532. div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
  533. div->reg = reg + pll_data->odf[odf].offset;
  534. div->shift = pll_data->odf[odf].shift;
  535. div->width = fls(pll_data->odf[odf].mask);
  536. div->lock = odf_lock;
  537. clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
  538. NULL, NULL,
  539. &div->hw, &clk_divider_ops,
  540. &gate->hw, &clk_gate_ops,
  541. flags);
  542. if (IS_ERR(clk))
  543. return clk;
  544. pr_debug("%s: parent %s rate %lu\n",
  545. __clk_get_name(clk),
  546. __clk_get_name(clk_get_parent(clk)),
  547. clk_get_rate(clk));
  548. return clk;
  549. }
  550. static void __init clkgen_c32_pll_setup(struct device_node *np,
  551. struct clkgen_pll_data *data)
  552. {
  553. struct clk *clk;
  554. const char *parent_name, *pll_name;
  555. void __iomem *pll_base;
  556. int num_odfs, odf;
  557. struct clk_onecell_data *clk_data;
  558. unsigned long pll_flags = 0;
  559. parent_name = of_clk_get_parent_name(np, 0);
  560. if (!parent_name)
  561. return;
  562. pll_base = clkgen_get_register_base(np);
  563. if (!pll_base)
  564. return;
  565. of_clk_detect_critical(np, 0, &pll_flags);
  566. clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
  567. np->name, data->lock);
  568. if (IS_ERR(clk))
  569. return;
  570. pll_name = __clk_get_name(clk);
  571. num_odfs = data->num_odfs;
  572. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  573. if (!clk_data)
  574. return;
  575. clk_data->clk_num = num_odfs;
  576. clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
  577. GFP_KERNEL);
  578. if (!clk_data->clks)
  579. goto err;
  580. for (odf = 0; odf < num_odfs; odf++) {
  581. struct clk *clk;
  582. const char *clk_name;
  583. unsigned long odf_flags = 0;
  584. if (of_property_read_string_index(np, "clock-output-names",
  585. odf, &clk_name))
  586. return;
  587. of_clk_detect_critical(np, odf, &odf_flags);
  588. clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
  589. odf, &clkgena_c32_odf_lock, clk_name);
  590. if (IS_ERR(clk))
  591. goto err;
  592. clk_data->clks[odf] = clk;
  593. }
  594. of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  595. return;
  596. err:
  597. kfree(pll_name);
  598. kfree(clk_data->clks);
  599. kfree(clk_data);
  600. }
  601. static void __init clkgen_c32_pll0_setup(struct device_node *np)
  602. {
  603. clkgen_c32_pll_setup(np,
  604. (struct clkgen_pll_data *) &st_pll3200c32_cx_0);
  605. }
  606. CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
  607. static void __init clkgen_c32_pll1_setup(struct device_node *np)
  608. {
  609. clkgen_c32_pll_setup(np,
  610. (struct clkgen_pll_data *) &st_pll3200c32_cx_1);
  611. }
  612. CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
  613. static void __init clkgen_c32_plla9_setup(struct device_node *np)
  614. {
  615. clkgen_c32_pll_setup(np,
  616. (struct clkgen_pll_data *) &st_pll3200c32_407_a9);
  617. }
  618. CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
  619. static void __init clkgen_c28_plla9_setup(struct device_node *np)
  620. {
  621. clkgen_c32_pll_setup(np,
  622. (struct clkgen_pll_data *) &st_pll4600c28_418_a9);
  623. }
  624. CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);