clk-flexgen.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * clk-flexgen.c
  4. *
  5. * Copyright (C) ST-Microelectronics SA 2013
  6. * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/module.h>
  11. #include <linux/slab.h>
  12. #include <linux/io.h>
  13. #include <linux/err.h>
  14. #include <linux/string.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. struct clkgen_data {
  18. unsigned long flags;
  19. bool mode;
  20. };
  21. struct flexgen {
  22. struct clk_hw hw;
  23. /* Crossbar */
  24. struct clk_mux mux;
  25. /* Pre-divisor's gate */
  26. struct clk_gate pgate;
  27. /* Pre-divisor */
  28. struct clk_divider pdiv;
  29. /* Final divisor's gate */
  30. struct clk_gate fgate;
  31. /* Final divisor */
  32. struct clk_divider fdiv;
  33. /* Asynchronous mode control */
  34. struct clk_gate sync;
  35. /* hw control flags */
  36. bool control_mode;
  37. };
  38. #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
  39. #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
  40. static int flexgen_enable(struct clk_hw *hw)
  41. {
  42. struct flexgen *flexgen = to_flexgen(hw);
  43. struct clk_hw *pgate_hw = &flexgen->pgate.hw;
  44. struct clk_hw *fgate_hw = &flexgen->fgate.hw;
  45. __clk_hw_set_clk(pgate_hw, hw);
  46. __clk_hw_set_clk(fgate_hw, hw);
  47. clk_gate_ops.enable(pgate_hw);
  48. clk_gate_ops.enable(fgate_hw);
  49. pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw));
  50. return 0;
  51. }
  52. static void flexgen_disable(struct clk_hw *hw)
  53. {
  54. struct flexgen *flexgen = to_flexgen(hw);
  55. struct clk_hw *fgate_hw = &flexgen->fgate.hw;
  56. /* disable only the final gate */
  57. __clk_hw_set_clk(fgate_hw, hw);
  58. clk_gate_ops.disable(fgate_hw);
  59. pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw));
  60. }
  61. static int flexgen_is_enabled(struct clk_hw *hw)
  62. {
  63. struct flexgen *flexgen = to_flexgen(hw);
  64. struct clk_hw *fgate_hw = &flexgen->fgate.hw;
  65. __clk_hw_set_clk(fgate_hw, hw);
  66. if (!clk_gate_ops.is_enabled(fgate_hw))
  67. return 0;
  68. return 1;
  69. }
  70. static u8 flexgen_get_parent(struct clk_hw *hw)
  71. {
  72. struct flexgen *flexgen = to_flexgen(hw);
  73. struct clk_hw *mux_hw = &flexgen->mux.hw;
  74. __clk_hw_set_clk(mux_hw, hw);
  75. return clk_mux_ops.get_parent(mux_hw);
  76. }
  77. static int flexgen_set_parent(struct clk_hw *hw, u8 index)
  78. {
  79. struct flexgen *flexgen = to_flexgen(hw);
  80. struct clk_hw *mux_hw = &flexgen->mux.hw;
  81. __clk_hw_set_clk(mux_hw, hw);
  82. return clk_mux_ops.set_parent(mux_hw, index);
  83. }
  84. static inline unsigned long
  85. clk_best_div(unsigned long parent_rate, unsigned long rate)
  86. {
  87. return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
  88. }
  89. static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
  90. unsigned long *prate)
  91. {
  92. unsigned long div;
  93. /* Round div according to exact prate and wished rate */
  94. div = clk_best_div(*prate, rate);
  95. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  96. *prate = rate * div;
  97. return rate;
  98. }
  99. return *prate / div;
  100. }
  101. static unsigned long flexgen_recalc_rate(struct clk_hw *hw,
  102. unsigned long parent_rate)
  103. {
  104. struct flexgen *flexgen = to_flexgen(hw);
  105. struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
  106. struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
  107. unsigned long mid_rate;
  108. __clk_hw_set_clk(pdiv_hw, hw);
  109. __clk_hw_set_clk(fdiv_hw, hw);
  110. mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
  111. return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
  112. }
  113. static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
  114. unsigned long parent_rate)
  115. {
  116. struct flexgen *flexgen = to_flexgen(hw);
  117. struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
  118. struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
  119. struct clk_hw *sync_hw = &flexgen->sync.hw;
  120. struct clk_gate *config = to_clk_gate(sync_hw);
  121. unsigned long div = 0;
  122. int ret = 0;
  123. u32 reg;
  124. __clk_hw_set_clk(pdiv_hw, hw);
  125. __clk_hw_set_clk(fdiv_hw, hw);
  126. if (flexgen->control_mode) {
  127. reg = readl(config->reg);
  128. reg &= ~BIT(config->bit_idx);
  129. writel(reg, config->reg);
  130. }
  131. div = clk_best_div(parent_rate, rate);
  132. /*
  133. * pdiv is mainly targeted for low freq results, while fdiv
  134. * should be used for div <= 64. The other way round can
  135. * lead to 'duty cycle' issues.
  136. */
  137. if (div <= 64) {
  138. clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
  139. ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
  140. } else {
  141. clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
  142. ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
  143. }
  144. return ret;
  145. }
  146. static const struct clk_ops flexgen_ops = {
  147. .enable = flexgen_enable,
  148. .disable = flexgen_disable,
  149. .is_enabled = flexgen_is_enabled,
  150. .get_parent = flexgen_get_parent,
  151. .set_parent = flexgen_set_parent,
  152. .round_rate = flexgen_round_rate,
  153. .recalc_rate = flexgen_recalc_rate,
  154. .set_rate = flexgen_set_rate,
  155. };
  156. static struct clk *clk_register_flexgen(const char *name,
  157. const char **parent_names, u8 num_parents,
  158. void __iomem *reg, spinlock_t *lock, u32 idx,
  159. unsigned long flexgen_flags, bool mode) {
  160. struct flexgen *fgxbar;
  161. struct clk *clk;
  162. struct clk_init_data init;
  163. u32 xbar_shift;
  164. void __iomem *xbar_reg, *fdiv_reg;
  165. fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
  166. if (!fgxbar)
  167. return ERR_PTR(-ENOMEM);
  168. init.name = name;
  169. init.ops = &flexgen_ops;
  170. init.flags = CLK_GET_RATE_NOCACHE | flexgen_flags;
  171. init.parent_names = parent_names;
  172. init.num_parents = num_parents;
  173. xbar_reg = reg + 0x18 + (idx & ~0x3);
  174. xbar_shift = (idx % 4) * 0x8;
  175. fdiv_reg = reg + 0x164 + idx * 4;
  176. /* Crossbar element config */
  177. fgxbar->mux.lock = lock;
  178. fgxbar->mux.mask = BIT(6) - 1;
  179. fgxbar->mux.reg = xbar_reg;
  180. fgxbar->mux.shift = xbar_shift;
  181. fgxbar->mux.table = NULL;
  182. /* Pre-divider's gate config (in xbar register)*/
  183. fgxbar->pgate.lock = lock;
  184. fgxbar->pgate.reg = xbar_reg;
  185. fgxbar->pgate.bit_idx = xbar_shift + 6;
  186. /* Pre-divider config */
  187. fgxbar->pdiv.lock = lock;
  188. fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
  189. fgxbar->pdiv.width = 10;
  190. /* Final divider's gate config */
  191. fgxbar->fgate.lock = lock;
  192. fgxbar->fgate.reg = fdiv_reg;
  193. fgxbar->fgate.bit_idx = 6;
  194. /* Final divider config */
  195. fgxbar->fdiv.lock = lock;
  196. fgxbar->fdiv.reg = fdiv_reg;
  197. fgxbar->fdiv.width = 6;
  198. /* Final divider sync config */
  199. fgxbar->sync.lock = lock;
  200. fgxbar->sync.reg = fdiv_reg;
  201. fgxbar->sync.bit_idx = 7;
  202. fgxbar->control_mode = mode;
  203. fgxbar->hw.init = &init;
  204. clk = clk_register(NULL, &fgxbar->hw);
  205. if (IS_ERR(clk))
  206. kfree(fgxbar);
  207. else
  208. pr_debug("%s: parent %s rate %u\n",
  209. __clk_get_name(clk),
  210. __clk_get_name(clk_get_parent(clk)),
  211. (unsigned int)clk_get_rate(clk));
  212. return clk;
  213. }
  214. static const char ** __init flexgen_get_parents(struct device_node *np,
  215. int *num_parents)
  216. {
  217. const char **parents;
  218. unsigned int nparents;
  219. nparents = of_clk_get_parent_count(np);
  220. if (WARN_ON(!nparents))
  221. return NULL;
  222. parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
  223. if (!parents)
  224. return NULL;
  225. *num_parents = of_clk_parent_fill(np, parents, nparents);
  226. return parents;
  227. }
  228. static const struct clkgen_data clkgen_audio = {
  229. .flags = CLK_SET_RATE_PARENT,
  230. };
  231. static const struct clkgen_data clkgen_video = {
  232. .flags = CLK_SET_RATE_PARENT,
  233. .mode = 1,
  234. };
  235. static const struct of_device_id flexgen_of_match[] = {
  236. {
  237. .compatible = "st,flexgen-audio",
  238. .data = &clkgen_audio,
  239. },
  240. {
  241. .compatible = "st,flexgen-video",
  242. .data = &clkgen_video,
  243. },
  244. {}
  245. };
  246. static void __init st_of_flexgen_setup(struct device_node *np)
  247. {
  248. struct device_node *pnode;
  249. void __iomem *reg;
  250. struct clk_onecell_data *clk_data;
  251. const char **parents;
  252. int num_parents, i;
  253. spinlock_t *rlock = NULL;
  254. const struct of_device_id *match;
  255. struct clkgen_data *data = NULL;
  256. unsigned long flex_flags = 0;
  257. int ret;
  258. bool clk_mode = 0;
  259. pnode = of_get_parent(np);
  260. if (!pnode)
  261. return;
  262. reg = of_iomap(pnode, 0);
  263. of_node_put(pnode);
  264. if (!reg)
  265. return;
  266. parents = flexgen_get_parents(np, &num_parents);
  267. if (!parents) {
  268. iounmap(reg);
  269. return;
  270. }
  271. match = of_match_node(flexgen_of_match, np);
  272. if (match) {
  273. data = (struct clkgen_data *)match->data;
  274. flex_flags = data->flags;
  275. clk_mode = data->mode;
  276. }
  277. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  278. if (!clk_data)
  279. goto err;
  280. ret = of_property_count_strings(np, "clock-output-names");
  281. if (ret <= 0) {
  282. pr_err("%s: Failed to get number of output clocks (%d)",
  283. __func__, clk_data->clk_num);
  284. goto err;
  285. }
  286. clk_data->clk_num = ret;
  287. clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
  288. GFP_KERNEL);
  289. if (!clk_data->clks)
  290. goto err;
  291. rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
  292. if (!rlock)
  293. goto err;
  294. spin_lock_init(rlock);
  295. for (i = 0; i < clk_data->clk_num; i++) {
  296. struct clk *clk;
  297. const char *clk_name;
  298. if (of_property_read_string_index(np, "clock-output-names",
  299. i, &clk_name)) {
  300. break;
  301. }
  302. flex_flags &= ~CLK_IS_CRITICAL;
  303. of_clk_detect_critical(np, i, &flex_flags);
  304. /*
  305. * If we read an empty clock name then the output is unused
  306. */
  307. if (*clk_name == '\0')
  308. continue;
  309. clk = clk_register_flexgen(clk_name, parents, num_parents,
  310. reg, rlock, i, flex_flags, clk_mode);
  311. if (IS_ERR(clk))
  312. goto err;
  313. clk_data->clks[i] = clk;
  314. }
  315. kfree(parents);
  316. of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  317. return;
  318. err:
  319. iounmap(reg);
  320. if (clk_data)
  321. kfree(clk_data->clks);
  322. kfree(clk_data);
  323. kfree(parents);
  324. kfree(rlock);
  325. }
  326. CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);