clk-pll-a10.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Altera Corporation. All rights reserved
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include "clk.h"
  11. /* Clock Manager offsets */
  12. #define CLK_MGR_PLL_CLK_SRC_SHIFT 8
  13. #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
  14. /* Clock bypass bits */
  15. #define SOCFPGA_PLL_BG_PWRDWN 0
  16. #define SOCFPGA_PLL_PWR_DOWN 1
  17. #define SOCFPGA_PLL_EXT_ENA 2
  18. #define SOCFPGA_PLL_DIVF_MASK 0x00001FFF
  19. #define SOCFPGA_PLL_DIVF_SHIFT 0
  20. #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
  21. #define SOCFPGA_PLL_DIVQ_SHIFT 16
  22. #define SOCFGPA_MAX_PARENTS 5
  23. #define SOCFPGA_MAIN_PLL_CLK "main_pll"
  24. #define SOCFPGA_PERIP_PLL_CLK "periph_pll"
  25. #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
  26. void __iomem *clk_mgr_a10_base_addr;
  27. static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
  28. unsigned long parent_rate)
  29. {
  30. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  31. unsigned long divf, divq, reg;
  32. unsigned long long vco_freq;
  33. /* read VCO1 reg for numerator and denominator */
  34. reg = readl(socfpgaclk->hw.reg + 0x4);
  35. divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
  36. divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
  37. vco_freq = (unsigned long long)parent_rate * (divf + 1);
  38. do_div(vco_freq, (1 + divq));
  39. return (unsigned long)vco_freq;
  40. }
  41. static u8 clk_pll_get_parent(struct clk_hw *hwclk)
  42. {
  43. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  44. u32 pll_src;
  45. pll_src = readl(socfpgaclk->hw.reg);
  46. return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
  47. CLK_MGR_PLL_CLK_SRC_MASK;
  48. }
  49. static const struct clk_ops clk_pll_ops = {
  50. .recalc_rate = clk_pll_recalc_rate,
  51. .get_parent = clk_pll_get_parent,
  52. };
  53. static struct clk * __init __socfpga_pll_init(struct device_node *node,
  54. const struct clk_ops *ops)
  55. {
  56. u32 reg;
  57. struct clk *clk;
  58. struct socfpga_pll *pll_clk;
  59. const char *clk_name = node->name;
  60. const char *parent_name[SOCFGPA_MAX_PARENTS];
  61. struct clk_init_data init;
  62. struct device_node *clkmgr_np;
  63. int rc;
  64. int i = 0;
  65. of_property_read_u32(node, "reg", &reg);
  66. pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
  67. if (WARN_ON(!pll_clk))
  68. return NULL;
  69. clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
  70. clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
  71. of_node_put(clkmgr_np);
  72. BUG_ON(!clk_mgr_a10_base_addr);
  73. pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
  74. of_property_read_string(node, "clock-output-names", &clk_name);
  75. init.name = clk_name;
  76. init.ops = ops;
  77. init.flags = 0;
  78. while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
  79. of_clk_get_parent_name(node, i)) != NULL)
  80. i++;
  81. init.num_parents = i;
  82. init.parent_names = parent_name;
  83. pll_clk->hw.hw.init = &init;
  84. pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
  85. clk = clk_register(NULL, &pll_clk->hw.hw);
  86. if (WARN_ON(IS_ERR(clk))) {
  87. kfree(pll_clk);
  88. return NULL;
  89. }
  90. rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  91. return clk;
  92. }
  93. void __init socfpga_a10_pll_init(struct device_node *node)
  94. {
  95. __socfpga_pll_init(node, &clk_pll_ops);
  96. }