clk-periph.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2011-2012 Calxeda, Inc.
  4. * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
  5. *
  6. * Based from clk-highbank.c
  7. */
  8. #include <linux/slab.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include "clk.h"
  13. #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
  14. static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
  15. unsigned long parent_rate)
  16. {
  17. struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
  18. u32 div, val;
  19. if (socfpgaclk->fixed_div) {
  20. div = socfpgaclk->fixed_div;
  21. } else {
  22. if (socfpgaclk->div_reg) {
  23. val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  24. val &= GENMASK(socfpgaclk->width - 1, 0);
  25. parent_rate /= (val + 1);
  26. }
  27. div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
  28. }
  29. return parent_rate / div;
  30. }
  31. static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
  32. {
  33. u32 clk_src;
  34. clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
  35. return clk_src & 0x1;
  36. }
  37. static const struct clk_ops periclk_ops = {
  38. .recalc_rate = clk_periclk_recalc_rate,
  39. .get_parent = clk_periclk_get_parent,
  40. };
  41. static __init void __socfpga_periph_init(struct device_node *node,
  42. const struct clk_ops *ops)
  43. {
  44. u32 reg;
  45. struct clk *clk;
  46. struct socfpga_periph_clk *periph_clk;
  47. const char *clk_name = node->name;
  48. const char *parent_name[SOCFPGA_MAX_PARENTS];
  49. struct clk_init_data init;
  50. int rc;
  51. u32 fixed_div;
  52. u32 div_reg[3];
  53. of_property_read_u32(node, "reg", &reg);
  54. periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
  55. if (WARN_ON(!periph_clk))
  56. return;
  57. periph_clk->hw.reg = clk_mgr_base_addr + reg;
  58. rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
  59. if (!rc) {
  60. periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
  61. periph_clk->shift = div_reg[1];
  62. periph_clk->width = div_reg[2];
  63. } else {
  64. periph_clk->div_reg = NULL;
  65. }
  66. rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
  67. if (rc)
  68. periph_clk->fixed_div = 0;
  69. else
  70. periph_clk->fixed_div = fixed_div;
  71. of_property_read_string(node, "clock-output-names", &clk_name);
  72. init.name = clk_name;
  73. init.ops = ops;
  74. init.flags = 0;
  75. init.num_parents = of_clk_parent_fill(node, parent_name,
  76. SOCFPGA_MAX_PARENTS);
  77. init.parent_names = parent_name;
  78. periph_clk->hw.hw.init = &init;
  79. clk = clk_register(NULL, &periph_clk->hw.hw);
  80. if (WARN_ON(IS_ERR(clk))) {
  81. kfree(periph_clk);
  82. return;
  83. }
  84. rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  85. }
  86. void __init socfpga_periph_init(struct device_node *node)
  87. {
  88. __socfpga_periph_init(node, &periclk_ops);
  89. }