clk-periph-s10.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017, Intel Corporation
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include "stratix10-clk.h"
  9. #include "clk.h"
  10. #define CLK_MGR_FREE_SHIFT 16
  11. #define CLK_MGR_FREE_MASK 0x7
  12. #define SWCTRLBTCLKSEN_SHIFT 8
  13. #define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
  14. static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
  15. unsigned long parent_rate)
  16. {
  17. struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
  18. unsigned long div = 1;
  19. u32 val;
  20. val = readl(socfpgaclk->hw.reg);
  21. val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
  22. parent_rate /= val;
  23. return parent_rate / div;
  24. }
  25. static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
  26. unsigned long parent_rate)
  27. {
  28. struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
  29. unsigned long div = 1;
  30. if (socfpgaclk->fixed_div) {
  31. div = socfpgaclk->fixed_div;
  32. } else {
  33. if (socfpgaclk->hw.reg)
  34. div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
  35. }
  36. return parent_rate / div;
  37. }
  38. static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
  39. {
  40. struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
  41. u32 clk_src, mask;
  42. u8 parent = 0;
  43. /* handle the bypass first */
  44. if (socfpgaclk->bypass_reg) {
  45. mask = (0x1 << socfpgaclk->bypass_shift);
  46. parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
  47. socfpgaclk->bypass_shift);
  48. if (parent)
  49. return parent;
  50. }
  51. if (socfpgaclk->hw.reg) {
  52. clk_src = readl(socfpgaclk->hw.reg);
  53. parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
  54. CLK_MGR_FREE_MASK;
  55. }
  56. return parent;
  57. }
  58. static const struct clk_ops peri_c_clk_ops = {
  59. .recalc_rate = clk_peri_c_clk_recalc_rate,
  60. .get_parent = clk_periclk_get_parent,
  61. };
  62. static const struct clk_ops peri_cnt_clk_ops = {
  63. .recalc_rate = clk_peri_cnt_clk_recalc_rate,
  64. .get_parent = clk_periclk_get_parent,
  65. };
  66. struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
  67. void __iomem *reg)
  68. {
  69. struct clk *clk;
  70. struct socfpga_periph_clk *periph_clk;
  71. struct clk_init_data init;
  72. const char *name = clks->name;
  73. const char *parent_name = clks->parent_name;
  74. periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
  75. if (WARN_ON(!periph_clk))
  76. return NULL;
  77. periph_clk->hw.reg = reg + clks->offset;
  78. init.name = name;
  79. init.ops = &peri_c_clk_ops;
  80. init.flags = clks->flags;
  81. init.num_parents = clks->num_parents;
  82. init.parent_names = parent_name ? &parent_name : NULL;
  83. if (init.parent_names == NULL)
  84. init.parent_data = clks->parent_data;
  85. periph_clk->hw.hw.init = &init;
  86. clk = clk_register(NULL, &periph_clk->hw.hw);
  87. if (WARN_ON(IS_ERR(clk))) {
  88. kfree(periph_clk);
  89. return NULL;
  90. }
  91. return clk;
  92. }
  93. struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
  94. void __iomem *regbase)
  95. {
  96. struct clk *clk;
  97. struct socfpga_periph_clk *periph_clk;
  98. struct clk_init_data init;
  99. const char *name = clks->name;
  100. const char *parent_name = clks->parent_name;
  101. periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
  102. if (WARN_ON(!periph_clk))
  103. return NULL;
  104. if (clks->offset)
  105. periph_clk->hw.reg = regbase + clks->offset;
  106. else
  107. periph_clk->hw.reg = NULL;
  108. if (clks->bypass_reg)
  109. periph_clk->bypass_reg = regbase + clks->bypass_reg;
  110. else
  111. periph_clk->bypass_reg = NULL;
  112. periph_clk->bypass_shift = clks->bypass_shift;
  113. periph_clk->fixed_div = clks->fixed_divider;
  114. init.name = name;
  115. init.ops = &peri_cnt_clk_ops;
  116. init.flags = clks->flags;
  117. init.num_parents = clks->num_parents;
  118. init.parent_names = parent_name ? &parent_name : NULL;
  119. if (init.parent_names == NULL)
  120. init.parent_data = clks->parent_data;
  121. periph_clk->hw.hw.init = &init;
  122. clk = clk_register(NULL, &periph_clk->hw.hw);
  123. if (WARN_ON(IS_ERR(clk))) {
  124. kfree(periph_clk);
  125. return NULL;
  126. }
  127. return clk;
  128. }