clk-gate.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2011-2012 Calxeda, Inc.
  4. * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
  5. *
  6. * Based from clk-highbank.c
  7. */
  8. #include <linux/slab.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/io.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of.h>
  13. #include <linux/regmap.h>
  14. #include "clk.h"
  15. #define SOCFPGA_L4_MP_CLK "l4_mp_clk"
  16. #define SOCFPGA_L4_SP_CLK "l4_sp_clk"
  17. #define SOCFPGA_NAND_CLK "nand_clk"
  18. #define SOCFPGA_NAND_X_CLK "nand_x_clk"
  19. #define SOCFPGA_MMC_CLK "sdmmc_clk"
  20. #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
  21. #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
  22. /* SDMMC Group for System Manager defines */
  23. #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
  24. static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
  25. {
  26. u32 l4_src;
  27. u32 perpll_src;
  28. const char *name = clk_hw_get_name(hwclk);
  29. if (streq(name, SOCFPGA_L4_MP_CLK)) {
  30. l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  31. return l4_src &= 0x1;
  32. }
  33. if (streq(name, SOCFPGA_L4_SP_CLK)) {
  34. l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  35. return !!(l4_src & 2);
  36. }
  37. perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  38. if (streq(name, SOCFPGA_MMC_CLK))
  39. return perpll_src &= 0x3;
  40. if (streq(name, SOCFPGA_NAND_CLK) ||
  41. streq(name, SOCFPGA_NAND_X_CLK))
  42. return (perpll_src >> 2) & 3;
  43. /* QSPI clock */
  44. return (perpll_src >> 4) & 3;
  45. }
  46. static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
  47. {
  48. u32 src_reg;
  49. const char *name = clk_hw_get_name(hwclk);
  50. if (streq(name, SOCFPGA_L4_MP_CLK)) {
  51. src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  52. src_reg &= ~0x1;
  53. src_reg |= parent;
  54. writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
  55. } else if (streq(name, SOCFPGA_L4_SP_CLK)) {
  56. src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  57. src_reg &= ~0x2;
  58. src_reg |= (parent << 1);
  59. writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
  60. } else {
  61. src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  62. if (streq(name, SOCFPGA_MMC_CLK)) {
  63. src_reg &= ~0x3;
  64. src_reg |= parent;
  65. } else if (streq(name, SOCFPGA_NAND_CLK) ||
  66. streq(name, SOCFPGA_NAND_X_CLK)) {
  67. src_reg &= ~0xC;
  68. src_reg |= (parent << 2);
  69. } else {/* QSPI clock */
  70. src_reg &= ~0x30;
  71. src_reg |= (parent << 4);
  72. }
  73. writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  74. }
  75. return 0;
  76. }
  77. static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
  78. unsigned long parent_rate)
  79. {
  80. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  81. u32 div = 1, val;
  82. if (socfpgaclk->fixed_div)
  83. div = socfpgaclk->fixed_div;
  84. else if (socfpgaclk->div_reg) {
  85. val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  86. val &= GENMASK(socfpgaclk->width - 1, 0);
  87. /* Check for GPIO_DB_CLK by its offset */
  88. if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
  89. div = val + 1;
  90. else
  91. div = (1 << val);
  92. }
  93. return parent_rate / div;
  94. }
  95. static int socfpga_clk_prepare(struct clk_hw *hwclk)
  96. {
  97. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  98. struct regmap *sys_mgr_base_addr;
  99. int i;
  100. u32 hs_timing;
  101. u32 clk_phase[2];
  102. if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
  103. sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
  104. if (IS_ERR(sys_mgr_base_addr)) {
  105. pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
  106. return -EINVAL;
  107. }
  108. for (i = 0; i < 2; i++) {
  109. switch (socfpgaclk->clk_phase[i]) {
  110. case 0:
  111. clk_phase[i] = 0;
  112. break;
  113. case 45:
  114. clk_phase[i] = 1;
  115. break;
  116. case 90:
  117. clk_phase[i] = 2;
  118. break;
  119. case 135:
  120. clk_phase[i] = 3;
  121. break;
  122. case 180:
  123. clk_phase[i] = 4;
  124. break;
  125. case 225:
  126. clk_phase[i] = 5;
  127. break;
  128. case 270:
  129. clk_phase[i] = 6;
  130. break;
  131. case 315:
  132. clk_phase[i] = 7;
  133. break;
  134. default:
  135. clk_phase[i] = 0;
  136. break;
  137. }
  138. }
  139. hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
  140. regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
  141. hs_timing);
  142. }
  143. return 0;
  144. }
  145. static struct clk_ops gateclk_ops = {
  146. .prepare = socfpga_clk_prepare,
  147. .recalc_rate = socfpga_clk_recalc_rate,
  148. .get_parent = socfpga_clk_get_parent,
  149. .set_parent = socfpga_clk_set_parent,
  150. };
  151. void __init socfpga_gate_init(struct device_node *node)
  152. {
  153. u32 clk_gate[2];
  154. u32 div_reg[3];
  155. u32 clk_phase[2];
  156. u32 fixed_div;
  157. struct clk *clk;
  158. struct socfpga_gate_clk *socfpga_clk;
  159. const char *clk_name = node->name;
  160. const char *parent_name[SOCFPGA_MAX_PARENTS];
  161. struct clk_init_data init;
  162. struct clk_ops *ops;
  163. int rc;
  164. socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
  165. if (WARN_ON(!socfpga_clk))
  166. return;
  167. ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
  168. if (WARN_ON(!ops))
  169. return;
  170. rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
  171. if (rc)
  172. clk_gate[0] = 0;
  173. if (clk_gate[0]) {
  174. socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
  175. socfpga_clk->hw.bit_idx = clk_gate[1];
  176. ops->enable = clk_gate_ops.enable;
  177. ops->disable = clk_gate_ops.disable;
  178. }
  179. rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
  180. if (rc)
  181. socfpga_clk->fixed_div = 0;
  182. else
  183. socfpga_clk->fixed_div = fixed_div;
  184. rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
  185. if (!rc) {
  186. socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
  187. socfpga_clk->shift = div_reg[1];
  188. socfpga_clk->width = div_reg[2];
  189. } else {
  190. socfpga_clk->div_reg = NULL;
  191. }
  192. rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
  193. if (!rc) {
  194. socfpga_clk->clk_phase[0] = clk_phase[0];
  195. socfpga_clk->clk_phase[1] = clk_phase[1];
  196. }
  197. of_property_read_string(node, "clock-output-names", &clk_name);
  198. init.name = clk_name;
  199. init.ops = ops;
  200. init.flags = 0;
  201. init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
  202. if (init.num_parents < 2) {
  203. ops->get_parent = NULL;
  204. ops->set_parent = NULL;
  205. }
  206. init.parent_names = parent_name;
  207. socfpga_clk->hw.hw.init = &init;
  208. clk = clk_register(NULL, &socfpga_clk->hw.hw);
  209. if (WARN_ON(IS_ERR(clk))) {
  210. kfree(socfpga_clk);
  211. return;
  212. }
  213. rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  214. if (WARN_ON(rc))
  215. return;
  216. }