clk.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. * Author: Thomas Abraham <thomas.ab@samsung.com>
  6. *
  7. * Common Clock Framework support for all Samsung platforms
  8. */
  9. #ifndef __SAMSUNG_CLK_H
  10. #define __SAMSUNG_CLK_H
  11. #include <linux/clk-provider.h>
  12. #include "clk-pll.h"
  13. /**
  14. * struct samsung_clk_provider: information about clock provider
  15. * @reg_base: virtual address for the register base.
  16. * @lock: maintains exclusion between callbacks for a given clock-provider.
  17. * @clk_data: holds clock related data like clk_hw* and number of clocks.
  18. */
  19. struct samsung_clk_provider {
  20. void __iomem *reg_base;
  21. struct device *dev;
  22. spinlock_t lock;
  23. /* clk_data must be the last entry due to variable length 'hws' array */
  24. struct clk_hw_onecell_data clk_data;
  25. };
  26. /**
  27. * struct samsung_clock_alias: information about mux clock
  28. * @id: platform specific id of the clock.
  29. * @dev_name: name of the device to which this clock belongs.
  30. * @alias: optional clock alias name to be assigned to this clock.
  31. */
  32. struct samsung_clock_alias {
  33. unsigned int id;
  34. const char *dev_name;
  35. const char *alias;
  36. };
  37. #define ALIAS(_id, dname, a) \
  38. { \
  39. .id = _id, \
  40. .dev_name = dname, \
  41. .alias = a, \
  42. }
  43. #define MHZ (1000 * 1000)
  44. /**
  45. * struct samsung_fixed_rate_clock: information about fixed-rate clock
  46. * @id: platform specific id of the clock.
  47. * @name: name of this fixed-rate clock.
  48. * @parent_name: optional parent clock name.
  49. * @flags: optional fixed-rate clock flags.
  50. * @fixed-rate: fixed clock rate of this clock.
  51. */
  52. struct samsung_fixed_rate_clock {
  53. unsigned int id;
  54. char *name;
  55. const char *parent_name;
  56. unsigned long flags;
  57. unsigned long fixed_rate;
  58. };
  59. #define FRATE(_id, cname, pname, f, frate) \
  60. { \
  61. .id = _id, \
  62. .name = cname, \
  63. .parent_name = pname, \
  64. .flags = f, \
  65. .fixed_rate = frate, \
  66. }
  67. /*
  68. * struct samsung_fixed_factor_clock: information about fixed-factor clock
  69. * @id: platform specific id of the clock.
  70. * @name: name of this fixed-factor clock.
  71. * @parent_name: parent clock name.
  72. * @mult: fixed multiplication factor.
  73. * @div: fixed division factor.
  74. * @flags: optional fixed-factor clock flags.
  75. */
  76. struct samsung_fixed_factor_clock {
  77. unsigned int id;
  78. char *name;
  79. const char *parent_name;
  80. unsigned long mult;
  81. unsigned long div;
  82. unsigned long flags;
  83. };
  84. #define FFACTOR(_id, cname, pname, m, d, f) \
  85. { \
  86. .id = _id, \
  87. .name = cname, \
  88. .parent_name = pname, \
  89. .mult = m, \
  90. .div = d, \
  91. .flags = f, \
  92. }
  93. /**
  94. * struct samsung_mux_clock: information about mux clock
  95. * @id: platform specific id of the clock.
  96. * @name: name of this mux clock.
  97. * @parent_names: array of pointer to parent clock names.
  98. * @num_parents: number of parents listed in @parent_names.
  99. * @flags: optional flags for basic clock.
  100. * @offset: offset of the register for configuring the mux.
  101. * @shift: starting bit location of the mux control bit-field in @reg.
  102. * @width: width of the mux control bit-field in @reg.
  103. * @mux_flags: flags for mux-type clock.
  104. */
  105. struct samsung_mux_clock {
  106. unsigned int id;
  107. const char *name;
  108. const char *const *parent_names;
  109. u8 num_parents;
  110. unsigned long flags;
  111. unsigned long offset;
  112. u8 shift;
  113. u8 width;
  114. u8 mux_flags;
  115. };
  116. #define __MUX(_id, cname, pnames, o, s, w, f, mf) \
  117. { \
  118. .id = _id, \
  119. .name = cname, \
  120. .parent_names = pnames, \
  121. .num_parents = ARRAY_SIZE(pnames), \
  122. .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
  123. .offset = o, \
  124. .shift = s, \
  125. .width = w, \
  126. .mux_flags = mf, \
  127. }
  128. #define MUX(_id, cname, pnames, o, s, w) \
  129. __MUX(_id, cname, pnames, o, s, w, 0, 0)
  130. #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
  131. __MUX(_id, cname, pnames, o, s, w, f, mf)
  132. /**
  133. * @id: platform specific id of the clock.
  134. * struct samsung_div_clock: information about div clock
  135. * @name: name of this div clock.
  136. * @parent_name: name of the parent clock.
  137. * @flags: optional flags for basic clock.
  138. * @offset: offset of the register for configuring the div.
  139. * @shift: starting bit location of the div control bit-field in @reg.
  140. * @div_flags: flags for div-type clock.
  141. */
  142. struct samsung_div_clock {
  143. unsigned int id;
  144. const char *name;
  145. const char *parent_name;
  146. unsigned long flags;
  147. unsigned long offset;
  148. u8 shift;
  149. u8 width;
  150. u8 div_flags;
  151. struct clk_div_table *table;
  152. };
  153. #define __DIV(_id, cname, pname, o, s, w, f, df, t) \
  154. { \
  155. .id = _id, \
  156. .name = cname, \
  157. .parent_name = pname, \
  158. .flags = f, \
  159. .offset = o, \
  160. .shift = s, \
  161. .width = w, \
  162. .div_flags = df, \
  163. .table = t, \
  164. }
  165. #define DIV(_id, cname, pname, o, s, w) \
  166. __DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
  167. #define DIV_F(_id, cname, pname, o, s, w, f, df) \
  168. __DIV(_id, cname, pname, o, s, w, f, df, NULL)
  169. #define DIV_T(_id, cname, pname, o, s, w, t) \
  170. __DIV(_id, cname, pname, o, s, w, 0, 0, t)
  171. /**
  172. * struct samsung_gate_clock: information about gate clock
  173. * @id: platform specific id of the clock.
  174. * @name: name of this gate clock.
  175. * @parent_name: name of the parent clock.
  176. * @flags: optional flags for basic clock.
  177. * @offset: offset of the register for configuring the gate.
  178. * @bit_idx: bit index of the gate control bit-field in @reg.
  179. * @gate_flags: flags for gate-type clock.
  180. */
  181. struct samsung_gate_clock {
  182. unsigned int id;
  183. const char *name;
  184. const char *parent_name;
  185. unsigned long flags;
  186. unsigned long offset;
  187. u8 bit_idx;
  188. u8 gate_flags;
  189. };
  190. #define __GATE(_id, cname, pname, o, b, f, gf) \
  191. { \
  192. .id = _id, \
  193. .name = cname, \
  194. .parent_name = pname, \
  195. .flags = f, \
  196. .offset = o, \
  197. .bit_idx = b, \
  198. .gate_flags = gf, \
  199. }
  200. #define GATE(_id, cname, pname, o, b, f, gf) \
  201. __GATE(_id, cname, pname, o, b, f, gf)
  202. #define PNAME(x) static const char * const x[] __initconst
  203. /**
  204. * struct samsung_clk_reg_dump: register dump of clock controller registers.
  205. * @offset: clock register offset from the controller base address.
  206. * @value: the value to be register at offset.
  207. */
  208. struct samsung_clk_reg_dump {
  209. u32 offset;
  210. u32 value;
  211. };
  212. /**
  213. * struct samsung_pll_clock: information about pll clock
  214. * @id: platform specific id of the clock.
  215. * @name: name of this pll clock.
  216. * @parent_name: name of the parent clock.
  217. * @flags: optional flags for basic clock.
  218. * @con_offset: offset of the register for configuring the PLL.
  219. * @lock_offset: offset of the register for locking the PLL.
  220. * @type: Type of PLL to be registered.
  221. */
  222. struct samsung_pll_clock {
  223. unsigned int id;
  224. const char *name;
  225. const char *parent_name;
  226. unsigned long flags;
  227. int con_offset;
  228. int lock_offset;
  229. enum samsung_pll_type type;
  230. const struct samsung_pll_rate_table *rate_table;
  231. };
  232. #define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
  233. { \
  234. .id = _id, \
  235. .type = _typ, \
  236. .name = _name, \
  237. .parent_name = _pname, \
  238. .flags = _flags, \
  239. .con_offset = _con, \
  240. .lock_offset = _lock, \
  241. .rate_table = _rtable, \
  242. }
  243. #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
  244. __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
  245. _con, _rtable)
  246. struct samsung_clock_reg_cache {
  247. struct list_head node;
  248. void __iomem *reg_base;
  249. struct samsung_clk_reg_dump *rdump;
  250. unsigned int rd_num;
  251. const struct samsung_clk_reg_dump *rsuspend;
  252. unsigned int rsuspend_num;
  253. };
  254. struct samsung_cmu_info {
  255. /* list of pll clocks and respective count */
  256. const struct samsung_pll_clock *pll_clks;
  257. unsigned int nr_pll_clks;
  258. /* list of mux clocks and respective count */
  259. const struct samsung_mux_clock *mux_clks;
  260. unsigned int nr_mux_clks;
  261. /* list of div clocks and respective count */
  262. const struct samsung_div_clock *div_clks;
  263. unsigned int nr_div_clks;
  264. /* list of gate clocks and respective count */
  265. const struct samsung_gate_clock *gate_clks;
  266. unsigned int nr_gate_clks;
  267. /* list of fixed clocks and respective count */
  268. const struct samsung_fixed_rate_clock *fixed_clks;
  269. unsigned int nr_fixed_clks;
  270. /* list of fixed factor clocks and respective count */
  271. const struct samsung_fixed_factor_clock *fixed_factor_clks;
  272. unsigned int nr_fixed_factor_clks;
  273. /* total number of clocks with IDs assigned*/
  274. unsigned int nr_clk_ids;
  275. /* list and number of clocks registers */
  276. const unsigned long *clk_regs;
  277. unsigned int nr_clk_regs;
  278. /* list and number of clocks registers to set before suspend */
  279. const struct samsung_clk_reg_dump *suspend_regs;
  280. unsigned int nr_suspend_regs;
  281. /* name of the parent clock needed for CMU register access */
  282. const char *clk_name;
  283. };
  284. extern struct samsung_clk_provider *__init samsung_clk_init(
  285. struct device_node *np, void __iomem *base,
  286. unsigned long nr_clks);
  287. extern void __init samsung_clk_of_add_provider(struct device_node *np,
  288. struct samsung_clk_provider *ctx);
  289. extern void __init samsung_clk_of_register_fixed_ext(
  290. struct samsung_clk_provider *ctx,
  291. struct samsung_fixed_rate_clock *fixed_rate_clk,
  292. unsigned int nr_fixed_rate_clk,
  293. const struct of_device_id *clk_matches);
  294. extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
  295. struct clk_hw *clk_hw, unsigned int id);
  296. extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
  297. const struct samsung_clock_alias *list,
  298. unsigned int nr_clk);
  299. extern void __init samsung_clk_register_fixed_rate(
  300. struct samsung_clk_provider *ctx,
  301. const struct samsung_fixed_rate_clock *clk_list,
  302. unsigned int nr_clk);
  303. extern void __init samsung_clk_register_fixed_factor(
  304. struct samsung_clk_provider *ctx,
  305. const struct samsung_fixed_factor_clock *list,
  306. unsigned int nr_clk);
  307. extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
  308. const struct samsung_mux_clock *clk_list,
  309. unsigned int nr_clk);
  310. extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
  311. const struct samsung_div_clock *clk_list,
  312. unsigned int nr_clk);
  313. extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
  314. const struct samsung_gate_clock *clk_list,
  315. unsigned int nr_clk);
  316. extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
  317. const struct samsung_pll_clock *pll_list,
  318. unsigned int nr_clk, void __iomem *base);
  319. extern struct samsung_clk_provider __init *samsung_cmu_register_one(
  320. struct device_node *,
  321. const struct samsung_cmu_info *);
  322. extern unsigned long _get_rate(const char *clk_name);
  323. #ifdef CONFIG_PM_SLEEP
  324. extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
  325. const unsigned long *rdump,
  326. unsigned long nr_rdump,
  327. const struct samsung_clk_reg_dump *rsuspend,
  328. unsigned long nr_rsuspend);
  329. #else
  330. static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
  331. const unsigned long *rdump,
  332. unsigned long nr_rdump,
  333. const struct samsung_clk_reg_dump *rsuspend,
  334. unsigned long nr_rsuspend) {}
  335. #endif
  336. #define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
  337. samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
  338. extern void samsung_clk_save(void __iomem *base,
  339. struct samsung_clk_reg_dump *rd,
  340. unsigned int num_regs);
  341. extern void samsung_clk_restore(void __iomem *base,
  342. const struct samsung_clk_reg_dump *rd,
  343. unsigned int num_regs);
  344. extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
  345. const unsigned long *rdump,
  346. unsigned long nr_rdump);
  347. #endif /* __SAMSUNG_CLK_H */