clk.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. * Author: Thomas Abraham <thomas.ab@samsung.com>
  6. *
  7. * This file includes utility functions to register clocks to common
  8. * clock framework for Samsung platforms.
  9. */
  10. #include <linux/slab.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of_address.h>
  16. #include <linux/syscore_ops.h>
  17. #include "clk.h"
  18. static LIST_HEAD(clock_reg_cache_list);
  19. void samsung_clk_save(void __iomem *base,
  20. struct samsung_clk_reg_dump *rd,
  21. unsigned int num_regs)
  22. {
  23. for (; num_regs > 0; --num_regs, ++rd)
  24. rd->value = readl(base + rd->offset);
  25. }
  26. void samsung_clk_restore(void __iomem *base,
  27. const struct samsung_clk_reg_dump *rd,
  28. unsigned int num_regs)
  29. {
  30. for (; num_regs > 0; --num_regs, ++rd)
  31. writel(rd->value, base + rd->offset);
  32. }
  33. struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
  34. const unsigned long *rdump,
  35. unsigned long nr_rdump)
  36. {
  37. struct samsung_clk_reg_dump *rd;
  38. unsigned int i;
  39. rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
  40. if (!rd)
  41. return NULL;
  42. for (i = 0; i < nr_rdump; ++i)
  43. rd[i].offset = rdump[i];
  44. return rd;
  45. }
  46. /* setup the essentials required to support clock lookup using ccf */
  47. struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
  48. void __iomem *base, unsigned long nr_clks)
  49. {
  50. struct samsung_clk_provider *ctx;
  51. int i;
  52. ctx = kzalloc(struct_size(ctx, clk_data.hws, nr_clks), GFP_KERNEL);
  53. if (!ctx)
  54. panic("could not allocate clock provider context.\n");
  55. for (i = 0; i < nr_clks; ++i)
  56. ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
  57. ctx->reg_base = base;
  58. ctx->clk_data.num = nr_clks;
  59. spin_lock_init(&ctx->lock);
  60. return ctx;
  61. }
  62. void __init samsung_clk_of_add_provider(struct device_node *np,
  63. struct samsung_clk_provider *ctx)
  64. {
  65. if (np) {
  66. if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
  67. &ctx->clk_data))
  68. panic("could not register clk provider\n");
  69. }
  70. }
  71. /* add a clock instance to the clock lookup table used for dt based lookup */
  72. void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
  73. struct clk_hw *clk_hw, unsigned int id)
  74. {
  75. if (id)
  76. ctx->clk_data.hws[id] = clk_hw;
  77. }
  78. /* register a list of aliases */
  79. void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
  80. const struct samsung_clock_alias *list,
  81. unsigned int nr_clk)
  82. {
  83. struct clk_hw *clk_hw;
  84. unsigned int idx, ret;
  85. for (idx = 0; idx < nr_clk; idx++, list++) {
  86. if (!list->id) {
  87. pr_err("%s: clock id missing for index %d\n", __func__,
  88. idx);
  89. continue;
  90. }
  91. clk_hw = ctx->clk_data.hws[list->id];
  92. if (!clk_hw) {
  93. pr_err("%s: failed to find clock %d\n", __func__,
  94. list->id);
  95. continue;
  96. }
  97. ret = clk_hw_register_clkdev(clk_hw, list->alias,
  98. list->dev_name);
  99. if (ret)
  100. pr_err("%s: failed to register lookup %s\n",
  101. __func__, list->alias);
  102. }
  103. }
  104. /* register a list of fixed clocks */
  105. void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
  106. const struct samsung_fixed_rate_clock *list,
  107. unsigned int nr_clk)
  108. {
  109. struct clk_hw *clk_hw;
  110. unsigned int idx, ret;
  111. for (idx = 0; idx < nr_clk; idx++, list++) {
  112. clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
  113. list->parent_name, list->flags, list->fixed_rate);
  114. if (IS_ERR(clk_hw)) {
  115. pr_err("%s: failed to register clock %s\n", __func__,
  116. list->name);
  117. continue;
  118. }
  119. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  120. /*
  121. * Unconditionally add a clock lookup for the fixed rate clocks.
  122. * There are not many of these on any of Samsung platforms.
  123. */
  124. ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
  125. if (ret)
  126. pr_err("%s: failed to register clock lookup for %s",
  127. __func__, list->name);
  128. }
  129. }
  130. /* register a list of fixed factor clocks */
  131. void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
  132. const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
  133. {
  134. struct clk_hw *clk_hw;
  135. unsigned int idx;
  136. for (idx = 0; idx < nr_clk; idx++, list++) {
  137. clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
  138. list->parent_name, list->flags, list->mult, list->div);
  139. if (IS_ERR(clk_hw)) {
  140. pr_err("%s: failed to register clock %s\n", __func__,
  141. list->name);
  142. continue;
  143. }
  144. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  145. }
  146. }
  147. /* register a list of mux clocks */
  148. void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
  149. const struct samsung_mux_clock *list,
  150. unsigned int nr_clk)
  151. {
  152. struct clk_hw *clk_hw;
  153. unsigned int idx;
  154. for (idx = 0; idx < nr_clk; idx++, list++) {
  155. clk_hw = clk_hw_register_mux(ctx->dev, list->name,
  156. list->parent_names, list->num_parents, list->flags,
  157. ctx->reg_base + list->offset,
  158. list->shift, list->width, list->mux_flags, &ctx->lock);
  159. if (IS_ERR(clk_hw)) {
  160. pr_err("%s: failed to register clock %s\n", __func__,
  161. list->name);
  162. continue;
  163. }
  164. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  165. }
  166. }
  167. /* register a list of div clocks */
  168. void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
  169. const struct samsung_div_clock *list,
  170. unsigned int nr_clk)
  171. {
  172. struct clk_hw *clk_hw;
  173. unsigned int idx;
  174. for (idx = 0; idx < nr_clk; idx++, list++) {
  175. if (list->table)
  176. clk_hw = clk_hw_register_divider_table(ctx->dev,
  177. list->name, list->parent_name, list->flags,
  178. ctx->reg_base + list->offset,
  179. list->shift, list->width, list->div_flags,
  180. list->table, &ctx->lock);
  181. else
  182. clk_hw = clk_hw_register_divider(ctx->dev, list->name,
  183. list->parent_name, list->flags,
  184. ctx->reg_base + list->offset, list->shift,
  185. list->width, list->div_flags, &ctx->lock);
  186. if (IS_ERR(clk_hw)) {
  187. pr_err("%s: failed to register clock %s\n", __func__,
  188. list->name);
  189. continue;
  190. }
  191. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  192. }
  193. }
  194. /* register a list of gate clocks */
  195. void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
  196. const struct samsung_gate_clock *list,
  197. unsigned int nr_clk)
  198. {
  199. struct clk_hw *clk_hw;
  200. unsigned int idx;
  201. for (idx = 0; idx < nr_clk; idx++, list++) {
  202. clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
  203. list->flags, ctx->reg_base + list->offset,
  204. list->bit_idx, list->gate_flags, &ctx->lock);
  205. if (IS_ERR(clk_hw)) {
  206. pr_err("%s: failed to register clock %s\n", __func__,
  207. list->name);
  208. continue;
  209. }
  210. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  211. }
  212. }
  213. /*
  214. * obtain the clock speed of all external fixed clock sources from device
  215. * tree and register it
  216. */
  217. void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
  218. struct samsung_fixed_rate_clock *fixed_rate_clk,
  219. unsigned int nr_fixed_rate_clk,
  220. const struct of_device_id *clk_matches)
  221. {
  222. const struct of_device_id *match;
  223. struct device_node *clk_np;
  224. u32 freq;
  225. for_each_matching_node_and_match(clk_np, clk_matches, &match) {
  226. if (of_property_read_u32(clk_np, "clock-frequency", &freq))
  227. continue;
  228. fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
  229. }
  230. samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
  231. }
  232. /* utility function to get the rate of a specified clock */
  233. unsigned long _get_rate(const char *clk_name)
  234. {
  235. struct clk *clk;
  236. clk = __clk_lookup(clk_name);
  237. if (!clk) {
  238. pr_err("%s: could not find clock %s\n", __func__, clk_name);
  239. return 0;
  240. }
  241. return clk_get_rate(clk);
  242. }
  243. #ifdef CONFIG_PM_SLEEP
  244. static int samsung_clk_suspend(void)
  245. {
  246. struct samsung_clock_reg_cache *reg_cache;
  247. list_for_each_entry(reg_cache, &clock_reg_cache_list, node) {
  248. samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
  249. reg_cache->rd_num);
  250. samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend,
  251. reg_cache->rsuspend_num);
  252. }
  253. return 0;
  254. }
  255. static void samsung_clk_resume(void)
  256. {
  257. struct samsung_clock_reg_cache *reg_cache;
  258. list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
  259. samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
  260. reg_cache->rd_num);
  261. }
  262. static struct syscore_ops samsung_clk_syscore_ops = {
  263. .suspend = samsung_clk_suspend,
  264. .resume = samsung_clk_resume,
  265. };
  266. void samsung_clk_extended_sleep_init(void __iomem *reg_base,
  267. const unsigned long *rdump,
  268. unsigned long nr_rdump,
  269. const struct samsung_clk_reg_dump *rsuspend,
  270. unsigned long nr_rsuspend)
  271. {
  272. struct samsung_clock_reg_cache *reg_cache;
  273. reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
  274. GFP_KERNEL);
  275. if (!reg_cache)
  276. panic("could not allocate register reg_cache.\n");
  277. reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
  278. if (!reg_cache->rdump)
  279. panic("could not allocate register dump storage.\n");
  280. if (list_empty(&clock_reg_cache_list))
  281. register_syscore_ops(&samsung_clk_syscore_ops);
  282. reg_cache->reg_base = reg_base;
  283. reg_cache->rd_num = nr_rdump;
  284. reg_cache->rsuspend = rsuspend;
  285. reg_cache->rsuspend_num = nr_rsuspend;
  286. list_add_tail(&reg_cache->node, &clock_reg_cache_list);
  287. }
  288. #endif
  289. /*
  290. * Common function which registers plls, muxes, dividers and gates
  291. * for each CMU. It also add CMU register list to register cache.
  292. */
  293. struct samsung_clk_provider * __init samsung_cmu_register_one(
  294. struct device_node *np,
  295. const struct samsung_cmu_info *cmu)
  296. {
  297. void __iomem *reg_base;
  298. struct samsung_clk_provider *ctx;
  299. reg_base = of_iomap(np, 0);
  300. if (!reg_base) {
  301. panic("%s: failed to map registers\n", __func__);
  302. return NULL;
  303. }
  304. ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
  305. if (cmu->pll_clks)
  306. samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
  307. reg_base);
  308. if (cmu->mux_clks)
  309. samsung_clk_register_mux(ctx, cmu->mux_clks,
  310. cmu->nr_mux_clks);
  311. if (cmu->div_clks)
  312. samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
  313. if (cmu->gate_clks)
  314. samsung_clk_register_gate(ctx, cmu->gate_clks,
  315. cmu->nr_gate_clks);
  316. if (cmu->fixed_clks)
  317. samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
  318. cmu->nr_fixed_clks);
  319. if (cmu->fixed_factor_clks)
  320. samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
  321. cmu->nr_fixed_factor_clks);
  322. if (cmu->clk_regs)
  323. samsung_clk_extended_sleep_init(reg_base,
  324. cmu->clk_regs, cmu->nr_clk_regs,
  325. cmu->suspend_regs, cmu->nr_suspend_regs);
  326. samsung_clk_of_add_provider(np, ctx);
  327. return ctx;
  328. }