clk-s3c64xx.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
  4. *
  5. * Common Clock Framework support for all S3C64xx SoCs.
  6. */
  7. #include <linux/slab.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/clk/samsung.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
  13. #include "clk.h"
  14. #include "clk-pll.h"
  15. /* S3C64xx clock controller register offsets. */
  16. #define APLL_LOCK 0x000
  17. #define MPLL_LOCK 0x004
  18. #define EPLL_LOCK 0x008
  19. #define APLL_CON 0x00c
  20. #define MPLL_CON 0x010
  21. #define EPLL_CON0 0x014
  22. #define EPLL_CON1 0x018
  23. #define CLK_SRC 0x01c
  24. #define CLK_DIV0 0x020
  25. #define CLK_DIV1 0x024
  26. #define CLK_DIV2 0x028
  27. #define HCLK_GATE 0x030
  28. #define PCLK_GATE 0x034
  29. #define SCLK_GATE 0x038
  30. #define MEM0_GATE 0x03c
  31. #define CLK_SRC2 0x10c
  32. #define OTHERS 0x900
  33. /* Helper macros to define clock arrays. */
  34. #define FIXED_RATE_CLOCKS(name) \
  35. static struct samsung_fixed_rate_clock name[]
  36. #define MUX_CLOCKS(name) \
  37. static struct samsung_mux_clock name[]
  38. #define DIV_CLOCKS(name) \
  39. static struct samsung_div_clock name[]
  40. #define GATE_CLOCKS(name) \
  41. static struct samsung_gate_clock name[]
  42. /* Helper macros for gate types present on S3C64xx. */
  43. #define GATE_BUS(_id, cname, pname, o, b) \
  44. GATE(_id, cname, pname, o, b, 0, 0)
  45. #define GATE_SCLK(_id, cname, pname, o, b) \
  46. GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
  47. #define GATE_ON(_id, cname, pname, o, b) \
  48. GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
  49. static void __iomem *reg_base;
  50. static bool is_s3c6400;
  51. /*
  52. * List of controller registers to be saved and restored during
  53. * a suspend/resume cycle.
  54. */
  55. static unsigned long s3c64xx_clk_regs[] __initdata = {
  56. APLL_LOCK,
  57. MPLL_LOCK,
  58. EPLL_LOCK,
  59. APLL_CON,
  60. MPLL_CON,
  61. EPLL_CON0,
  62. EPLL_CON1,
  63. CLK_SRC,
  64. CLK_DIV0,
  65. CLK_DIV1,
  66. CLK_DIV2,
  67. HCLK_GATE,
  68. PCLK_GATE,
  69. SCLK_GATE,
  70. };
  71. static unsigned long s3c6410_clk_regs[] __initdata = {
  72. CLK_SRC2,
  73. MEM0_GATE,
  74. };
  75. /* List of parent clocks common for all S3C64xx SoCs. */
  76. PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
  77. PNAME(uart_p) = { "mout_epll", "dout_mpll" };
  78. PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
  79. "pcmcdclk0", "none", "none", "none" };
  80. PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
  81. "pcmcdclk0", "none", "none", "none" };
  82. PNAME(mfc_p) = { "hclkx2", "mout_epll" };
  83. PNAME(apll_p) = { "fin_pll", "fout_apll" };
  84. PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
  85. PNAME(epll_p) = { "fin_pll", "fout_epll" };
  86. PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
  87. /* S3C6400-specific parent clocks. */
  88. PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
  89. PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
  90. PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
  91. /* S3C6410-specific parent clocks. */
  92. PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
  93. PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
  94. PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
  95. PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
  96. PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
  97. "pcmcdclk1", "none", "none", "none" };
  98. /* Fixed rate clocks generated outside the SoC. */
  99. FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
  100. FRATE(0, "fin_pll", NULL, 0, 0),
  101. FRATE(0, "xusbxti", NULL, 0, 0),
  102. };
  103. /* Fixed rate clocks generated inside the SoC. */
  104. FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
  105. FRATE(CLK27M, "clk27m", NULL, 0, 27000000),
  106. FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
  107. };
  108. /* List of clock muxes present on all S3C64xx SoCs. */
  109. MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
  110. MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
  111. MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
  112. MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
  113. MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
  114. MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
  115. MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
  116. MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
  117. MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
  118. MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
  119. MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
  120. MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
  121. MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
  122. MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
  123. };
  124. /* List of clock muxes present on S3C6400. */
  125. MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
  126. MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
  127. MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
  128. MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
  129. MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
  130. };
  131. /* List of clock muxes present on S3C6410. */
  132. MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
  133. MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
  134. MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
  135. MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
  136. MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
  137. MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
  138. MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
  139. MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
  140. };
  141. /* List of clock dividers present on all S3C64xx SoCs. */
  142. DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
  143. DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
  144. DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
  145. DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
  146. DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
  147. DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
  148. DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
  149. DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
  150. DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
  151. DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
  152. DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
  153. DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
  154. DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
  155. DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
  156. DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
  157. DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
  158. DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
  159. DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
  160. DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
  161. DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
  162. DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
  163. };
  164. /* List of clock dividers present on S3C6400. */
  165. DIV_CLOCKS(s3c6400_div_clks) __initdata = {
  166. DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
  167. };
  168. /* List of clock dividers present on S3C6410. */
  169. DIV_CLOCKS(s3c6410_div_clks) __initdata = {
  170. DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
  171. DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
  172. DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
  173. };
  174. /* List of clock gates present on all S3C64xx SoCs. */
  175. GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
  176. GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
  177. GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
  178. GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
  179. GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
  180. GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
  181. GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
  182. GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
  183. GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
  184. GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
  185. GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
  186. GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
  187. GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
  188. GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
  189. GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
  190. GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
  191. GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
  192. GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
  193. GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
  194. GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
  195. GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
  196. GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
  197. GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
  198. GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
  199. GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
  200. GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
  201. GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
  202. GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
  203. GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
  204. GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
  205. GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
  206. GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
  207. GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
  208. GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
  209. GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
  210. GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
  211. GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
  212. GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
  213. GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
  214. GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
  215. GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
  216. GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
  217. GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
  218. GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
  219. GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
  220. GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
  221. GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
  222. GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
  223. GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
  224. GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
  225. GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
  226. GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
  227. GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
  228. GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
  229. GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
  230. GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
  231. GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
  232. GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
  233. GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
  234. GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
  235. GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
  236. GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
  237. GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
  238. GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
  239. GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
  240. GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
  241. GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
  242. GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
  243. GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
  244. GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
  245. GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
  246. GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
  247. GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
  248. GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
  249. GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
  250. GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
  251. GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
  252. };
  253. /* List of clock gates present on S3C6400. */
  254. GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
  255. GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
  256. GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
  257. };
  258. /* List of clock gates present on S3C6410. */
  259. GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
  260. GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
  261. GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
  262. GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
  263. GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
  264. GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
  265. GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
  266. GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
  267. GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
  268. GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
  269. GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
  270. GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
  271. GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
  272. GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
  273. GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
  274. };
  275. /* List of PLL clocks. */
  276. static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
  277. PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
  278. APLL_LOCK, APLL_CON, NULL),
  279. PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
  280. MPLL_LOCK, MPLL_CON, NULL),
  281. PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
  282. EPLL_LOCK, EPLL_CON0, NULL),
  283. };
  284. /* Aliases for common s3c64xx clocks. */
  285. static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
  286. ALIAS(FOUT_APLL, NULL, "fout_apll"),
  287. ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
  288. ALIAS(FOUT_EPLL, NULL, "fout_epll"),
  289. ALIAS(MOUT_EPLL, NULL, "mout_epll"),
  290. ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
  291. ALIAS(HCLKX2, NULL, "hclk2"),
  292. ALIAS(HCLK, NULL, "hclk"),
  293. ALIAS(PCLK, NULL, "pclk"),
  294. ALIAS(PCLK, NULL, "clk_uart_baud2"),
  295. ALIAS(ARMCLK, NULL, "armclk"),
  296. ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
  297. ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
  298. ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
  299. ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
  300. ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
  301. ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
  302. ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
  303. ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
  304. ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
  305. ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
  306. ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
  307. ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
  308. ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
  309. ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
  310. ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
  311. ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
  312. ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
  313. ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
  314. ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
  315. ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
  316. ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
  317. ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
  318. ALIAS(PCLK_PWM, NULL, "timers"),
  319. ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
  320. ALIAS(PCLK_WDT, NULL, "watchdog"),
  321. ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
  322. ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
  323. ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
  324. ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
  325. ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
  326. ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
  327. ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
  328. ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
  329. ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
  330. ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
  331. ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
  332. ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
  333. ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
  334. ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
  335. ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
  336. ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
  337. ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
  338. ALIAS(SCLK_CAM, "s3c-camif", "camera"),
  339. };
  340. /* Aliases for s3c6400-specific clocks. */
  341. static struct samsung_clock_alias s3c6400_clock_aliases[] = {
  342. /* Nothing to place here yet. */
  343. };
  344. /* Aliases for s3c6410-specific clocks. */
  345. static struct samsung_clock_alias s3c6410_clock_aliases[] = {
  346. ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
  347. ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
  348. ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
  349. ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
  350. ALIAS(MEM0_SROM, NULL, "srom"),
  351. };
  352. static void __init s3c64xx_clk_register_fixed_ext(
  353. struct samsung_clk_provider *ctx,
  354. unsigned long fin_pll_f,
  355. unsigned long xusbxti_f)
  356. {
  357. s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
  358. s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
  359. samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
  360. ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
  361. }
  362. /* Register s3c64xx clocks. */
  363. void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
  364. unsigned long xusbxti_f, bool s3c6400,
  365. void __iomem *base)
  366. {
  367. struct samsung_clk_provider *ctx;
  368. reg_base = base;
  369. is_s3c6400 = s3c6400;
  370. if (np) {
  371. reg_base = of_iomap(np, 0);
  372. if (!reg_base)
  373. panic("%s: failed to map registers\n", __func__);
  374. }
  375. ctx = samsung_clk_init(np, reg_base, NR_CLKS);
  376. /* Register external clocks. */
  377. if (!np)
  378. s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
  379. /* Register PLLs. */
  380. samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
  381. ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
  382. /* Register common internal clocks. */
  383. samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
  384. ARRAY_SIZE(s3c64xx_fixed_rate_clks));
  385. samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
  386. ARRAY_SIZE(s3c64xx_mux_clks));
  387. samsung_clk_register_div(ctx, s3c64xx_div_clks,
  388. ARRAY_SIZE(s3c64xx_div_clks));
  389. samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
  390. ARRAY_SIZE(s3c64xx_gate_clks));
  391. /* Register SoC-specific clocks. */
  392. if (is_s3c6400) {
  393. samsung_clk_register_mux(ctx, s3c6400_mux_clks,
  394. ARRAY_SIZE(s3c6400_mux_clks));
  395. samsung_clk_register_div(ctx, s3c6400_div_clks,
  396. ARRAY_SIZE(s3c6400_div_clks));
  397. samsung_clk_register_gate(ctx, s3c6400_gate_clks,
  398. ARRAY_SIZE(s3c6400_gate_clks));
  399. samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
  400. ARRAY_SIZE(s3c6400_clock_aliases));
  401. } else {
  402. samsung_clk_register_mux(ctx, s3c6410_mux_clks,
  403. ARRAY_SIZE(s3c6410_mux_clks));
  404. samsung_clk_register_div(ctx, s3c6410_div_clks,
  405. ARRAY_SIZE(s3c6410_div_clks));
  406. samsung_clk_register_gate(ctx, s3c6410_gate_clks,
  407. ARRAY_SIZE(s3c6410_gate_clks));
  408. samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
  409. ARRAY_SIZE(s3c6410_clock_aliases));
  410. }
  411. samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
  412. ARRAY_SIZE(s3c64xx_clock_aliases));
  413. samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
  414. ARRAY_SIZE(s3c64xx_clk_regs));
  415. if (!is_s3c6400)
  416. samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
  417. ARRAY_SIZE(s3c6410_clk_regs));
  418. samsung_clk_of_add_provider(np, ctx);
  419. pr_info("%s clocks: apll = %lu, mpll = %lu\n"
  420. "\tepll = %lu, arm_clk = %lu\n",
  421. is_s3c6400 ? "S3C6400" : "S3C6410",
  422. _get_rate("fout_apll"), _get_rate("fout_mpll"),
  423. _get_rate("fout_epll"), _get_rate("armclk"));
  424. }
  425. static void __init s3c6400_clk_init(struct device_node *np)
  426. {
  427. s3c64xx_clk_init(np, 0, 0, true, NULL);
  428. }
  429. CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
  430. static void __init s3c6410_clk_init(struct device_node *np)
  431. {
  432. s3c64xx_clk_init(np, 0, 0, false, NULL);
  433. }
  434. CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);